June 2023 - U-Boot

[PATCH] axi: fix a warning
by Sergei Antonov 20 Jun '23

20 Jun '23

Fix an enum/integer mismatch encountered in 'sandbox_defconfig' build. .../u-boot/drivers/axi/axi-emul-uclass.c:16:5: warning: conflicting types for ‘axi_sandbox_get_emul’ due to enum/integer mismatch; have ‘int(struct udevice *, ulong, enum axi_size_t, struct udevice **)’ {aka ‘int(struct udevice *, long unsigned int, enum axi_size_t, struct udevice **)’} [-Wenum-int-mismatch] 16 | int axi_sandbox_get_emul(struct udevice *bus, ulong address, | ^~~~~~~~~~~~~~~~~~~~ In file included from .../u-boot/drivers/axi/axi-emul-uclass.c:14: .../u-boot/arch/sandbox/include/asm/axi.h:48:5: note: previous declaration of ‘axi_sandbox_get_emul’ with type ‘int(struct udevice *, ulong, uint, struct udevice **)’ {aka ‘int(struct udevice *, long unsigned int, unsigned int, struct udevice **)’} 48 | int axi_sandbox_get_emul(struct udevice *bus, ulong address, uint length, | ^~~~~~~~~~~~~~~~~~~~ Make function declaration match function definition. Cc: Mario Six <mario.six(a)gdsys.cc> Signed-off-by: Sergei Antonov <saproj(a)gmail.com> --- arch/sandbox/include/asm/axi.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/sandbox/include/asm/axi.h b/arch/sandbox/include/asm/axi.h index d483f7b65a02..a93975c6534b 100644 --- a/arch/sandbox/include/asm/axi.h +++ b/arch/sandbox/include/asm/axi.h @@ -7,6 +7,8 @@ #ifndef __asm_axi_h #define __asm_axi_h +#include <axi.h> + #define axi_emul_get_ops(dev) ((struct axi_emul_ops *)(dev)->driver->ops) /** @@ -14,10 +16,10 @@ * @bus: The AXI bus from which to retrieve a emulation device * @address: The address of a transfer that should be handled by a emulation * device - * @length: The data width of a transfer that should be handled by a emulation + * @size: The data width of a transfer that should be handled by a emulation * device * @emulp: Pointer to a buffer receiving the emulation device that handles - * the transfer specified by the address and length parameters + * the transfer specified by the address and size parameters * * To test the AXI uclass, we implement a simple AXI emulation device, which is * a virtual device on a AXI bus that exposes a simple storage interface: When @@ -45,7 +47,7 @@ * Return: 0 of OK, -ENODEV if no device capable of handling the specified * transfer exists or the device could not be retrieved */ -int axi_sandbox_get_emul(struct udevice *bus, ulong address, uint length, +int axi_sandbox_get_emul(struct udevice *bus, ulong address, enum axi_size_t size, struct udevice **emulp); /** * axi_get_store() - Get address of internal storage of a emulated AXI device -- 2.37.2

2 1

[PATCH 1/2] imx: hab: Fix a couple of build warnings with DEBUG enabled
by Marek Vasut 20 Jun '23

20 Jun '23

In case the DEBUG is enabled, these three lines warn about cast of pointer to integer of different size, add the missing casts to fix the warnings. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Heiko Schocher <hs(a)denx.de> Cc: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Cc: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: Ye Li <ye.li(a)nxp.com> --- arch/arm/mach-imx/hab.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index c6747b257c4..439cdaf07a7 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -932,10 +932,10 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, printf("ivt entry = 0x%08x, dcd = 0x%08x, csf = 0x%08x\n", ivt->entry, ivt->dcd, ivt->csf); puts("Dumping IVT\n"); - print_buffer(ivt_addr, (void *)(ivt_addr), 4, 0x8, 0); + print_buffer(ivt_addr, (void *)(uintptr_t)(ivt_addr), 4, 0x8, 0); puts("Dumping CSF Header\n"); - print_buffer(ivt->csf, (void *)(ivt->csf), 4, 0x10, 0); + print_buffer(ivt->csf, (void *)(uintptr_t)(ivt->csf), 4, 0x10, 0); #if !defined(CONFIG_SPL_BUILD) get_hab_status(); @@ -944,7 +944,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, puts("\nCalling authenticate_image in ROM\n"); printf("\tivt_offset = 0x%x\n", ivt_offset); printf("\tstart = 0x%08lx\n", start); - printf("\tbytes = 0x%x\n", bytes); + printf("\tbytes = 0x%lx\n", (ulong)bytes); #endif #ifndef CONFIG_ARM64 -- 2.39.2

3 4

[PATCH] spl: spl_legacy: Add extra address checks
by Marek Vasut 20 Jun '23

20 Jun '23

Check whether the loaded image or entry point does not overlap SPL. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Heiko Schocher <hs(a)denx.de> Cc: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Cc: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: Ye Li <ye.li(a)nxp.com> --- common/spl/spl_legacy.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index 16851c55eb5..b21173baf55 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -7,6 +7,7 @@ #include <image.h> #include <log.h> #include <malloc.h> +#include <asm/sections.h> #include <spl.h> #include <lzma/LzmaTypes.h> @@ -15,6 +16,22 @@ #define LZMA_LEN (1 << 20) +static void spl_parse_legacy_validate(uintptr_t start, uintptr_t size) +{ + uintptr_t spl_start = (uintptr_t)__image_copy_start; + uintptr_t spl_end = (uintptr_t)__image_copy_end; + uintptr_t end = start + size; + + if ((start >= spl_start && start < spl_end) || + (end > spl_start && end <= spl_end) || + (start < spl_start && end >= spl_end) || + (start > end && end > spl_start)) + panic("SPL: Image overlaps SPL\n"); + + if (size > CONFIG_SYS_BOOTM_LEN) + panic("SPL: Image too large\n"); +} + int spl_parse_legacy_header(struct spl_image_info *spl_image, const struct legacy_img_hdr *header) { @@ -58,6 +75,9 @@ int spl_parse_legacy_header(struct spl_image_info *spl_image, "payload image: %32s load addr: 0x%lx size: %d\n", spl_image->name, spl_image->load_addr, spl_image->size); + spl_parse_legacy_validate(spl_image->load_addr, spl_image->size); + spl_parse_legacy_validate(spl_image->entry_point, 0); + return 0; } -- 2.39.2

4 3

Re: [PATCH 1/3] riscv: timer: Update the sifive clint timer driver to support aclint
by Rick Chen 20 Jun '23

20 Jun '23

Hi Bin, > From: Bin Meng <bmeng(a)tinylab.org> > Sent: Monday, June 12, 2023 3:36 PM > To: u-boot(a)lists.denx.de > Cc: Anup Patel <anup(a)brainfault.org>; Atish Patra <atishp(a)atishpatra.org>; Bin Meng <bmeng.cn(a)gmail.com>; Palmer Dabbelt <palmer(a)dabbelt.com>; Paul Walmsley <paul.walmsley(a)sifive.com>; Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com> > Subject: [PATCH 1/3] riscv: timer: Update the sifive clint timer driver to support aclint > > This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. > > The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint timer driver to support ACLINT mtimer device, using a per-driver data field to hold the mtimer offset to the base address encoded in the mtimer node. > > [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc > > Signed-off-by: Bin Meng <bmeng(a)tinylab.org> > --- > > drivers/timer/sifive_clint_timer.c | 16 +++++++++++----- > include/configs/ae350.h | 2 +- > include/configs/qemu-riscv.h | 2 +- > include/configs/sifive-unleashed.h | 2 +- > include/configs/starfive-visionfive2.h | 1 + > 5 files changed, 15 insertions(+), 8 deletions(-) > > diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c > index 939b99d937..be45f17ddf 100644 > --- a/drivers/timer/sifive_clint_timer.c > +++ b/drivers/timer/sifive_clint_timer.c > @@ -12,12 +12,16 @@ > #include <dm/device-internal.h> > #include <linux/err.h> > > +#define CLINT_MTIME_OFFSET 0xbff8 > +#define ACLINT_MTIME_OFFSET 0 > + > /* mtime register */ > -#define MTIME_REG(base) ((ulong)(base) + 0xbff8) > +#define MTIME_REG(base, offset) ((ulong)(base) + (offset)) > > static u64 notrace sifive_clint_get_count(struct udevice *dev) { > - return readq((void __iomem *)MTIME_REG(dev_get_priv(dev))); > + return readq((void __iomem *)MTIME_REG(dev_get_priv(dev), > + dev_get_driver_data(dev))); > } > > #if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) @@ -35,7 +39,8 @@ unsigned long notrace timer_early_get_rate(void) > */ > u64 notrace timer_early_get_count(void) { > - return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE)); > + return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE, > + RISCV_MMODE_TIMEROFF)); > } > #endif > > @@ -53,8 +58,9 @@ static int sifive_clint_probe(struct udevice *dev) } > > static const struct udevice_id sifive_clint_ids[] = { > - { .compatible = "riscv,clint0" }, > - { .compatible = "sifive,clint0" }, > + { .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET }, > + { .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET }, > + { .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET }, > { } > }; > > diff --git a/include/configs/ae350.h b/include/configs/ae350.h index b566ecf296..02c5c80215 100644 > --- a/include/configs/ae350.h > +++ b/include/configs/ae350.h > @@ -8,8 +8,8 @@ > #define __CONFIG_H > > #define RISCV_MMODE_TIMERBASE 0xe6000000 > +#define RISCV_MMODE_TIMEROFF 0xbff8 Why add this for ae350 ? > #define RISCV_MMODE_TIMER_FREQ 60000000 > - > #define RISCV_SMODE_TIMER_FREQ 60000000 > > /* > diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 20135f569e..f6d326bda0 100644 > --- a/include/configs/qemu-riscv.h > +++ b/include/configs/qemu-riscv.h > @@ -11,8 +11,8 @@ > #define CFG_SYS_SDRAM_BASE 0x80000000 > > #define RISCV_MMODE_TIMERBASE 0x2000000 > +#define RISCV_MMODE_TIMEROFF 0xbff8 > #define RISCV_MMODE_TIMER_FREQ 1000000 > - > #define RISCV_SMODE_TIMER_FREQ 1000000 > > /* Environment options */ > diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h > index de3a0dcdd5..f208f5e20d 100644 > --- a/include/configs/sifive-unleashed.h > +++ b/include/configs/sifive-unleashed.h > @@ -14,8 +14,8 @@ > #define CFG_SYS_SDRAM_BASE 0x80000000 > > #define RISCV_MMODE_TIMERBASE 0x2000000 > +#define RISCV_MMODE_TIMEROFF 0xbff8 > #define RISCV_MMODE_TIMER_FREQ 1000000 > - > #define RISCV_SMODE_TIMER_FREQ 1000000 > > /* Environment options */ > diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h > index 93dcc22d36..4ee02b8420 100644 > --- a/include/configs/starfive-visionfive2.h > +++ b/include/configs/starfive-visionfive2.h > @@ -9,6 +9,7 @@ > #define _STARFIVE_VISIONFIVE2_H > > #define RISCV_MMODE_TIMERBASE 0x2000000 > +#define RISCV_MMODE_TIMEROFF 0xbff8 > #define RISCV_MMODE_TIMER_FREQ 4000000 > #define RISCV_SMODE_TIMER_FREQ 4000000

2 1

[PATCH v3 1/3] mmc: Fix MMC_CMD_STOP_TRANSMISSION response type and add comment
by Marek Vasut 20 Jun '23

20 Jun '23

For MMC/eMMC, the MMC_CMD_STOP_TRANSMISSION response is R1 for read transfers and R1b for write transfers per JEDEC Standard No. 84-B51 Page 126 . The response is R1b unconditionally per Physical Layer Simplified Specification Version 9.00. Correct the response type and add a comment about it. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- V2: New patch V3: Account for SD case --- Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> Cc: Hai Pham <hai.pham.ud(a)renesas.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Loic Poulain <loic.poulain(a)linaro.org> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Takeshi Kihara <takeshi.kihara.df(a)renesas.com> --- drivers/mmc/mmc.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 965bc8f0dba..38d85c71402 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -427,7 +427,16 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, if (blkcnt > 1) { cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; cmd.cmdarg = 0; - cmd.resp_type = MMC_RSP_R1b; + /* + * JEDEC Standard No. 84-B51 Page 126 + * CMD12 STOP_TRANSMISSION R1/R1b[3] + * NOTE 3 R1 for read cases and R1b for write cases. + * + * Physical Layer Simplified Specification Version 9.00 + * 7.3.1.3 Detailed Command Description + * CMD12 R1b + */ + cmd.resp_type = IS_SD(mmc) ? MMC_RSP_R1b : MMC_RSP_R1; if (mmc_send_cmd(mmc, &cmd, NULL)) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) pr_err("mmc fail to send stop cmd\n"); -- 2.39.2

2 5

[PATCH] ARM: rmobile: Update little‐endian byte order option in srec_cat command
by Marek Vasut 20 Jun '23

20 Jun '23

From: Hai Pham <hai.pham.ud(a)renesas.com> Since srecord v1.60, option "-Little_Endian_CONSTant" is deprecated. Fix the build warnings by updating little‐endian byte order option in srec_cat command when generating loader header. Reviewed-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud(a)renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- arch/arm/mach-rmobile/Makefile | 55 +++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index fadb6eb0ab6..4eddba53ed2 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -25,6 +25,13 @@ cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \ spl/u-boot-spl.srec: spl/u-boot-spl FORCE $(call if_changed,objcopy) +srec_cat_gte_160 := ${shell expr `srec_cat -VERSION | grep ^srec_cat | sed 's/^.* //g' | cut -f1-2 -d.` \>= "1.60"} +ifeq "$(srec_cat_gte_160)" "1" + srec_cat_le_cmd := "-constant-l-e" +else + srec_cat_le_cmd := "-l-e-constant" +endif + ifneq ($(CONFIG_R8A774C0)$(CONFIG_R8A77990)$(CONFIG_R8A77995),) # # The first 6 generate statements generate the R-Car Gen3 SCIF loader header. @@ -52,34 +59,34 @@ quiet_cmd_srec_cat = SRECCAT $@ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ -offset -0x13fd0 \ -Output_Block_Size 16 \ - -generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \ - -generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \ - -generate 0xe63005d4 0xe63005d8 -l-e-constant 0xe6304000 4 \ - -generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \ - -generate 0xe6301154 0xe6301158 -l-e-constant 0xe6304000 4 \ - -generate 0xe6301264 0xe6301268 -l-e-constant $2 4 \ - -generate 0xe6304000 0xe6304004 -l-e-constant 0xd2bcc000 4 \ - -generate 0xe6304004 0xe6304008 -l-e-constant 0xb26c0400 4 \ - -generate 0xe6304008 0xe630400c -l-e-constant 0xb2720001 4 \ - -generate 0xe630400c 0xe6304010 -l-e-constant 0xb27c0421 4 \ - -generate 0xe6304010 0xe6304014 -l-e-constant 0xb2710402 4 \ - -generate 0xe6304014 0xe6304018 -l-e-constant 0xaa0203e0 4 \ - -generate 0xe6304018 0xe630401c -l-e-constant 0xd28e0003 4 \ - -generate 0xe630401c 0xe6304020 -l-e-constant 0xa8c11424 4 \ - -generate 0xe6304020 0xe6304024 -l-e-constant 0xa8811444 4 \ - -generate 0xe6304024 0xe6304028 -l-e-constant 0xf1004063 4 \ - -generate 0xe6304028 0xe630402c -l-e-constant 0x54ffffaa 4 \ - -generate 0xe630402c 0xe6304030 -l-e-constant 0xd61f0000 4 + -generate 0xe6300400 0xe6300404 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xe630048c 0xe6300490 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xe63005d4 0xe63005d8 $(srec_cat_le_cmd) 0xe6304000 4 \ + -generate 0xe63006e4 0xe63006e8 $(srec_cat_le_cmd) $2 4 \ + -generate 0xe6301154 0xe6301158 $(srec_cat_le_cmd) 0xe6304000 4 \ + -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4 \ + -generate 0xe6304000 0xe6304004 $(srec_cat_le_cmd) 0xd2bcc000 4 \ + -generate 0xe6304004 0xe6304008 $(srec_cat_le_cmd) 0xb26c0400 4 \ + -generate 0xe6304008 0xe630400c $(srec_cat_le_cmd) 0xb2720001 4 \ + -generate 0xe630400c 0xe6304010 $(srec_cat_le_cmd) 0xb27c0421 4 \ + -generate 0xe6304010 0xe6304014 $(srec_cat_le_cmd) 0xb2710402 4 \ + -generate 0xe6304014 0xe6304018 $(srec_cat_le_cmd) 0xaa0203e0 4 \ + -generate 0xe6304018 0xe630401c $(srec_cat_le_cmd) 0xd28e0003 4 \ + -generate 0xe630401c 0xe6304020 $(srec_cat_le_cmd) 0xa8c11424 4 \ + -generate 0xe6304020 0xe6304024 $(srec_cat_le_cmd) 0xa8811444 4 \ + -generate 0xe6304024 0xe6304028 $(srec_cat_le_cmd) 0xf1004063 4 \ + -generate 0xe6304028 0xe630402c $(srec_cat_le_cmd) 0x54ffffaa 4 \ + -generate 0xe630402c 0xe6304030 $(srec_cat_le_cmd) 0xd61f0000 4 else quiet_cmd_srec_cat = SRECCAT $@ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ -Output_Block_Size 16 \ - -generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \ - -generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \ - -generate 0xe63005d4 0xe63005d8 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \ - -generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \ - -generate 0xe6301154 0xe6301158 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \ - -generate 0xe6301264 0xe6301268 -l-e-constant $2 4 + -generate 0xe6300400 0xe6300404 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xe630048c 0xe6300490 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0xe63005d4 0xe63005d8 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \ + -generate 0xe63006e4 0xe63006e8 $(srec_cat_le_cmd) $2 4 \ + -generate 0xe6301154 0xe6301158 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \ + -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4 endif spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin -- 2.39.2

1 0

[PATCH] clk: renesas: Tear clock controller down last before booting OS
by Marek Vasut 20 Jun '23

20 Jun '23

Once all the other drivers got torn down in preparation for the OS to start, tear down the clock controller last. The clock controller must be torn down last as some of the clock which get turned off might have still been needed during the teardown stage of the other drivers. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa(a)renesas.com> Signed-off-by: Hai Pham <hai.pham.ud(a)renesas.com> --- drivers/clk/renesas/clk-rcar-gen3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index c8a5512b65e..0d274bb986e 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -526,6 +526,7 @@ U_BOOT_DRIVER(clk_gen3) = { .ops = &gen3_clk_ops, .probe = gen3_clk_probe, .remove = gen3_clk_remove, + .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL, }; static int gen3_reset_assert(struct reset_ctl *reset_ctl) @@ -565,6 +566,7 @@ U_BOOT_DRIVER(rst_gen3) = { .name = "rst_gen3", .id = UCLASS_RESET, .ops = &rst_gen3_ops, + .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL, }; int gen3_cpg_bind(struct udevice *parent) -- 2.39.2

1 0

[PATCH 1/2] ARM: dts: renesas: Clean up R8A779G0 V4H RPC SPI DT node
by Marek Vasut 20 Jun '23

20 Jun '23

Use the phandle reference to &rpc node in arch/arm/dts/r8a779g0.dtsi and remove properties which are already in arch/arm/dts/r8a779g0.dtsi. No functional change and no resulting DT change. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)mailbox.org> --- arch/arm/dts/r8a779g0-u-boot.dtsi | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi index 150657fad54..cc8becac996 100644 --- a/arch/arm/dts/r8a779g0-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-u-boot.dtsi @@ -7,20 +7,10 @@ #include "r8a779x-u-boot.dtsi" -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a779g0-rpc-if", "renesas,rcar-gen4-rpc-if"; - reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 629>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 629>; - bank-width = <2>; - num-cs = <1>; - status = "disabled"; - }; - }; +&rpc { + reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>; + bank-width = <2>; + num-cs = <1>; }; &extalr_clk { -- 2.39.2

1 1

[PATCH v3 0/6] corstone1000: fwu metadata and GPT
by Rui Miguel Silva 19 Jun '23

19 Jun '23

Now that the nvmxip block driver is merged we can add on top of it the platform code to use GPT and FWU metadata in the Corstone1000. But first, push 2 fixes that are needed to make all this work: - move nvmxip header to include - setup fwu metadata structures as packed (we have a 32bit writer - Secure enclave Cortex-M0 and a 64bit reader host Cortex-A35) Cheers, Rui v2 [1]-> v3: Tom Rini: - fix definition of __packed compilation issue after merge of mkfwumdata tool. v1 [0]-> v2: Ilias: - add Reviewed-by tag in patch 1/6 Heinrich: - fix test include nvmxip header after the move to include/ in patch 2/6 [0]: https://lore.kernel.org/u-boot/20230502131200.2551513-1-rui.silva@linaro.or… [1]: https://lore.kernel.org/u-boot/20230529140229.3225090-1-rui.silva@linaro.or… Rui Miguel Silva (6): fwu_metadata: make sure structures are packed nvmxip: move header to include corstone1000: add fwu-metadata store info corstone1000: add boot index corstone1000: set kernel_addr based on boot_idx corstone1000: add nvmxip, fwu-mdata and gpt options arch/arm/dts/corstone1000.dtsi | 7 ++- board/armltd/corstone1000/corstone1000.c | 73 +++++++++++++++++++++- board/armltd/corstone1000/corstone1000.env | 10 +-- configs/corstone1000_defconfig | 14 ++++- include/fwu_mdata.h | 7 ++- {drivers/mtd/nvmxip => include}/nvmxip.h | 0 test/dm/nvmxip.c | 2 +- 7 files changed, 97 insertions(+), 16 deletions(-) rename {drivers/mtd/nvmxip => include}/nvmxip.h (100%) -- 2.41.0

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[PATCH] global: Use proper project name U-Boot (next)
by Michal Simek 19 Jun '23

19 Jun '23

Use proper project name in DTs, messages and READMEs. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- Sending this separately because changing outputs/names can break automated tools that's why better to do it on smaller series. --- arch/arm/dts/am335x-igep0033.dtsi | 2 +- arch/arm/dts/armada-3720-db.dts | 2 +- board/armadeus/opos6uldev/opos6uldev.env | 8 ++++---- board/freescale/common/fsl_chain_of_trust.c | 2 +- board/freescale/ls1012afrdm/README | 4 ++-- board/freescale/ls1012aqds/README | 4 ++-- board/freescale/ls1012ardb/README | 8 ++++---- board/imgtec/boston/checkboard.c | 2 +- include/dt-bindings/memory/bcm-ns3-mc.h | 2 +- 9 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/dts/am335x-igep0033.dtsi b/arch/arm/dts/am335x-igep0033.dtsi index ad57c74fafc4..4488dcce0123 100644 --- a/arch/arm/dts/am335x-igep0033.dtsi +++ b/arch/arm/dts/am335x-igep0033.dtsi @@ -175,7 +175,7 @@ }; partition@1 { - label = "U-boot"; + label = "U-Boot"; reg = <0x00080000 0x001e0000>; }; diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts index 3e5789f37206..1ee92406b74c 100644 --- a/arch/arm/dts/armada-3720-db.dts +++ b/arch/arm/dts/armada-3720-db.dts @@ -180,7 +180,7 @@ reg = <0x0 0x200000>; }; partition@200000 { - label = "U-boot Env"; + label = "U-Boot Env"; reg = <0x200000 0x10000>; }; partition@210000 { diff --git a/board/armadeus/opos6uldev/opos6uldev.env b/board/armadeus/opos6uldev/opos6uldev.env index 585f28ca8587..f90029787104 100644 --- a/board/armadeus/opos6uldev/opos6uldev.env +++ b/board/armadeus/opos6uldev/opos6uldev.env @@ -42,8 +42,8 @@ flash_uboot_spl= setexpr sz ${filesize} / 0x200; setexpr sz ${sz} + 1; if mmc write ${loadaddr} 0x2 ${sz}; then - echo Flashing of U-boot SPL succeed; - else echo Flashing of U-boot SPL failed; + echo Flashing of U-Boot SPL succeed; + else echo Flashing of U-Boot SPL failed; fi; fi; download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img @@ -52,8 +52,8 @@ flash_uboot_img= setexpr sz ${filesize} / 0x200; setexpr sz ${sz} + 1; if mmc write ${loadaddr} 0x8a ${sz}; then - echo Flashing of U-boot image succeed; - else echo Flashing of U-boot image failed; + echo Flashing of U-Boot image succeed; + else echo Flashing of U-Boot image failed; fi; fi; update_uboot=run download_uboot_spl flash_uboot_spl diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index b47ce052516e..87ed814d6a2a 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -127,7 +127,7 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) &img_addr); if (res == 0) - printf("SPL: Validation of U-boot successful\n"); + printf("SPL: Validation of U-Boot successful\n"); } #ifdef CONFIG_SPL_FRAMEWORK diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README index 382b668fbec6..e60ed606ec13 100644 --- a/board/freescale/ls1012afrdm/README +++ b/board/freescale/ls1012afrdm/README @@ -52,7 +52,7 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4020_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README index c1956f9fd78a..e9b80cad506a 100644 --- a/board/freescale/ls1012aqds/README +++ b/board/freescale/ls1012aqds/README @@ -53,7 +53,7 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4020_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README index 5b6f306a1d9d..26b0485a7f89 100644 --- a/board/freescale/ls1012ardb/README +++ b/board/freescale/ls1012ardb/README @@ -48,8 +48,8 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4020_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000 @@ -90,8 +90,8 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4030_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4030_0000 PPA FIT image | 2MB | 0x4040_0000 PFE firmware | 20K | 0x00a0_0000 Linux ITB | ~53MB | 0x4100_0000 diff --git a/board/imgtec/boston/checkboard.c b/board/imgtec/boston/checkboard.c index 1b8a47d2549f..c246a7b9d455 100644 --- a/board/imgtec/boston/checkboard.c +++ b/board/imgtec/boston/checkboard.c @@ -16,7 +16,7 @@ int checkboard(void) { u32 changelist; - lowlevel_display("U-boot "); + lowlevel_display("U-Boot "); printf("Board: MIPS Boston\n"); diff --git a/include/dt-bindings/memory/bcm-ns3-mc.h b/include/dt-bindings/memory/bcm-ns3-mc.h index 84795ec27a42..d2478d9ae318 100644 --- a/include/dt-bindings/memory/bcm-ns3-mc.h +++ b/include/dt-bindings/memory/bcm-ns3-mc.h @@ -28,7 +28,7 @@ #define BCM_NS3_MEM_SHARE_START 0x8d000000 #define BCM_NS3_MEM_SHARE_LEN 0x020fffff -/* ATF/U-boot/Linux error logs */ +/* ATF/U-Boot/Linux error logs */ #define BCM_NS3_MEM_ELOG_START 0x8f113000 #define BCM_NS3_MEM_ELOG_LEN 0x00100000 -- 2.36.1

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