April 2023 - U-Boot

[PATCH v2 0/9] serial: msm-geni: fix UART baudrate on modern platforms
by Vladimir Zapolskiy 12 Apr '23

12 Apr '23

The changeset touches Qualcomm platforms, it adds a new quite trivial misc wrapper driver to be accessed by GENI UART to get information about a proper clock divisor. The change does not intend to break any currently supported Qualcomm platforms, there should be no need to update board config or dts files. Changes from v1 to v2: * fixes according to the code review by Konrad, * added two changes developed by Konrad to the series, * removed .bind from the GENI SE wrapper driver, * minor fix in MSM GENI serial driver Kconfig to match the new changes, * changed dts files of SDM845 powered boards by adding GENI SE wrapper. Konrad Dybcio (2): serial: msm-geni: Always bind before relocation serial: msm-geni: Use upstream Linux bindings Vladimir Zapolskiy (7): misc: add Qualcomm GENI SE QUP device driver serial: msm-geni: remove redundant includes serial: msm-geni: remove invalid se-clk clock name serial: msm-geni: fix code indentation serial: msm-geni: fix a compile time warning from msm_serial_setbrg() serial: msm-geni: correct oversampling value based on QUP hardware revision arm: dts: sdm845: add GENI SE QUP device tree node arch/arm/dts/dragonboard845c.dts | 2 +- arch/arm/dts/sdm845.dtsi | 25 +++++--- arch/arm/dts/starqltechn.dts | 2 +- .../serial/msm-geni-serial.txt | 2 +- drivers/misc/Kconfig | 7 +++ drivers/misc/Makefile | 1 + drivers/misc/qcom-geni-se.c | 41 ++++++++++++ drivers/serial/Kconfig | 2 + drivers/serial/serial_msm_geni.c | 62 +++++++++++++------ 9 files changed, 113 insertions(+), 31 deletions(-) create mode 100644 drivers/misc/qcom-geni-se.c -- 2.33.0

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[PATCH v2 00/18] Migration to using binman to generate
by Neha Malcom Francis 12 Apr '23

12 Apr '23

This series aims to eliminate the use of additional custom repositories such as k3-image-gen (K3 Image Generation) repo that was plumbed into the U-Boot build flow to generate boot images for TI K3 platform devices. And instead, we move towards using binman that aligns better with the community standard build flow. This series uses binman for all K3 platforms supported on U-Boot currently; both HS (High Security) and GP (General Purpose) devices. Background on using k3-image-gen: * TI K3 devices require a SYSFW (System Firmware) image consisting of a signed system firmware image and board configuration binaries, this is needed to bring up system firmware during U-Boot R5 SPL startup. * Board configuration data contain board-specific information such as resource management, power management and security. Series intends to use binman to take over the packaging and signing for the R5 bootloader images tiboot3.bin (and sysfw.itb, for non-combined boot flow) instead of k3-image-gen. Series also packages the A72/A53 bootloader images (tispl.bin and u-boot.img) using ATF, OPTEE and DM (Device Manager) Changes in v2: - removed all external scripts - created ti-board-config etype to support generation of board config binaries - created ti-secure and ti-secure-rom etypes to handle signing instead of using external TI_SECURE_DEV_PKG - updated openssl btool to support x509 certificate generation - dropped Makefile changes to obtain external binary components, moving to using BINMAN_INDIRS to achieve the same Neha Malcom Francis (18): binman: Add support for generating TI Board config binaries binman: ti-secure: Add support for TI signing ti: sysfw: tiboot3: Add support for packaging sysfw.itb and tiboot3.bin j721e: schema: yaml: Add general schema and J721E board config files j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img j7200: yaml: Add J7200 board config files j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img am65x: yaml: Add AM65x board config files am65: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img config: am64x: Add board config for AM64x am64x: dts: binman: Package tiboot3.bin, tispl.bin u-boot.img j721s2: yaml: Add board config for J721S2 j721s2: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img am62: yaml: Add board config for AM62 am625: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img am62a: yaml: Add board config for AM62ax am62a: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img k3: tools: config.mk: Update makefile and remove scripts arch/arm/dts/k3-am625-r5-sk.dts | 1 + arch/arm/dts/k3-am625-sk-binman.dtsi | 472 +++ arch/arm/dts/k3-am625-sk-u-boot.dtsi | 2 + arch/arm/dts/k3-am62a-sk-binman.dtsi | 472 +++ arch/arm/dts/k3-am62a7-r5-sk.dts | 1 + arch/arm/dts/k3-am62a7-sk.dts | 1 + arch/arm/dts/k3-am642-evm-u-boot.dtsi | 2 + arch/arm/dts/k3-am642-r5-evm.dts | 1 + arch/arm/dts/k3-am64x-binman.dtsi | 521 +++ arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 1 + .../dts/k3-am654-r5-base-board-u-boot.dtsi | 1 + arch/arm/dts/k3-am65x-binman.dtsi | 543 +++ arch/arm/dts/k3-j7200-binman.dtsi | 471 +++ .../k3-j7200-common-proc-board-u-boot.dtsi | 2 + arch/arm/dts/k3-j721e-binman.dtsi | 634 ++++ .../k3-j721e-common-proc-board-u-boot.dtsi | 1 + .../arm/dts/k3-j721e-r5-common-proc-board.dts | 1 + arch/arm/dts/k3-j721s2-binman.dtsi | 474 +++ .../k3-j721s2-common-proc-board-u-boot.dtsi | 2 + .../dts/k3-j721s2-r5-common-proc-board.dts | 1 + arch/arm/mach-k3/config.mk | 126 +- board/ti/am62ax/Kconfig | 2 + board/ti/am62ax/board-cfg.yaml | 36 + board/ti/am62ax/pm-cfg.yaml | 12 + board/ti/am62ax/rm-cfg.yaml | 1151 +++++++ board/ti/am62ax/sec-cfg.yaml | 375 +++ board/ti/am62x/Kconfig | 2 + board/ti/am62x/board-cfg.yaml | 36 + board/ti/am62x/pm-cfg.yaml | 12 + board/ti/am62x/rm-cfg.yaml | 1088 +++++++ board/ti/am62x/sec-cfg.yaml | 375 +++ board/ti/am64x/Kconfig | 2 + board/ti/am64x/board-cfg.yaml | 37 + board/ti/am64x/pm-cfg.yaml | 12 + board/ti/am64x/rm-cfg.yaml | 1400 ++++++++ board/ti/am64x/sec-cfg.yaml | 378 +++ board/ti/am65x/Kconfig | 2 + board/ti/am65x/board-cfg.yaml | 36 + board/ti/am65x/pm-cfg.yaml | 12 + board/ti/am65x/rm-cfg.yaml | 2068 ++++++++++++ board/ti/am65x/sec-cfg.yaml | 375 +++ board/ti/common/schema.yaml | 355 ++ board/ti/j721e/Kconfig | 4 + board/ti/j721e/board-cfg.yaml | 37 + board/ti/j721e/board-cfg_j7200.yaml | 36 + board/ti/j721e/pm-cfg.yaml | 13 + board/ti/j721e/pm-cfg_j7200.yaml | 12 + board/ti/j721e/rm-cfg.yaml | 2757 ++++++++++++++++ board/ti/j721e/rm-cfg_j7200.yaml | 2065 ++++++++++++ board/ti/j721e/sec-cfg.yaml | 379 +++ board/ti/j721e/sec-cfg_j7200.yaml | 378 +++ board/ti/j721s2/Kconfig | 2 + board/ti/j721s2/board-cfg.yaml | 37 + board/ti/j721s2/pm-cfg.yaml | 12 + board/ti/j721s2/rm-cfg.yaml | 2901 +++++++++++++++++ board/ti/j721s2/sec-cfg.yaml | 375 +++ board/ti/keys/custMpk.pem | 51 + board/ti/keys/ti-degenerate-key.pem | 10 + scripts/Makefile.spl | 2 + tools/binman/btool/openssl.py | 244 ++ tools/binman/entries.rst | 75 + tools/binman/etype/ti_board_config.py | 246 ++ tools/binman/etype/ti_secure.py | 83 + tools/binman/etype/ti_secure_rom.py | 233 ++ tools/binman/etype/x509_cert.py | 87 +- tools/binman/ftest.py | 57 + tools/binman/test/277_ti_board_cfg.dts | 11 + .../binman/test/278_ti_board_cfg_combined.dts | 25 + tools/binman/test/279_ti_secure.dts | 17 + tools/binman/test/280_ti_secure_rom.dts | 17 + .../test/281_ti_secure_rom_combined.dts | 25 + tools/binman/test/yaml/config.yaml | 11 + tools/binman/test/yaml/schema.yaml | 26 + tools/k3_fit_atf.sh | 123 - tools/k3_gen_x509_cert.sh | 262 -- 75 files changed, 21634 insertions(+), 475 deletions(-) create mode 100644 arch/arm/dts/k3-am625-sk-binman.dtsi create mode 100644 arch/arm/dts/k3-am62a-sk-binman.dtsi create mode 100644 arch/arm/dts/k3-am64x-binman.dtsi create mode 100644 arch/arm/dts/k3-am65x-binman.dtsi create mode 100644 arch/arm/dts/k3-j7200-binman.dtsi create mode 100644 arch/arm/dts/k3-j721e-binman.dtsi create mode 100644 arch/arm/dts/k3-j721s2-binman.dtsi create mode 100644 board/ti/am62ax/board-cfg.yaml create mode 100644 board/ti/am62ax/pm-cfg.yaml create mode 100644 board/ti/am62ax/rm-cfg.yaml create mode 100644 board/ti/am62ax/sec-cfg.yaml create mode 100644 board/ti/am62x/board-cfg.yaml create mode 100644 board/ti/am62x/pm-cfg.yaml create mode 100644 board/ti/am62x/rm-cfg.yaml create mode 100644 board/ti/am62x/sec-cfg.yaml create mode 100644 board/ti/am64x/board-cfg.yaml create mode 100644 board/ti/am64x/pm-cfg.yaml create mode 100644 board/ti/am64x/rm-cfg.yaml create mode 100644 board/ti/am64x/sec-cfg.yaml create mode 100644 board/ti/am65x/board-cfg.yaml create mode 100644 board/ti/am65x/pm-cfg.yaml create mode 100644 board/ti/am65x/rm-cfg.yaml create mode 100644 board/ti/am65x/sec-cfg.yaml create mode 100644 board/ti/common/schema.yaml create mode 100644 board/ti/j721e/board-cfg.yaml create mode 100644 board/ti/j721e/board-cfg_j7200.yaml create mode 100644 board/ti/j721e/pm-cfg.yaml create mode 100644 board/ti/j721e/pm-cfg_j7200.yaml create mode 100644 board/ti/j721e/rm-cfg.yaml create mode 100644 board/ti/j721e/rm-cfg_j7200.yaml create mode 100644 board/ti/j721e/sec-cfg.yaml create mode 100644 board/ti/j721e/sec-cfg_j7200.yaml create mode 100644 board/ti/j721s2/board-cfg.yaml create mode 100644 board/ti/j721s2/pm-cfg.yaml create mode 100644 board/ti/j721s2/rm-cfg.yaml create mode 100644 board/ti/j721s2/sec-cfg.yaml create mode 100644 board/ti/keys/custMpk.pem create mode 100644 board/ti/keys/ti-degenerate-key.pem create mode 100644 tools/binman/etype/ti_board_config.py create mode 100644 tools/binman/etype/ti_secure.py create mode 100644 tools/binman/etype/ti_secure_rom.py create mode 100644 tools/binman/test/277_ti_board_cfg.dts create mode 100644 tools/binman/test/278_ti_board_cfg_combined.dts create mode 100644 tools/binman/test/279_ti_secure.dts create mode 100644 tools/binman/test/280_ti_secure_rom.dts create mode 100644 tools/binman/test/281_ti_secure_rom_combined.dts create mode 100644 tools/binman/test/yaml/config.yaml create mode 100644 tools/binman/test/yaml/schema.yaml delete mode 100755 tools/k3_fit_atf.sh delete mode 100755 tools/k3_gen_x509_cert.sh -- 2.34.1

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[PATCH v3] ARM: dts: imx7d-sdb-u-boot: Fix usdhc1 UHS operation
by Fabio Estevam 12 Apr '23

12 Apr '23

From: Fabio Estevam <festevam(a)denx.de> Commit 1a7904fdfa7d ("mmc: fsl_esdhc_imx: Use esdhc_soc_data flags to set host caps") exposed the following SD card error: U-Boot 2023.04-00652-g487e42f7bc5e (Apr 05 2023 - 22:14:21 -0300) CPU: Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 35C Reset cause: POR Model: Freescale i.MX7 SabreSD Board Board: i.MX7D SABRESD in non-secure mode DRAM: 1 GiB Core: 100 devices, 19 uclasses, devicetree: separate PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... Card did not respond to voltage select! : -110 *** Warning - No block device, using default environment The reason of the problem, as explained by Ye Li: "When UHS is enabled in defconfig, the usdhc1 node in imx7d-sdb.dts does not configure pad for VSELECT, also the data pad should be set to 100Mhz/200Mhz pin states." Apply these changes into u-boot.dtsi for now. When these changes reach the Linux mainline imx7d-sdb, they can be dropped from u-boot.dtsi. This fixes UHS mode on the imx7d-sdb board. Suggested-by: Ye Li <ye.li(a)nxp.com> Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- Changes since v2: - Fixed the devicetree instead of the imx sdhci driver (Ye Li). arch/arm/dts/imx7d-sdb-u-boot.dtsi | 51 ++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi index b78358fa1397..913127b5e3c2 100644 --- a/arch/arm/dts/imx7d-sdb-u-boot.dtsi +++ b/arch/arm/dts/imx7d-sdb-u-boot.dtsi @@ -5,3 +5,54 @@ &usbotg1 { dr_mode = "peripheral"; }; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; +}; + +&pinctrl_uart1 { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; +}; + +&iomuxc { + pinctrl_usdhc1_gpio: usdhc1gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; +}; -- 2.34.1

1 0

[PATCH v2] mmc: fsl_esdhc: Do not set UHS_CAPS based on CONFIG_MMC_UHS_SUPPORT
by Fabio Estevam 12 Apr '23

12 Apr '23

From: Fabio Estevam <festevam(a)denx.de> Since commit 1a7904fdfa7d ("mmc: fsl_esdhc_imx: Use esdhc_soc_data flags to set host caps") the following SD card error is observed on an imx7d-sdb board: U-Boot 2023.04-00652-g487e42f7bc5e (Apr 05 2023 - 22:14:21 -0300) CPU: Freescale i.MX7D rev1.0 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 35C Reset cause: POR Model: Freescale i.MX7 SabreSD Board Board: i.MX7D SABRESD in non-secure mode DRAM: 1 GiB Core: 100 devices, 19 uclasses, devicetree: separate PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... Card did not respond to voltage select! : -110 *** Warning - No block device, using default environment Setting UHS_CAPS only based on the CONFIG_MMC_UHS_SUPPORT config option is not correct because UHS_CAPS has the following definition: #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \ MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \ MMC_CAP(UHS_DDR50)) and the SD card may not necessarily support all these modes. Remove the UHS_CAPS setting to fix the SD card regression. Fixes: 1a7904fdfa7d ("mmc: fsl_esdhc_imx: Use esdhc_soc_data flags to set host caps") Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- Changes since v1: - Remove setting UHS_CAPS completely. drivers/mmc/fsl_esdhc_imx.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 66caf683f7..5e7d9f41b6 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1258,13 +1258,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, esdhc_write32(&regs->tuning_ctrl, val); } - /* - * UHS doesn't have explicit ESDHC flags, so if it's - * not supported, disable it in config. - */ - if (CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)) - cfg->host_caps |= UHS_CAPS; - if (CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)) { if (priv->flags & ESDHC_FLAG_HS200) cfg->host_caps |= MMC_CAP(MMC_HS_200); -- 2.34.1

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[PATCH v4 1/5] ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB 2.0 host
by Eugen Hristev 12 Apr '23

12 Apr '23

Add USB 2.0 host nodes and PHYs. Co-developed-by: William Wu <william.wu(a)rock-chips.com> Signed-off-by: William Wu <william.wu(a)rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev(a)collabora.com> --- Changes in v4: - removed u-boot,dm-spl on regulator which was useless - moved usb nodes to rk3588s-u-boot-dtsi Changes in v2,v3: - none arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 82 +++++++++++++++++++++++ arch/arm/dts/rk3588s-u-boot.dtsi | 86 +++++++++++++++++++++++++ 2 files changed, 168 insertions(+) diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index bee4c32e8965..93942b105c3d 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -4,6 +4,9 @@ */ #include "rk3588-u-boot.dtsi" +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> / { aliases { @@ -13,6 +16,18 @@ chosen { u-boot,spl-boot-order = &sdmmc; }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; }; &sdmmc { @@ -20,3 +35,70 @@ bootph-pre-ram; status = "okay"; }; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&usb_host0_ehci { + companion = <&usb_host0_ohci>; + phys = <&u2phy2_host>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb_host0_ohci { + phys = <&u2phy2_host>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy2_grf { + status = "okay"; +}; + +&u2phy2 { + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; + clock-output-names = "usb480m_phy2"; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host1_ehci { + companion = <&usb_host1_ohci>; + phys = <&u2phy3_host>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb_host1_ohci { + phys = <&u2phy3_host>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy3_grf { + status = "okay"; +}; + +&u2phy3 { + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; + clock-output-names = "usb480m_phy3"; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 1e225d71efc2..fb1b802fd273 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -12,12 +12,98 @@ status = "okay"; }; + usb_host0_ehci: usb@fc800000 { + compatible = "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + pmu1_grf: syscon@fd58a000 { bootph-all; compatible = "rockchip,rk3588-pmu1-grf", "syscon"; reg = <0x0 0xfd58a000 0x0 0x2000>; }; + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + sdmmc: mmc@fe2c0000 { compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2c0000 0x0 0x4000>; -- 2.34.1

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[PATCH v4 0/3] Add StarFive JH7110 PCIe drvier support
by Minda Chen 12 Apr '23

12 Apr '23

This patchset needs to apply after patchset in [1]. These PCIe series patches are based on the JH7110 RISC-V SoC and VisionFive V2 board. [1] https://patchwork.ozlabs.org/project/uboot/cover/20230329034224.26545-1-yan… The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init. The PCIe dts configuation includes all these setting. The PCIe drivers codes has been tested on the VisionFive V2 boards. The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter. previous patch version v1: https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-min… v2: https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.95730-1-min… v3: https://patchwork.ozlabs.org/project/uboot/cover/20230329100143.10724-1-min… changes v4 patch 1 1. Remove the IDS_REVISION_ID macros. 2. Replace sec_busno to first_busno in starfive_pcie 3. Remove starfive_pcie_off_conf function. 4. Replace "imply" to "depends on" in PCIe Kconfig. 5 .Check sec_busno in starfive_pcie_addr_valid. v3 patch 1 1. remove the read vendor ID delay 2. remove starfive_pcie_hide_rc_bar function. do not hide host bridge BAR write. 3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros. 4. Add comments for bus and address limitation reason in function starfive_pcie_addr_valid 5. Change the multiple line comments in Line 373 6. Using gpio_request_by_name to get PCIe reset gpio,and using dm_gpio_set_value set GPIO value. patch 2 1. support PCIeboth 12a and 13b vf2 board. patch 3 1. reset dts change to reset-gpio. v2 1. remove clock commit. The pcie clocks change has been includeded in [1]. 2. Using GENMASK marco1 in patch1. 3. remove the syscon dts node in patch3. The syscon dts dts node has been included in [1]. --- Mason Huo (3): starfive: pci: Add StarFive JH7110 pcie driver configs: starfive-jh7110: Add support for PCIe host driver riscv: dts: starfive: Enable PCIe host controller .../dts/jh7110-starfive-visionfive-2.dtsi | 11 + arch/riscv/dts/jh7110.dtsi | 74 +++ configs/starfive_visionfive2_12a_defconfig | 10 + configs/starfive_visionfive2_13b_defconfig | 10 + drivers/pci/Kconfig | 9 + drivers/pci/Makefile | 1 + drivers/pci/pcie_starfive_jh7110.c | 465 ++++++++++++++++++ 7 files changed, 580 insertions(+) create mode 100644 drivers/pci/pcie_starfive_jh7110.c base-commit: 41a88ad529b3943b1e465846eb24fe2c29203e35 prerequisite-patch-id: a84452ba131408ff842b65ae19a3a05f64b3ff60 prerequisite-patch-id: 4abb46d56dbaf36017b2866688f31a73c2cacd0d prerequisite-patch-id: ef5e9d61f7392c7d2e5321aa8a10996ca8eae5fc prerequisite-patch-id: 26dfdb401d680ecd9449acf09131cf4790e987b7 prerequisite-patch-id: a0cfa5d8cdb49bbe9d4739afa90991f882950881 prerequisite-patch-id: 61ceecb41cfd9029bfb267f7b7c5330a2d7e5edc prerequisite-patch-id: d834ece14ffb525b8c3e661e78736692f33fca9b prerequisite-patch-id: 88c9f9637335fdc4107d42db67b9110c9b73ead3 prerequisite-patch-id: ebc26ed3f97f7babc0fc805152acb578f5eff922 prerequisite-patch-id: e85a9ca22facac4d5b5562a2708b7332478d6db4 prerequisite-patch-id: ff5bd799e4cb905fef6cf1cd0ce757980e1d34b7 prerequisite-patch-id: a341d4e8a8e25cb711309123939235fcb3c10c1a prerequisite-patch-id: 749e4eafb431857ee2bec4ac8e78a682f6a57588 prerequisite-patch-id: d4a3666ce2e7135402537cea60e9e6f0435230bf prerequisite-patch-id: fa8ad1bfce7d6ab74ad63ff8d31dff3c2ccb5e43 prerequisite-patch-id: cc352634b8dfaf2d4243819362326a579e010c94 prerequisite-patch-id: 8e0fa3d987020ca06e22401bc4c69f834c38c3dc -- 2.17.1

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[PATCH] watchdog: ulp_wdog: guard reset_cpu with condition check
by Peng Fan (OSS) 12 Apr '23

12 Apr '23

From: Peng Fan <peng.fan(a)nxp.com> There will be build error if CONFIG_SYSRESET is enabled, so guard the reset_cpu with condition check here Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- drivers/watchdog/ulp_wdog.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index c21aa3af55f..0eea04ed2c6 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -122,6 +122,7 @@ void hw_watchdog_init(void) ulp_watchdog_init(wdog, CONFIG_WATCHDOG_TIMEOUT_MSECS); } +#if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; @@ -159,6 +160,7 @@ void reset_cpu(void) while (1); } +#endif static int ulp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { -- 2.36.0

3 2

[PATCH v4 1/2] regulator: implement basic reference counter
by Eugen Hristev 12 Apr '23

12 Apr '23

Some devices share a regulator supply, when the first one will request regulator disable, the second device will have it's supply cut off before graciously shutting down. Hence there will be timeouts and other failed operations. Implement a reference counter mechanism similar with what is done in Linux, to keep track of enable and disable requests, and only disable the regulator when the last of the consumers has requested shutdown. Signed-off-by: Eugen Hristev <eugen.hristev(a)collabora.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v4: - add documentation for error codes Changes in v3: - add error return codes Changes in v2: - add info in header regarding the function drivers/power/regulator/regulator_common.c | 22 ++++++++++++++++++++++ drivers/power/regulator/regulator_common.h | 21 +++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c index 93d8196b381e..484a4fc31ef7 100644 --- a/drivers/power/regulator/regulator_common.c +++ b/drivers/power/regulator/regulator_common.c @@ -73,6 +73,23 @@ int regulator_common_set_enable(const struct udevice *dev, return 0; } + /* If previously enabled, increase count */ + if (enable && dev_pdata->enable_count > 0) { + dev_pdata->enable_count++; + return -EALREADY; + } + + if (!enable) { + if (dev_pdata->enable_count > 1) { + /* If enabled multiple times, decrease count */ + dev_pdata->enable_count--; + return -EBUSY; + } else if (!dev_pdata->enable_count) { + /* If already disabled, do nothing */ + return -EALREADY; + } + } + ret = dm_gpio_set_value(&dev_pdata->gpio, enable); if (ret) { pr_err("Can't set regulator : %s gpio to: %d\n", dev->name, @@ -87,5 +104,10 @@ int regulator_common_set_enable(const struct udevice *dev, if (!enable && dev_pdata->off_on_delay_us) udelay(dev_pdata->off_on_delay_us); + if (enable) + dev_pdata->enable_count++; + else + dev_pdata->enable_count--; + return 0; } diff --git a/drivers/power/regulator/regulator_common.h b/drivers/power/regulator/regulator_common.h index c10492f01675..0faab447d099 100644 --- a/drivers/power/regulator/regulator_common.h +++ b/drivers/power/regulator/regulator_common.h @@ -13,6 +13,7 @@ struct regulator_common_plat { struct gpio_desc gpio; /* GPIO for regulator enable control */ unsigned int startup_delay_us; unsigned int off_on_delay_us; + unsigned int enable_count; }; int regulator_common_of_to_plat(struct udevice *dev, @@ -20,6 +21,26 @@ int regulator_common_of_to_plat(struct udevice *dev, char *enable_gpio_name); int regulator_common_get_enable(const struct udevice *dev, struct regulator_common_plat *dev_pdata); +/* + * Enable or Disable a regulator + * + * This is a reentrant function and subsequent calls that enable will + * increase an internal counter, and disable calls will decrease the counter. + * The actual resource will be enabled when the counter gets to 1 coming from 0, + * and disabled when it reaches 0 coming from 1. + * + * @dev: regulator device + * @dev_pdata: Platform data + * @enable: bool indicating whether to enable or disable the regulator + * @return: + * 0 on Success + * -EBUSY if the regulator cannot be disabled because it's requested by + * another device + * -EALREADY if the regulator has already been enabled or has already been + * disabled + * -EACCES if there is no possibility to enable/disable the regulator + * -ve on different error situation + */ int regulator_common_set_enable(const struct udevice *dev, struct regulator_common_plat *dev_pdata, bool enable); -- 2.34.1

2 4

[PATCH] cmd: sf/nand: Print and return failure when 0 length is passed
by Ashok Reddy Soma 12 Apr '23

12 Apr '23

For sf commands, when '0' length is passed for erase, update, write or read, we might see undesired results. Ideally '0' length means nothing to do. So print 'size is 0' and return cmd failure when length '0' is passed to sf commands. Samething applies for nand commands also. Example: ZynqMP> sf erase 0 0 'size is 0' ZynqMP> sf write 10000 0 0 'size is 0' ZynqMP> sf read 10000 0 0 'size is 0' ZynqMP> sf update 1000 10000 0 'size is 0' ZynqMP> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)amd.com> --- cmd/legacy-mtd-utils.c | 5 +++++ cmd/sf.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/cmd/legacy-mtd-utils.c b/cmd/legacy-mtd-utils.c index ac7139f84d..7b49bfd858 100644 --- a/cmd/legacy-mtd-utils.c +++ b/cmd/legacy-mtd-utils.c @@ -88,6 +88,11 @@ int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, return -1; } + if (*size == 0) { + printf("'size is 0'\n"); + return -1; + } + print: printf("device %d ", *idx); if (*size == chipsize) diff --git a/cmd/sf.c b/cmd/sf.c index 11b9c25896..46b5475fe8 100644 --- a/cmd/sf.c +++ b/cmd/sf.c @@ -353,6 +353,11 @@ static int do_spi_flash_erase(int argc, char *const argv[]) if (ret != 1) return CMD_RET_USAGE; + if (size == 0) { + printf("'size is 0'\n"); + return CMD_RET_FAILURE; + } + /* Consistency checking */ if (offset + size > flash->size) { printf("ERROR: attempting %s past flash size (%#x)\n", -- 2.17.1

2 1

[PATCH 0/8] Add ESM support for J721E and J7200
by Neha Malcom Francis 12 Apr '23

12 Apr '23

Add support for ESM (Error Signalling Module) in J721E and J7200. The ESM error pin output is routed to the PMIC (Power Management IC) which can reset the board. The dts nodes for SoC and PMIC ESM modules are added (if not already) to enable them. Gowtham Tammana (6): arm: dts: k3-j7200: Add Main domain ESM support arm: dts: k3-j7200-r5-common: Add pmic node for esm arm: dts: k3-j7200: Add ESM PMIC support for tps659413 j721e_init: initialize ESM support for J7200 SOM power: pmic: tps65491: Dont fail on master node configs: j7200_evm_r5_defconfig: Enable ESM modules Tero Kristo (2): arm: mach-k3: j721e_init: initialize ESM support arm: dts: k3-k721e: Add Main domain ESM support .../k3-j7200-common-proc-board-u-boot.dtsi | 4 +++ arch/arm/dts/k3-j7200-main.dtsi | 6 +++++ .../k3-j7200-r5-common-proc-board-u-boot.dtsi | 11 ++++++++ .../arm/dts/k3-j7200-r5-common-proc-board.dts | 13 +++++++--- arch/arm/dts/k3-j7200.dtsi | 1 + arch/arm/dts/k3-j721e.dtsi | 1 + arch/arm/mach-k3/j721e_init.c | 25 ++++++++++++++++++- configs/j7200_evm_r5_defconfig | 2 ++ drivers/power/pmic/tps65941.c | 1 - 9 files changed, 59 insertions(+), 5 deletions(-) create mode 100644 arch/arm/dts/k3-j7200-r5-common-proc-board-u-boot.dtsi -- 2.34.1

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