April 2023 - U-Boot

[PATCH v2 0/2] Update mailmap ids
by Ashok Reddy Soma 03 May '23

03 May '23

In this patch series - Sort mailmap ids according to dictionary order - Update all Xilinx users mail ids to AMD Changes in v2: - Updated the missing mailids - Removed the space after mail id - Added closing brace for Vikhyat Goyal email id Algapally Santosh Sagar (2): .mailmap: Sort the mailmap ids in dictionary order .mailmap: Map all Xilinx users mail ids to AMD .mailmap | 81 +++++++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 65 insertions(+), 16 deletions(-) -- 2.17.1

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[PATCH v4 0/3] Add MAX14526 MUIC driver
by Svyatoslav Ryhel 03 May '23

03 May '23

MAX14526 MUIC is used by LG P880/P895 which are currently in the process of merging. MAX14526 is a powerful extcon device which has the ability to accurately determine plugged devices. In this implementation muic can be configured to represent 3 modes: CP-USB/UART and AP-USB. Unfortunately AP-UART was disabled on P880/P895. Additionally the driver configures some stuff required by the charger. Extcon class has empty platform struct and ops, all configuration is performed in the probe. Filling of struct and ops is welcomed. --- Changes from v3: - fix typo in commit title - added reviewed-by Changes from v2: - created a new simple extcon uclass Changes from v1: - used log_* instead of printf - log messages made simpler --- Svyatoslav Ryhel (3): dm: extcon: add an uclass for extcon test: Add tests for the extcon extcon: add MAX14526 MUIC support arch/sandbox/dts/test.dts | 4 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/extcon/Kconfig | 31 +++++++ drivers/extcon/Makefile | 7 ++ drivers/extcon/extcon-max14526.c | 151 +++++++++++++++++++++++++++++++ drivers/extcon/extcon-sandbox.c | 17 ++++ drivers/extcon/extcon-uclass.c | 16 ++++ include/dm/uclass-id.h | 1 + include/extcon.h | 19 ++++ test/dm/Makefile | 1 + test/dm/extcon.c | 21 +++++ 12 files changed, 271 insertions(+) create mode 100644 drivers/extcon/Kconfig create mode 100644 drivers/extcon/Makefile create mode 100644 drivers/extcon/extcon-max14526.c create mode 100644 drivers/extcon/extcon-sandbox.c create mode 100644 drivers/extcon/extcon-uclass.c create mode 100644 include/extcon.h create mode 100644 test/dm/extcon.c -- 2.39.2

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[PATCH] pinctrl: mediatek: set R1/R0 in case pullen/pullsel succeeded
by Daniel Golle 03 May '23

03 May '23

Commit dafe0fbfb0f3 ("pinctrl: mediatek: rewrite mtk_pinconf_set and related functions") changed the logic deciding to set R0 and R1 registers for V1 devices. Before: /* Also set PUPD/R0/R1 if the pin has them */ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup); if (err != -EINVAL) { mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0); mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1); } After: /* try pupd_r1_r0 if pullen_pullsel return error */ err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup, val); if (err) return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable, pullup, val); Tracing mtk_pinconf_bias_set_pullen_pullsel shows that the function always either returns 0 in case of success or -EINVAL in case any error has occurred. Hence the logic responsible of the decision to program R0 and R1 has been inverted. This leads to problems on BananaPi R2 (MT7623N) when booting from SDMMC, it turns out accessing eMMC no longer works since U-Boot 2022.07: MT7623> mmc dev 0 Card did not respond to voltage select! : -110 The problem wasn't detected for a long time as both eMMC and SDMMC work fine if they are used to boot from, and hence R0 and R1 were already setup by the bootrom and/or preloader. Fix the logic to restore the originally intended and correct behavior and also change the descriptive comment accordingly. Fixes: dafe0fbfb0f3 ("pinctrl: mediatek: rewrite mtk_pinconf_set and related functions") Signed-off-by: Daniel Golle <daniel(a)makrotopia.org> --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 4ae328699e2..23d759aa2d8 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -319,10 +319,10 @@ int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable, { int err; - /* try pupd_r1_r0 if pullen_pullsel return error */ + /* set pupd_r1_r0 if pullen_pullsel succeeded */ err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup, val); - if (err) + if (!err) return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable, pullup, val); -- 2.40.0

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[PATCH v2 0/2] Add DTS for BPI-R3
by Frank Wunderlich 03 May '23

03 May '23

From: Frank Wunderlich <frank-w(a)public-files.de> Add board specific devicetree for BananaPi R3. It is taken from openwrt https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=package/boot/uboot-… only enabled the factory button which was disabled because a HW-bug in rev 1.0 of r3. v2: changed label for wps-button (used as reset in openwrt) Daniel Golle (1): board: mediatek: add Bananapi-R3 devicetree Frank Wunderlich (1): configs: change bpi-r3 to board specific dts and change prompt arch/arm/dts/Makefile | 2 + arch/arm/dts/mt7986a-bpi-r3-emmc.dts | 32 ++++ arch/arm/dts/mt7986a-bpi-r3-sd.dts | 268 +++++++++++++++++++++++++++ configs/mt7986a_bpir3_emmc_defconfig | 6 +- configs/mt7986a_bpir3_sd_defconfig | 6 +- 5 files changed, 308 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/mt7986a-bpi-r3-emmc.dts create mode 100644 arch/arm/dts/mt7986a-bpi-r3-sd.dts -- 2.34.1

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[PATCH v5 0/3] Add Broadcom Northstar basic support
by Linus Walleij 03 May '23

03 May '23

This adds the device trees and minimal code needed to run U-Boot on Broadcom Northstar SoCs. This is needed to properly boot the D-Link DIR-890L router as it refuse to directly boot compressed kernels bigger than 2MB, and well our compressed kernel is bigger than 2MB so let's put in U-Boot. While it is a bit tailored to this usecase (it can probably also be used with the DIR-885L without modifications) it forms a base that can be used to support more Northstar boards. I have this working with DIR-890L and OpenWrt: https://dflund.se/~triad/krad/dlink-dir-890l/ ChangeLog v4->v5: - Drop the iProc NAND and NAND base patches that were merged to the U-Boot master. - Rebase on the master branch and test. - Add some documentation. ChangeLog v3->v4: - Rewrote the algorithm detection patch to be more careful so as to fix Tom's regression. ChangeLog v1->v3: - Bundle with the iproc NAND and nand base pacthes as the iproc patch is a prerequisite. - Jump from v1->v3 as the other patches was at version v3. Linus Walleij (3): arm: dts: Import device tree for Broadcom Northstar arm: Add support for the Broadcom Northstar SoCs board: Add new Broadcom Northstar board arch/arm/Kconfig | 22 +- arch/arm/dts/Makefile | 2 + arch/arm/dts/bcm5301x.dtsi | 581 ++++++++++++++++++++++++++++ arch/arm/dts/ns-board.dts | 57 +++ board/broadcom/bcmns/Kconfig | 12 + board/broadcom/bcmns/MAINTAINERS | 6 + board/broadcom/bcmns/Makefile | 2 + board/broadcom/bcmns/ns.c | 60 +++ configs/bcmns_defconfig | 41 ++ doc/board/broadcom/index.rst | 1 + doc/board/broadcom/northstar.rst | 44 +++ include/configs/bcmns.h | 49 +++ include/dt-bindings/clock/bcm-nsp.h | 51 +++ 13 files changed, 927 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/bcm5301x.dtsi create mode 100644 arch/arm/dts/ns-board.dts create mode 100644 board/broadcom/bcmns/Kconfig create mode 100644 board/broadcom/bcmns/MAINTAINERS create mode 100644 board/broadcom/bcmns/Makefile create mode 100644 board/broadcom/bcmns/ns.c create mode 100644 configs/bcmns_defconfig create mode 100644 doc/board/broadcom/northstar.rst create mode 100644 include/configs/bcmns.h create mode 100644 include/dt-bindings/clock/bcm-nsp.h -- 2.40.0

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[PATCH v3 0/9] serial: msm-geni: fix UART baudrate on modern platforms
by Vladimir Zapolskiy 03 May '23

03 May '23

The changeset touches Qualcomm platforms, it adds a new quite trivial misc wrapper driver to be accessed by GENI UART to get information about a proper clock divisor. The change does not intend to break any currently supported Qualcomm platforms, there should be no need to update board config or dts files. Changes from v2 to v3: * fixed return value of misc_read() from the new GENI SE QUP driver, thanks to Simon for the review comment. Changes from v1 to v2: * fixes according to the code review by Konrad, * added two changes developed by Konrad to the series, * removed .bind from the GENI SE wrapper driver, * minor fix in MSM GENI serial driver Kconfig to match the new changes, * changed dts files of SDM845 powered boards by adding GENI SE wrapper. Konrad Dybcio (2): serial: msm-geni: Always bind before relocation serial: msm-geni: Use upstream Linux bindings Vladimir Zapolskiy (7): misc: add Qualcomm GENI SE QUP device driver serial: msm-geni: remove redundant includes serial: msm-geni: remove invalid se-clk clock name serial: msm-geni: fix code indentation serial: msm-geni: fix a compile time warning from msm_serial_setbrg() serial: msm-geni: correct oversampling value based on QUP hardware revision arm: dts: msm: add GENI SE QUP device tree node arch/arm/dts/dragonboard845c.dts | 2 +- arch/arm/dts/sdm845.dtsi | 25 ++++--- arch/arm/dts/starqltechn.dts | 2 +- .../serial/msm-geni-serial.txt | 2 +- drivers/misc/Kconfig | 7 ++ drivers/misc/Makefile | 1 + drivers/misc/qcom-geni-se.c | 41 ++++++++++++ drivers/serial/Kconfig | 2 + drivers/serial/serial_msm_geni.c | 65 ++++++++++++++----- 9 files changed, 116 insertions(+), 31 deletions(-) create mode 100644 drivers/misc/qcom-geni-se.c -- 2.33.0

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[PATCH 1/2] board: Fix board file path for sdm845.c for Samsung and Qualcomm boards
by Bhupesh Sharma 03 May '23

03 May '23

Currently a few 'board/qualcomm/../Makefile' point to incorrect path of sdm845 board file. Fix the same. Signed-off-by: Bhupesh Sharma <bhupesh.sharma(a)linaro.org> --- board/qualcomm/dragonboard845c/Makefile | 2 +- board/samsung/starqltechn/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/qualcomm/dragonboard845c/Makefile b/board/qualcomm/dragonboard845c/Makefile index 0abefdaf36..fe585ad263 100644 --- a/board/qualcomm/dragonboard845c/Makefile +++ b/board/qualcomm/dragonboard845c/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2022 Sumit Garg <sumit.garg(a)linaro.org> # # This empty file prevents make error. -# Board logic defined in board/qualcomm/common/sdm845.c, no custom logic for dragonboard845c so far. +# Board logic defined in arch/arm/mach-snapdragon/init_sdm845.c, no custom logic for dragonboard845c so far. # obj-y += dragonboard845c.o diff --git a/board/samsung/starqltechn/Makefile b/board/samsung/starqltechn/Makefile index c38c0b4710..e017c827a7 100644 --- a/board/samsung/starqltechn/Makefile +++ b/board/samsung/starqltechn/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2021 Dzmitry Sankouski <dsankouski(a)gmail.com> # # This empty file prevents make error. -# Board logic defined in board/qualcomm/common/sdm845.c, no custom logic for starqltechn so far. +# Board logic defined in arch/arm/mach-snapdragon/init_sdm845.c, no custom logic for starqltechn so far. # obj-y += starqltechn.o -- 2.38.1

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[PATCH] arm: mach-k3: common: Default to non fitImage boot on HS-FS
by Vignesh Raghavendra 03 May '23

03 May '23

Allow non fitImage bootflow on Field Securable (HS-FS) devices in addition to GP, force fitImage boot only on Security enforced (HS-SE) devices where signed images are necessary to maintain chain of trust. Signed-off-by: Vignesh Raghavendra <vigneshr(a)ti.com> --- arch/arm/mach-k3/common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index a2adb791f6c0..1efeae4bc677 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -606,8 +606,8 @@ int misc_init_r(void) printf("Failed to probe am65_cpsw_nuss driver\n"); } - /* Default FIT boot on non-GP devices */ - if (get_device_type() != K3_DEVICE_TYPE_GP) + /* Default FIT boot on HS-SE devices */ + if (get_device_type() == K3_DEVICE_TYPE_HS_SE) env_set("boot_fit", "1"); return 0; -- 2.40.0

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[PATCH] arm: mach-k3: common: don't reconfigure background firewalls
by Manorit Chawdhry 03 May '23

03 May '23

K3 devices have some firewalls set up by ROM that we usually remove so that the development is easy in HS devices. While removing the firewalls disabling a background region before disabling the foreground regions keeps the firewall in a state where all the transactions will be blacklisted until all the regions are disabled. This causes a race for some other entity trying to access that memory region before all the firewalls are disabled and causes an exception. Since the background regions configured by ROM are in such a manner that they allow all transactions, don't touch the background regions at all. Signed-off-by: Manorit Chawdhry <m-chawdhry(a)ti.com> --- arch/arm/mach-k3/common.c | 5 ++++- arch/arm/mach-k3/common.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index a2adb791f6c0..6f382c651b5d 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -545,7 +545,10 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) fwl_ops->get_fwl_region(ti_sci, &region); - if (region.control != 0) { + /* Don't disable the background regions */ + if (region.control != 0 && + ((region.control & K3_BACKGROUND_FIREWALL_BIT) == + 0)) { pr_debug("Attempting to disable firewall %5d (%25s)\n", region.fwl_id, fwl_data[i].name); region.control = 0; diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 8f38fcef7f01..6ff84b188cef 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -11,6 +11,7 @@ #define J721E 0xbb64 #define J7200 0xbb6d +#define K3_BACKGROUND_FIREWALL_BIT BIT(8) struct fwl_data { const char *name; --- base-commit: a25dcda452bf6a6de72764a8d990d72e5def643d change-id: 20230418-b4-upstream-j721s2-bg-fwl-fix-2c5c340eb4a9 Best regards, -- Manorit Chawdhry <m-chawdhry(a)ti.com>

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[PATCH] arm: mach-k3: am62a7: Enable QoS for DSS
by Aradhya Bhatia 03 May '23

03 May '23

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is done by setting the DSS DMA orderID to 8. The C7x and VPAC have been overwhelming the DSS's access to the DDR (when it was accessing via the Non Real-Time (NRT) Queue), primarily because their functional frequencies, and hence DDR accesses, were significantly higher than that of DSS. This led the display to flicker when certain edgeAI models were being run. With the DSS traffic serviced from the RT queue, the flickering issue has been found to be mitigated. The am62a qos files are auto generated from the k3 resource partitioning tool. Section-3.1.12, "QoS Programming Guide", in the AM62A TRM[1], provides more information about the QoS, and section-14.1, "System Interconnect Registers", provides the register descriptions. [1] AM62A Tech Ref Manual: https://www.ti.com/lit/pdf/spruj16 Signed-off-by: Aradhya Bhatia <a-bhatia1(a)ti.com> --- arch/arm/mach-k3/am62a7_init.c | 16 +++ arch/arm/mach-k3/am62ax/Makefile | 1 + arch/arm/mach-k3/am62ax/am62a_qos_data.c | 47 +++++++++ arch/arm/mach-k3/include/mach/am62a_qos.h | 114 ++++++++++++++++++++++ arch/arm/mach-k3/include/mach/hardware.h | 9 ++ 5 files changed, 187 insertions(+) create mode 100644 arch/arm/mach-k3/am62ax/am62a_qos_data.c create mode 100644 arch/arm/mach-k3/include/mach/am62a_qos.h diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c index 02da24a3d6f0..2a827a31cf19 100644 --- a/arch/arm/mach-k3/am62a7_init.c +++ b/arch/arm/mach-k3/am62a7_init.c @@ -65,6 +65,20 @@ static void ctrl_mmr_unlock(void) mmr_unlock(PADCFG_MMR1_BASE, 1); } +#if (IS_ENABLED(CONFIG_CPU_V7R)) +static void setup_qos(void) +{ + u32 i; + + for (i = 0; i < am62a_qos_count; i++) + writel(am62a_qos_data[i].val, (uintptr_t)am62a_qos_data[i].reg); +} +#else +static void setup_qos(void) +{ +} +#endif + void board_init_f(ulong dummy) { struct udevice *dev; @@ -158,6 +172,8 @@ void board_init_f(ulong dummy) panic("DRAM init failed: %d\n", ret); #endif + setup_qos(); + printf("am62a_init: %s done\n", __func__); } diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile index c58e52df1fa2..02a941805e9a 100644 --- a/arch/arm/mach-k3/am62ax/Makefile +++ b/arch/arm/mach-k3/am62ax/Makefile @@ -4,3 +4,4 @@ obj-y += clk-data.o obj-y += dev-data.o +obj-y += am62a_qos_data.o diff --git a/arch/arm/mach-k3/am62ax/am62a_qos_data.c b/arch/arm/mach-k3/am62ax/am62a_qos_data.c new file mode 100644 index 000000000000..01b76f7493c3 --- /dev/null +++ b/arch/arm/mach-k3/am62ax/am62a_qos_data.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am62a Quality of Service (QoS) Configuration Data + * Auto generated from K3 Resource Partitioning tool + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ +#include <common.h> +#include <asm/arch/hardware.h> +#include "common.h" + +struct k3_qos_data am62a_qos_data[] = { + /* modules_qosConfig0 - 1 endpoints, 4 channels */ + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0, + .val = ORDERID_8, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1, + .val = ORDERID_8, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2, + .val = ORDERID_8, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3, + .val = ORDERID_8, + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */ + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0, + .val = 0x76543210, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4, + .val = 0xfedcba98, + }, +}; + +uint32_t am62a_qos_count = sizeof(am62a_qos_data) / sizeof(am62a_qos_data[0]); diff --git a/arch/arm/mach-k3/include/mach/am62a_qos.h b/arch/arm/mach-k3/include/mach/am62a_qos.h new file mode 100644 index 000000000000..c74d69a28f8c --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am62a_qos.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Keystone3 Quality of service endpoint definitions + * Auto generated by K3 Resource Partitioning Tool + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#define QOS_0 (0 << 0) +#define QOS_1 (1 << 0) +#define QOS_2 (2 << 0) +#define QOS_3 (3 << 0) +#define QOS_4 (4 << 0) +#define QOS_5 (5 << 0) +#define QOS_6 (6 << 0) +#define QOS_7 (7 << 0) + +#define ORDERID_0 (0 << 4) +#define ORDERID_1 (1 << 4) +#define ORDERID_2 (2 << 4) +#define ORDERID_3 (3 << 4) +#define ORDERID_4 (4 << 4) +#define ORDERID_5 (5 << 4) +#define ORDERID_6 (6 << 4) +#define ORDERID_7 (7 << 4) +#define ORDERID_8 (8 << 4) +#define ORDERID_9 (9 << 4) +#define ORDERID_10 (10 << 4) +#define ORDERID_11 (11 << 4) +#define ORDERID_12 (12 << 4) +#define ORDERID_13 (13 << 4) +#define ORDERID_14 (14 << 4) +#define ORDERID_15 (15 << 4) + +#define ASEL_0 (0 << 8) +#define ASEL_1 (1 << 8) +#define ASEL_2 (2 << 8) +#define ASEL_3 (3 << 8) +#define ASEL_4 (4 << 8) +#define ASEL_5 (5 << 8) +#define ASEL_6 (6 << 8) +#define ASEL_7 (7 << 8) +#define ASEL_8 (8 << 8) +#define ASEL_9 (9 << 8) +#define ASEL_10 (10 << 8) +#define ASEL_11 (11 << 8) +#define ASEL_12 (12 << 8) +#define ASEL_13 (13 << 8) +#define ASEL_14 (14 << 8) +#define ASEL_15 (15 << 8) + +#define EPRIORITY_0 (0 << 12) +#define EPRIORITY_1 (1 << 12) +#define EPRIORITY_2 (2 << 12) +#define EPRIORITY_3 (3 << 12) +#define EPRIORITY_4 (4 << 12) +#define EPRIORITY_5 (5 << 12) +#define EPRIORITY_6 (6 << 12) +#define EPRIORITY_7 (7 << 12) + +#define VIRTID_0 (0 << 16) +#define VIRTID_1 (1 << 16) +#define VIRTID_2 (2 << 16) +#define VIRTID_3 (3 << 16) +#define VIRTID_4 (4 << 16) +#define VIRTID_5 (5 << 16) +#define VIRTID_6 (6 << 16) +#define VIRTID_7 (7 << 16) +#define VIRTID_8 (8 << 16) +#define VIRTID_9 (9 << 16) +#define VIRTID_10 (10 << 16) +#define VIRTID_11 (11 << 16) +#define VIRTID_12 (12 << 16) +#define VIRTID_13 (13 << 16) +#define VIRTID_14 (14 << 16) +#define VIRTID_15 (15 << 16) + +#define ATYPE_0 (0 << 28) +#define ATYPE_1 (1 << 28) +#define ATYPE_2 (2 << 28) +#define ATYPE_3 (3 << 28) + +#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000 +#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400 +#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800 +#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000 +#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400 +#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800 +#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R 0x45D20400 +#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W 0x45D20800 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45D21800 +#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45D21C00 +#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM 0x45D22000 +#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM 0x45D22400 +#define EMMCSD8SS_MAIN_0_EMMCSDSS_RD 0x45D22800 +#define EMMCSD8SS_MAIN_0_EMMCSDSS_WR 0x45D22C00 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D23000 +#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D23400 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D23800 +#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D23C00 +#define USB2SS_16FFC_MAIN_0_MSTW0 0x45D24000 +#define USB2SS_16FFC_MAIN_0_MSTR0 0x45D24400 +#define USB2SS_16FFC_MAIN_1_MSTR0 0x45D24800 +#define USB2SS_16FFC_MAIN_1_MSTW0 0x45D24C00 +#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D25000 +#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400 +#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W 0x45D25800 +#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R 0x45D25C00 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45D26800 +#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45D26C00 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45D27000 +#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45D27400 +#define SAM62A_C7XV_WRAP_MAIN_0_C7XV_SOC 0x45D27800 +#define SAM62A_VPAC_WRAP_MAIN_0_LDC0_M_MST 0x45D28000 diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 2c60ef85432b..6e6557ff6e3f 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -28,6 +28,7 @@ #ifdef CONFIG_SOC_K3_AM62A7 #include "am62a_hardware.h" +#include "am62a_qos.h" #endif /* Assuming these addresses and definitions stay common across K3 devices */ @@ -71,4 +72,12 @@ struct rom_extended_boot_data { u32 num_components; }; +struct k3_qos_data { + u32 reg; + u32 val; +}; + +extern struct k3_qos_data am62a_qos_data[]; +extern u32 am62a_qos_count; + #endif /* _ASM_ARCH_HARDWARE_H_ */ -- 2.39.1

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