April 2023 - U-Boot

[PATCH v3 0/2] Add support to fetch baudrate from dtb
by Venkatesh Yadav Abbarapu 18 May '23

18 May '23

From: Algapally Santosh Sagar <santoshsagar.algapally(a)amd.com> In this patch series - Fetch baudrate from the dtb and update - Add support in Kconfig and convert for armada boards Changes in v3: - Moved filler changes from zynqmp.h to generic file env_default.h - Removed ENV_RW_FILLER and added padding in the generic file env_default.h. - Print baudrate parameter properly when SERIAL_DT is enabled. - Add SERIAL_DT_BAUD to Kconfig - Moved DEFAULT_ENV_IS_RW to Kconfig also updated armada files Changes in v2: - Changed to #ifdef from #if CONFIG_IS_ENABLED to enable patching in spl. - Added SPL_ENV_SUPPORT dependency in SERIAL_DT_BAUD to allow SPL compilation. - Moved DEFAULT_ENV_IS_RW to Kconfig also updated armada files - Moved ENV_RW_FILLER to generic file env_default.h. - Increased the ENV_RW_FILLER padding to support 8000000 baud. Algapally Santosh Sagar (2): serial: zynqmp: Fetch baudrate from dtb and update configs: Add support in Kconfig and convert for armada boards configs/mvebu_db-88f3720_defconfig | 1 + configs/mvebu_espressobin-88f3720_defconfig | 1 + configs/mvebu_mcbin-88f8040_defconfig | 1 + drivers/serial/Kconfig | 16 +++++++++ drivers/serial/serial-uclass.c | 32 +++++++++++++++++ include/configs/mvebu_armada-37xx.h | 1 - include/env_default.h | 7 ++-- include/env_internal.h | 2 +- include/fdtdec.h | 8 +++++ include/serial.h | 1 + lib/fdtdec.c | 40 +++++++++++++++++++++ 11 files changed, 106 insertions(+), 4 deletions(-) -- 2.25.1

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[u-boot, v2019.04-aspeed-openbmc] ARM: dts: aspeed: add Meta greatlakes board (AST2600)
by Delphine CC Chiu 18 May '23

18 May '23

Add initial version of device tree for Meta Greatlakes BMC which is equipped with Aspeed AST2600 BMC SoC. Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu(a)Wiwynn.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/ast2600-greatlakes.dts | 191 ++++++++++++++++++++++++++ configs/ast2600_openbmc_spl_defconfig | 1 + 3 files changed, 193 insertions(+) create mode 100644 arch/arm/dts/ast2600-greatlakes.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6c34b83336..c9cb54cddd 100755 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -686,6 +686,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ ast2600-evb.dtb \ ast2600-dcscm.dtb \ ast2600-fpga.dtb \ + ast2600-greatlakes.dtb \ ast2600-intel.dtb \ ast2600-ncsi.dtb \ ast2600-p10bmc.dtb \ diff --git a/arch/arm/dts/ast2600-greatlakes.dts b/arch/arm/dts/ast2600-greatlakes.dts new file mode 100644 index 0000000000..94caf295da --- /dev/null +++ b/arch/arm/dts/ast2600-greatlakes.dts @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2022 Meta Platforms Inc. +/dts-v1/; + +#include "ast2600-u-boot.dtsi" + +/ { + model = "Facebook Greatlakes BMC"; + compatible = "facebook,greatlakes-bmc", "aspeed,ast2600"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + stdout-path = &uart5; + }; + + aliases { + spi0 = &fmc; + ethernet3 = &mac3; + }; + + cpus { + cpu@0 { + clock-frequency = <800000000>; + }; + cpu@1 { + clock-frequency = <800000000>; + }; + }; +}; + +&uart5 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&sdrammc { + clock-frequency = <400000000>; +}; + +&wdt1 { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&wdt3 { + status = "okay"; +}; + +&mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio4_default>; + #address-cells = <1>; + #size-cells = <0>; + ethphy3: ethernet-phy@3 { + reg = <0>; + }; +}; + +&mac3 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&ethphy3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; +}; + +&fmc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fmcquad_default>; +}; + +&gpio0 { + status = "okay"; + line_148 { + gpio-hog; + gpios = <148 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc-slot1-isolated-enabled"; + }; + line_149 { + gpio-hog; + gpios = <149 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc-slot2-isolated-enabled"; + }; + line_150 { + gpio-hog; + gpios = <150 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc-slot3-isolated-enabled"; + }; + line_151 { + gpio-hog; + gpios = <151 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc-slot4-isolated-enabled"; + }; +}; + +&i2c0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; +}; + +&i2c1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_default>; +}; + +&i2c2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; +}; + +&i2c3 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; +}; + +&i2c4 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; +}; + +&i2c5 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; +}; + +&i2c6 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; +}; + +&i2c7 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; +}; + +&i2c8 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; +}; + +&scu { + mac0-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; + mac1-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; + mac2-clk-delay = <0x08 0x04 + 0x08 0x04 + 0x08 0x04>; + mac3-clk-delay = <0x08 0x04 + 0x08 0x04 + 0x08 0x04>; +}; + +&hace { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/configs/ast2600_openbmc_spl_defconfig b/configs/ast2600_openbmc_spl_defconfig index 95d7651b8e..efd683570f 100644 --- a/configs/ast2600_openbmc_spl_defconfig +++ b/configs/ast2600_openbmc_spl_defconfig @@ -100,6 +100,7 @@ CONFIG_ASPEED_ACRY=y CONFIG_DM_GPIO=y CONFIG_SPL_GPIO_HOG=y CONFIG_ASPEED_GPIO=y +CONFIG_GPIO_HOG=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_ASPEED=y CONFIG_MISC=y -- 2.17.1

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[PATCH 00/14] rockchip: rk35xx: Update defconfigs and enable boot from SPI NOR flash
by Jonas Karlman 17 May '23

17 May '23

This series sync some defconfig options across the different rk35xx boards and enables boot from SPI NOR flash on rk3568-rock-3a and rk3588-rock-5b. Patch 1 fixes use of sfc-no-dma prop in rockchip sfc driver. Patch 2-7 updates defconfig for rk356x boards. Patch 8 enables boot from SPI NOR flash on rk3568-rock-3a. Patch 9-12 updates defconfig for rk3588 boards. Patch 13 enables boot from SPI NOR flash on rk3588-rock-5b. Patch 14 reverts addition of regulator-boot-on props. Please note that patches related to rk3588 depend on [1] and [2], they may not apply clean. The final patch revert a workaround to fix usb that is not needed after series [1] and [3]. This series can also be found at [4]. [1] https://patchwork.ozlabs.org/project/uboot/patch/20230419134014.128461-1-eu… [2] https://patchwork.ozlabs.org/project/uboot/patch/20230417100641.5703-1-euge… [3] https://patchwork.ozlabs.org/project/uboot/patch/20230419134526.128800-1-eu… [4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk35xx-defconfig-spi-v1 Jonas Karlman (14): spi: rockchip_sfc: Use linux rockchip,sfc-no-dma prop rockchip: rk356x-u-boot: Add xin24m clock node to SPL rockchip: rk3566-radxa-cm3-io: Update defconfig rockchip: rk3566-radxa-cm3-io: Use pinctrl for sdmmc and sdhci in SPL rockchip: rk3568-evb: Update defconfig rockchip: rk3568-rock-3a: Update defconfig rockchip: rk3568-rock-3a: Use pinctrl for sdmmc and sdhci in SPL rockchip: rk3568-rock-3a: Enable boot from SPI NOR flash rockchip: rk3588: Select DM_RESET and DM_REGULATOR_FIXED in arch Kconfig rockchip: rk3588-evb: Update defconfig rockchip: rk3588-rock-5b: Update defconfig rockchip: rk3588-rock-5b: Add bootph prop to pinctrl for uart2 and sdhci rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash Revert "arm: dts: rockchip: radxa-cm3-io, rock-3a: enable regulators for usb" arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 65 ++++++++++++++- arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 85 ++++++++++++++++++-- arch/arm/dts/rk356x-u-boot.dtsi | 16 ++++ arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 52 ++++++++++++ arch/arm/dts/rk3588s-u-boot.dtsi | 20 +++++ arch/arm/mach-rockchip/Kconfig | 2 + arch/arm/mach-rockchip/rk3588/rk3588.c | 1 + configs/evb-rk3568_defconfig | 15 ++-- configs/evb-rk3588_defconfig | 11 +-- configs/neu6a-io-rk3588_defconfig | 1 - configs/radxa-cm3-io-rk3566_defconfig | 10 ++- configs/rock-3a-rk3568_defconfig | 20 +++-- configs/rock5b-rk3588_defconfig | 19 +++-- drivers/spi/rockchip_sfc.c | 10 ++- 14 files changed, 285 insertions(+), 42 deletions(-) -- 2.40.0

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[PATCH v3 1/7] pci: pcie_dw_rockchip: Add rk3588 compatible
by Eugen Hristev 17 May '23

17 May '23

From: Jon Lin <jon.lin(a)rock-chips.com> Add compatible for RK3588 SoC. Signed-off-by: Jon Lin <jon.lin(a)rock-chips.com> Reviewed-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v2,v3: - none drivers/pci/pcie_dw_rockchip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 6155710a9f5f..ff121046604a 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -468,6 +468,7 @@ static const struct dm_pci_ops rockchip_pcie_ops = { static const struct udevice_id rockchip_pcie_ids[] = { { .compatible = "rockchip,rk3568-pcie" }, + { .compatible = "rockchip,rk3588-pcie" }, { } }; -- 2.34.1

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[PATCH] gpio: renesas: Simplify .request/.rfree callbacks
by Pali Rohár 16 May '23

16 May '23

Remove identify wrapper functions. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/gpio/gpio-rcar.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index 138801850d3e..ba00bb459679 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -130,20 +130,9 @@ static int rcar_gpio_get_function(struct udevice *dev, unsigned offset) return GPIOF_INPUT; } -static int rcar_gpio_request(struct udevice *dev, unsigned offset, - const char *label) -{ - return pinctrl_gpio_request(dev, offset, label); -} - -static int rcar_gpio_free(struct udevice *dev, unsigned offset) -{ - return pinctrl_gpio_free(dev, offset); -} - static const struct dm_gpio_ops rcar_gpio_ops = { - .request = rcar_gpio_request, - .rfree = rcar_gpio_free, + .request = pinctrl_gpio_request, + .rfree = pinctrl_gpio_free, .direction_input = rcar_gpio_direction_input, .direction_output = rcar_gpio_direction_output, .get_value = rcar_gpio_get_value, -- 2.20.1

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[PATCH v8 00/24] Fixes for Rockchip NFC driver part 1
by Johan Jonker 16 May '23

16 May '23

This serie contains fixes for the Rockchip NFC driver, which was ported to U-boot and merged with little review and testing it seems. Part 1 aims at passing the probe function without errors. Extended with tree wide function cleanup needed for 64bit DT parsing. Fixed are: 64bit FDT parsing compatible string removal add missing layout structure add missing flash_node pointer add missing chip ID Changed V8: change comments use uintptr_t size instead of phys_addr_t add another fdt_addr_t fix Changed V7: add proof of concept for syscon node with variable reg size handling use another map_sysmem() function as cast remove cast Changed V6: use -EINVAL on return drop cast use map_sysmem() function as cast add and rename patch Changed V5: sort patch order add more fixes with pointer functions add debug text fixes test with binman for ARM only due to limited resources Changed V4: fix cast and divider in syscon-uclass.c Changed V3: use dev_read_addr_ptr fix oobfree Johan Jonker (23): mtd: nand: raw: rockchip_nfc: use dev_read_addr_ptr mtd: nand: raw: rockchip_nfc: remove the compatible string "rockchip,rk3308-nfc" mtd: nand: raw: rockchip_nfc: add layout structure mtd: nand: raw: rockchip_nfc: add flash_node to chip structure mtd: nand: raw: rockchip_nfc: fix oobfree offset and description rockchip: adc: rockchip-saradc: use dev_read_addr_ptr rockchip: timer: dw-apb-timer: use regs variable with uintptr_t size rockchip: pwm: rk_pwm: use base variable with uintptr_t size rockchip: spi: rk_spi: use base variable with uintptr_t size include: dm: ofnode: fix headers core: remap: fix regmap_init_mem_plat() reg size handeling rockchip: rk3288: syscon_rk3288: store syscon platdata in regmap core: fdtaddr: add devfdt_get_addr_size_index_ptr function core: read: add dev_read_addr_index_ptr function spi: spi-aspeed-smc: use devfdt_get_addr_index_ptr drivers: use dev_read_addr_index_ptr when cast to pointer drivers: use dev_read_addr_ptr when cast to pointer drivers: use devfdt_get_addr_size_index_ptr when cast to pointer drivers: use devfdt_get_addr_index_ptr when cast to pointer drivers: use devfdt_get_addr_ptr when cast to pointer drivers: fix debug string with fdt_addr_t input arm: stm32mp: spl: fix function with fdt_addr_t input include: fdtdec: decouple fdt_addr_t and phys_addr_t size Paweł Jarosz (1): mtd: nand: add support for the Sandisk SDTNQGAMA chip Kconfig | 8 ++ arch/arm/mach-mvebu/cpu.c | 2 +- arch/arm/mach-mvebu/system-controller.c | 4 +- arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 121 ++++++++++++++++++ arch/arm/mach-stm32mp/spl.c | 2 +- doc/develop/driver-model/livetree.rst | 2 +- drivers/adc/rockchip-saradc.c | 6 +- drivers/ata/dwc_ahsata.c | 2 +- drivers/cache/cache-l2x0.c | 2 +- drivers/cache/cache-v5l2.c | 2 +- drivers/clk/at91/sama7g5.c | 2 +- drivers/clk/at91/sckc.c | 2 +- drivers/clk/clk-hsdk-cgu.c | 4 +- drivers/clk/ti/clk-ctrl.c | 9 +- drivers/core/fdtaddr.c | 17 ++- drivers/core/read.c | 15 ++- drivers/core/regmap.c | 23 +++- drivers/core/syscon-uclass.c | 23 +++- drivers/ddr/altera/sdram_gen5.c | 4 +- drivers/gpio/mscc_sgpio.c | 2 +- drivers/gpio/tegra_gpio.c | 4 +- drivers/gpio/xilinx_gpio.c | 2 +- drivers/i2c/i2c-cdns.c | 4 +- drivers/i2c/tegra_i2c.c | 4 +- drivers/mmc/am654_sdhci.c | 2 +- drivers/mmc/davinci_mmc.c | 2 +- drivers/mmc/piton_mmc.c | 2 +- drivers/mmc/tegra_mmc.c | 2 +- drivers/mmc/xenon_sdhci.c | 2 +- drivers/mmc/zynq_sdhci.c | 6 +- drivers/mtd/nand/raw/arasan_nfc.c | 2 +- drivers/mtd/nand/raw/cortina_nand.c | 6 +- drivers/mtd/nand/raw/mxic_nand.c | 2 +- drivers/mtd/nand/raw/nand_ids.c | 3 + drivers/mtd/nand/raw/rockchip_nfc.c | 78 ++++------- drivers/mtd/nand/raw/tegra_nand.c | 2 +- drivers/mtd/nand/raw/zynq_nand.c | 2 +- drivers/net/dm9000x.c | 2 +- drivers/net/dwmac_meson8b.c | 4 +- drivers/net/mvmdio.c | 2 +- drivers/net/mvpp2.c | 24 ++-- drivers/net/qe/dm_qe_uec_phy.c | 2 +- drivers/pci/pci-aardvark.c | 4 +- drivers/pci/pcie_dw_meson.c | 8 +- drivers/pci/pcie_dw_mvebu.c | 10 +- drivers/pci/pcie_dw_rockchip.c | 8 +- drivers/pci/pcie_imx.c | 4 +- drivers/pci/pcie_layerscape_ep.c | 8 +- drivers/phy/allwinner/phy-sun50i-usb3.c | 6 +- drivers/phy/marvell/comphy_core.c | 12 +- drivers/phy/phy-stm32-usbphyc.c | 4 +- drivers/phy/qcom/phy-qcom-usb-hs-28nm.c | 4 +- drivers/phy/qcom/phy-qcom-usb-ss.c | 4 +- .../phy/rockchip/phy-rockchip-snps-pcie3.c | 4 +- drivers/phy/rockchip/phy-rockchip-typec.c | 6 +- drivers/pwm/rk_pwm.c | 2 +- drivers/pwm/tegra_pwm.c | 2 +- drivers/ram/rockchip/sdram_rk3066.c | 2 +- drivers/ram/rockchip/sdram_rk3188.c | 2 +- drivers/ram/rockchip/sdram_rk322x.c | 2 +- drivers/ram/rockchip/sdram_rk3288.c | 2 +- drivers/ram/rockchip/sdram_rk3328.c | 2 +- drivers/ram/rockchip/sdram_rk3399.c | 2 +- drivers/serial/serial_zynq.c | 6 +- drivers/spi/cadence_qspi.c | 5 +- drivers/spi/mpc8xxx_spi.c | 2 +- drivers/spi/mscc_bb_spi.c | 2 +- drivers/spi/mtk_snor.c | 2 +- drivers/spi/mtk_spim.c | 2 +- drivers/spi/rk_spi.c | 2 +- drivers/spi/sh_qspi.c | 2 +- drivers/spi/spi-aspeed-smc.c | 17 ++- drivers/spi/spi-mxic.c | 2 +- drivers/spi/xilinx_spi.c | 2 +- drivers/timer/dw-apb-timer.c | 2 +- drivers/ufs/ufs.c | 2 +- drivers/usb/host/ehci-tegra.c | 2 +- drivers/usb/musb-new/ti-musb.c | 2 +- drivers/video/dw_mipi_dsi.c | 4 +- drivers/video/rockchip/rk_vop.c | 2 +- drivers/video/stm32/stm32_dsi.c | 4 +- drivers/video/stm32/stm32_ltdc.c | 4 +- drivers/video/tegra124/display.c | 2 +- drivers/video/tegra124/sor.c | 6 +- drivers/video/ti/tilcdc.c | 4 +- drivers/watchdog/cdns_wdt.c | 6 +- drivers/watchdog/sbsa_gwdt.c | 12 +- drivers/watchdog/sp805_wdt.c | 6 +- drivers/watchdog/xilinx_tb_wdt.c | 6 +- include/dm/fdtaddr.h | 17 ++- include/dm/ofnode.h | 16 +-- include/fdtdec.h | 13 +- include/regmap.h | 5 +- include/syscon.h | 13 -- 94 files changed, 426 insertions(+), 255 deletions(-) -- 2.20.1

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[V3,1/1] riscv: Increase the upper bound of NR_CPUS to 4095
by Leo Yu-Chi Liang 16 May '23

16 May '23

From: Xiang W <wxjstz(a)126.com> The maximum hart number is 32 and is determined by the type of gd->arch.available_harts. However, various RISC-V specifications allow the hart number to be greater than 32. We can eliminate this limitation through bitmaps. The patch modifies the upper bound of the hart number to 4095, which is also the maximum hart number RISC-V Advanced Core Local Interruptor Specification gives. Some defconfigs, (e.g. qemu-riscv32_smode_defconfig, qemu-riscv64_smode_defconfig, openpiton_riscv64_defconfig, ...) do not define CONFIG_NR_CPUS, and may result in compile error, so define CONFIG_NR_CPUS to be 1 if CONFIG_NR_CPUS is not defined. Tested on sifive unmatched. Signed-off-by: Xiang W <wxjstz(a)126.com> Signed-off-by: Leo Yu-Chi Liang <ycliang(a)andestech.com> --- Changes v2 -> v3: - Fix the calculation of the GD_AVAILABLE_HARTS start address - Fix compilation error for defconfigs that do not define CONFIG_NR_CPUS --- arch/riscv/Kconfig | 4 ++-- arch/riscv/cpu/start.S | 20 +++++++++++++++----- arch/riscv/include/asm/global_data.h | 8 +++++++- arch/riscv/lib/smp.c | 2 +- 4 files changed, 25 insertions(+), 9 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ebc4bef220..063734cbb9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -232,8 +232,8 @@ config SPL_SMP all, single processor machines. config NR_CPUS - int "Maximum number of CPUs (2-32)" - range 2 32 + int "Maximum number of CPUs (2-4095)" + range 2 4095 depends on SMP || SPL_SMP default 8 help diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 4687bca3c9..ae19c2b43d 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -172,11 +172,21 @@ wait_for_gd_init: bnez t1, 1b /* register available harts in the available_harts mask */ - li t1, 1 - sll t1, t1, tp - LREG t2, GD_AVAILABLE_HARTS(gp) - or t2, t2, t1 - SREG t2, GD_AVAILABLE_HARTS(gp) + li t1, GD_AVAILABLE_HARTS + add t1, t1, gp +#if defined(CONFIG_ARCH_RV64I) + srli t2, tp, 6 + slli t2, t2, 3 +#elif defined(CONFIG_ARCH_RV32I) + srli t2, tp, 5 + slli t2, t2, 2 +#endif + add t1, t1, t2 + LREG t2, 0(t1) + li t3, 1 + sll t3, t3, tp + or t2, t2, t3 + SREG t2, 0(t1) amoswap.w.rl zero, zero, 0(t0) #endif diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 6fdc86dd8b..7e37e90db0 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -10,9 +10,15 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include <config.h> #include <asm/smp.h> #include <asm/u-boot.h> #include <compiler.h> +#include <linux/bitops.h> + +#ifndef CONFIG_NR_CPUS +#define CONFIG_NR_CPUS 1 +#endif /* Architecture-specific global data */ struct arch_global_data { @@ -29,7 +35,7 @@ struct arch_global_data { #endif #if !CONFIG_IS_ENABLED(XIP) #ifdef CONFIG_AVAILABLE_HARTS - ulong available_harts; + ulong available_harts[BITS_TO_LONGS(CONFIG_NR_CPUS)]; #endif #endif }; diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index 4f073a016f..511e3ed98d 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -48,7 +48,7 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) #if !CONFIG_IS_ENABLED(XIP) #ifdef CONFIG_AVAILABLE_HARTS /* skip if hart is not available */ - if (!(gd->arch.available_harts & (1 << reg))) + if (!test_bit(reg, gd->arch.available_harts)) continue; #endif #endif -- 2.38.0.68.ge85701b4af.dirty

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[PATCH v3 1/2] firmware: zynqmp: Remove extraordinary return value
by Stefan Herbrechtsmeier 16 May '23

16 May '23

From: Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> Return a common -EACCES error value instead of a positive private error value XST_PM_NO_ACCESS (2002) in zynqmp_pmufw_load_config_object function if the config object is not loadable to simplify the error checking. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> --- Changes in v3: - Rebase Changes in v2: - Use macro for node id drivers/firmware/firmware-zynqmp.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index dc8e3ad2b9..2b1ad5d2c3 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -82,7 +82,7 @@ int zynqmp_pmufw_node(u32 id) ret = zynqmp_pmufw_load_config_object(xpm_configobject, sizeof(xpm_configobject)); - if (ret == XST_PM_NO_ACCESS && id == NODE_OCM_BANK_0) + if (ret == -EACCES && id == NODE_OCM_BANK_0) skip_config = true; return 0; @@ -235,8 +235,7 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id) * * @cfg_obj: Pointer to the configuration object * @size: Size of @cfg_obj in bytes - * Return: 0 on success otherwise negative errno. If the config object - * is not loadable returns positive errno XST_PM_NO_ACCESS(2002) + * Return: 0 on success otherwise negative errno. */ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) { @@ -251,10 +250,8 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) err = xilinx_pm_request(PM_SET_CONFIGURATION, (u32)(u64)cfg_obj, 0, 0, 0, ret_payload); if (err == XST_PM_NO_ACCESS) { - if (((u32 *)cfg_obj)[NODE_ID_LOCATION] == NODE_OCM_BANK_0) { + if (((u32 *)cfg_obj)[NODE_ID_LOCATION] == NODE_OCM_BANK_0) printf("PMUFW: No permission to change config object\n"); - return err; - } return -EACCES; } -- 2.30.2

2 4

[PATCH v5 00/17] Basic StarFive JH7110 RISC-V SoC support
by Yanhong Wang 16 May '23

16 May '23

This series of patches base on the latest branch/master, and add support for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for this to be achieved, the respective DT nodes have been added, and the required defconfigs have been added to the boards' defconfig. What is more, the basic required DM drivers have been added, such as reset, clock, pinctrl, uart, ram etc. Note that the register base address of reset controller is same with the clock controller. Therefore, there is no device tree node alone for reset driver. It binds device node in the clock driver. The u-boot-spl and u-boot has been tested on the StarFive VisionFive 2 1.2A and 1.3B boards which equip with JH7110 SoC and works normally. For more information and support, you can visit RVspace wiki[1]. [1] https://wiki.rvspace.org/ v5: - Fixed the build errors that came from "make htmldocs". - Remove the MMU configuration from the S7 device tree node. - Splitted starfive_visionfive2_defconfig into starfive_visionfive2_12a_defconfig and starfive_visionfive2_13b_defconfig. - Added the implementation of 'get_function' callback function to pinctrl. v4: - Replace compatible string "starfive,jh7110-ccache" with "sifive,ccache0". - Added 'gmac0_tx_inv','gmac1_tx_inv','gmac1_rx' clock registration. - Added enable_caches() call to enable L2 cache in board_init() function. - Moved 'S7_0' device node from board dts to SoC -u-boot.dtsi. - Added 'i2cx' device node to board dts to consistent with linux. - Renamed device node 'sdcard1_pins' to 'mmc1_pins'. v3: - Added doc/board/starfive/visionfive2.rst file. - Added support booting from SD. - Added support pinctrl in SPL. - Reworded dts to consistent with linux. - Added CFG_EXTRA_ENV_SETTINGS configuration. - Reworded starfive_visionfive2_defconfig. - Reworded the clock driver. - Renamed 'starfive-jh7110.h' to 'starfive,jh7110-crg.h'. - Separated 'starfive_visionfive2.dts' to 'jh7110-starfive-visionfive-2-v1.3b.dts' and 'jh7110-starfive-visionfive-2-v1.2a.dts' to consistent with linux. - Added pinmux_property_set callback function implementation in 'pinctrl-starfive.c'. v2: - Renamed file 'jh7110-regs.h' to 'regs.h'. - Reworded the clear L2 LIM memory code in C. - Removed flash init call in 'spl_soc_init' function. - Reworded the clock driver. - Rename the macro 'SET_DIV' to 'ASSIGNED_CLOCK_PARENTS' in 'spl.c'. - Moved the device tree node 'dmc@15700000' from 'jh7110-u-boot.dtsi' to 'starfive_visionfive2-u-boot.dtsi' Previous versions: v1 - https://patchwork.ozlabs.org/project/uboot/cover/20221212025020.23778-1-yan… v2 - https://patchwork.ozlabs.org/project/uboot/cover/20230118081132.31403-1-yan… v3 - https://patchwork.ozlabs.org/project/uboot/patch/20230303032432.7837-2-yanh… v4 - https://patchwork.ozlabs.org/project/uboot/cover/20230316025332.3297-1-yanh… Jianlong Huang (1): dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Kuan Lim Lee (1): pinctrl: starfive: Add StarFive JH7110 driver Yanhong Wang (15): riscv: cpu: jh7110: Add support for jh7110 SoC cache: starfive: Add StarFive JH7110 support dt-bindings: reset: Add StarFive JH7110 reset definitions reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC dt-bindings: clock: Add StarFive JH7110 clock definitions clk: starfive: Add StarFive JH7110 clock driver ram: starfive: add ddr driver board: starfive: add StarFive VisionFive v2 board support riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC board: starfive: Add Kconfig for StarFive VisionFive v2 Board board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig riscv: dts: jh7110: Add initial StarFive JH7110 device tree riscv: dts: jh7110: Add initial u-boot device tree riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree configs: starfive: add defconfig for StarFive VisionFvie2 1.2A and 1.3B arch/riscv/Kconfig | 5 + arch/riscv/cpu/jh7110/Kconfig | 28 + arch/riscv/cpu/jh7110/Makefile | 10 + arch/riscv/cpu/jh7110/cpu.c | 23 + arch/riscv/cpu/jh7110/dram.c | 38 + arch/riscv/cpu/jh7110/spl.c | 64 + arch/riscv/dts/Makefile | 3 +- ...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 69 + .../jh7110-starfive-visionfive-2-v1.2a.dts | 12 + ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 69 + .../jh7110-starfive-visionfive-2-v1.3b.dts | 12 + .../dts/jh7110-starfive-visionfive-2.dtsi | 319 +++ arch/riscv/dts/jh7110-u-boot.dtsi | 99 + arch/riscv/dts/jh7110.dtsi | 573 +++++ arch/riscv/include/asm/arch-jh7110/regs.h | 19 + arch/riscv/include/asm/arch-jh7110/spl.h | 12 + board/starfive/visionfive2/Kconfig | 53 + board/starfive/visionfive2/MAINTAINERS | 7 + board/starfive/visionfive2/Makefile | 7 + board/starfive/visionfive2/spl.c | 87 + .../visionfive2/starfive_visionfive2.c | 40 + configs/starfive_visionfive2_12a_defconfig | 79 + configs/starfive_visionfive2_13b_defconfig | 79 + doc/board/index.rst | 1 + doc/board/starfive/index.rst | 9 + doc/board/starfive/visionfive2.rst | 492 +++++ drivers/cache/cache-sifive-ccache.c | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/starfive/Kconfig | 17 + drivers/clk/starfive/Makefile | 4 + drivers/clk/starfive/clk-jh7110-pll.c | 321 +++ drivers/clk/starfive/clk-jh7110.c | 603 +++++ drivers/clk/starfive/clk.h | 57 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/starfive/Kconfig | 28 + drivers/pinctrl/starfive/Makefile | 6 + drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 113 + drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 399 ++++ drivers/pinctrl/starfive/pinctrl-starfive.c | 398 ++++ drivers/pinctrl/starfive/pinctrl-starfive.h | 55 + drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 4 +- drivers/ram/starfive/Kconfig | 5 + drivers/ram/starfive/Makefile | 11 + drivers/ram/starfive/ddrcsr_boot.c | 339 +++ drivers/ram/starfive/ddrphy_start.c | 279 +++ drivers/ram/starfive/ddrphy_train.c | 383 ++++ drivers/ram/starfive/ddrphy_utils.c | 1955 +++++++++++++++++ drivers/ram/starfive/starfive_ddr.c | 161 ++ drivers/ram/starfive/starfive_ddr.h | 65 + drivers/reset/Kconfig | 16 + drivers/reset/Makefile | 1 + drivers/reset/reset-jh7110.c | 158 ++ include/configs/starfive-visionfive2.h | 49 + .../dt-bindings/clock/starfive,jh7110-crg.h | 257 +++ .../pinctrl/pinctrl-starfive-jh7110.h | 427 ++++ .../dt-bindings/reset/starfive,jh7110-crg.h | 183 ++ 59 files changed, 8507 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/cpu/jh7110/Kconfig create mode 100644 arch/riscv/cpu/jh7110/Makefile create mode 100644 arch/riscv/cpu/jh7110/cpu.c create mode 100644 arch/riscv/cpu/jh7110/dram.c create mode 100644 arch/riscv/cpu/jh7110/spl.c create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110.dtsi create mode 100644 arch/riscv/include/asm/arch-jh7110/regs.h create mode 100644 arch/riscv/include/asm/arch-jh7110/spl.h create mode 100644 board/starfive/visionfive2/Kconfig create mode 100644 board/starfive/visionfive2/MAINTAINERS create mode 100644 board/starfive/visionfive2/Makefile create mode 100644 board/starfive/visionfive2/spl.c create mode 100644 board/starfive/visionfive2/starfive_visionfive2.c create mode 100644 configs/starfive_visionfive2_12a_defconfig create mode 100644 configs/starfive_visionfive2_13b_defconfig create mode 100644 doc/board/starfive/index.rst create mode 100644 doc/board/starfive/visionfive2.rst create mode 100644 drivers/clk/starfive/Kconfig create mode 100644 drivers/clk/starfive/Makefile create mode 100644 drivers/clk/starfive/clk-jh7110-pll.c create mode 100644 drivers/clk/starfive/clk-jh7110.c create mode 100644 drivers/clk/starfive/clk.h create mode 100644 drivers/pinctrl/starfive/Kconfig create mode 100644 drivers/pinctrl/starfive/Makefile create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h create mode 100644 drivers/ram/starfive/Kconfig create mode 100644 drivers/ram/starfive/Makefile create mode 100644 drivers/ram/starfive/ddrcsr_boot.c create mode 100644 drivers/ram/starfive/ddrphy_start.c create mode 100644 drivers/ram/starfive/ddrphy_train.c create mode 100644 drivers/ram/starfive/ddrphy_utils.c create mode 100644 drivers/ram/starfive/starfive_ddr.c create mode 100644 drivers/ram/starfive/starfive_ddr.h create mode 100644 drivers/reset/reset-jh7110.c create mode 100644 include/configs/starfive-visionfive2.h create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h base-commit: 41a88ad529b3943b1e465846eb24fe2c29203e35 -- 2.17.1

8 35

[PATCH v3 00/19] Migration to using binman for bootloader
by Neha Malcom Francis 16 May '23

16 May '23

This series aims to eliminate the use of additional custom repositories such as k3-image-gen (K3 Image Generation) repo and core-secdev-k3 (K3 Security Development Tools) that was plumbed into the U-Boot build flow to generate boot images for TI K3 platform devices. And instead, we move towards using binman that aligns better with the community standard build flow. This series uses binman for all K3 platforms supported on U-Boot currently; both HS (High Security, both SE and FS) and GP (General Purpose) devices. Background on using k3-image-gen: * TI K3 devices require a SYSFW (System Firmware) image consisting of a signed system firmware image and board configuration binaries, this is needed to bring up system firmware during U-Boot R5 SPL startup. * Board configuration data contain board-specific information such as resource management, power management and security. Background on using core-secdev-k3: * Contains resources to sign x509 certificates for HS devices Series intends to use binman to take over the packaging and signing for the R5 bootloader images tiboot3.bin (and sysfw.itb, for non-combined boot flow) instead of k3-image-gen. Series also packages the A72/A53 bootloader images (tispl.bin and u-boot.img) using ATF, OPTEE and DM (Device Manager) Changes in v3: - added support for HS-FS devices - added support for AM68-sk - added back dropped documentation patch - changed prefix for SYSFW and DM files to expected directory name - extended test coverage to 100% - documentation fixes - corrected formatting changes Changes in v2: - removed all external scripts - created ti-board-config etype to support generation of board config binaries - created ti-secure and ti-secure-rom etypes to handle signing instead of using external TI_SECURE_DEV_PKG - updated openssl btool to support x509 certificate generation - dropped Makefile changes to obtain external binary components, moving to using BINMAN_INDIRS to achieve the same v1: https://patchwork.ozlabs.org/project/uboot/cover/20230120101903.179959-1-n-… v2: https://patchwork.ozlabs.org/project/uboot/cover/20230404121342.446935-1-n-… Neha Malcom Francis (19): binman: ti-board-config: Add support for TI board config binaries binman: ti-secure: Add support for TI signing ti: sysfw: tiboot3: Add support for packaging sysfw.itb and tiboot3.bin j721e: schema: yaml: Add general schema and J721E board config files j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img j7200: yaml: Add J7200 board config files j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img am65x: yaml: Add AM65x board config files am65: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img am64x: yaml: Add board configs for AM64x am64x: dts: binman: Package tiboot3.bin, tispl.bin u-boot.img j721s2: yaml: Add board configs for J721S2 j721s2: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img am62: yaml: Add board configs for AM62 am625: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img am62a: yaml: Add board configs for AM62ax am62a: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img k3: tools: config.mk: Update makefile and remove scripts doc: board: ti: Update documentation for binman flow arch/arm/dts/k3-am625-r5-sk.dts | 1 + arch/arm/dts/k3-am625-sk-binman.dtsi | 529 +++ arch/arm/dts/k3-am625-sk-u-boot.dtsi | 2 + arch/arm/dts/k3-am62a-sk-binman.dtsi | 528 +++ arch/arm/dts/k3-am62a7-r5-sk.dts | 1 + arch/arm/dts/k3-am62a7-sk.dts | 1 + arch/arm/dts/k3-am642-evm-u-boot.dtsi | 2 + arch/arm/dts/k3-am642-r5-evm.dts | 1 + arch/arm/dts/k3-am64x-binman.dtsi | 569 ++++ arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 1 + .../dts/k3-am654-r5-base-board-u-boot.dtsi | 1 + arch/arm/dts/k3-am65x-binman.dtsi | 551 ++++ arch/arm/dts/k3-j7200-binman.dtsi | 529 +++ .../k3-j7200-common-proc-board-u-boot.dtsi | 2 + arch/arm/dts/k3-j721e-binman.dtsi | 732 +++++ .../k3-j721e-common-proc-board-u-boot.dtsi | 1 + .../arm/dts/k3-j721e-r5-common-proc-board.dts | 1 + arch/arm/dts/k3-j721s2-binman.dtsi | 613 ++++ .../k3-j721s2-common-proc-board-u-boot.dtsi | 2 + .../dts/k3-j721s2-r5-common-proc-board.dts | 1 + arch/arm/mach-k3/config.mk | 126 +- board/ti/am62ax/Kconfig | 2 + board/ti/am62ax/board-cfg.yaml | 36 + board/ti/am62ax/pm-cfg.yaml | 12 + board/ti/am62ax/rm-cfg.yaml | 1151 +++++++ board/ti/am62ax/sec-cfg.yaml | 375 +++ board/ti/am62x/Kconfig | 2 + board/ti/am62x/board-cfg.yaml | 36 + board/ti/am62x/pm-cfg.yaml | 12 + board/ti/am62x/rm-cfg.yaml | 1088 +++++++ board/ti/am62x/sec-cfg.yaml | 375 +++ board/ti/am64x/Kconfig | 2 + board/ti/am64x/board-cfg.yaml | 37 + board/ti/am64x/pm-cfg.yaml | 12 + board/ti/am64x/rm-cfg.yaml | 1400 ++++++++ board/ti/am64x/sec-cfg.yaml | 378 +++ board/ti/am65x/Kconfig | 2 + board/ti/am65x/board-cfg.yaml | 36 + board/ti/am65x/pm-cfg.yaml | 12 + board/ti/am65x/rm-cfg.yaml | 2068 ++++++++++++ board/ti/am65x/sec-cfg.yaml | 375 +++ board/ti/common/schema.yaml | 355 ++ board/ti/j721e/Kconfig | 4 + board/ti/j721e/board-cfg.yaml | 37 + board/ti/j721e/board-cfg_j7200.yaml | 36 + board/ti/j721e/pm-cfg.yaml | 13 + board/ti/j721e/pm-cfg_j7200.yaml | 12 + board/ti/j721e/rm-cfg.yaml | 2757 ++++++++++++++++ board/ti/j721e/rm-cfg_j7200.yaml | 2065 ++++++++++++ board/ti/j721e/sec-cfg.yaml | 379 +++ board/ti/j721e/sec-cfg_j7200.yaml | 378 +++ board/ti/j721s2/Kconfig | 2 + board/ti/j721s2/board-cfg.yaml | 37 + board/ti/j721s2/pm-cfg.yaml | 12 + board/ti/j721s2/rm-cfg.yaml | 2901 +++++++++++++++++ board/ti/j721s2/sec-cfg.yaml | 375 +++ board/ti/keys/custMpk.pem | 51 + board/ti/keys/ti-degenerate-key.pem | 10 + doc/board/ti/am62x_sk.rst | 20 +- doc/board/ti/j721e_evm.rst | 37 +- doc/board/ti/k3.rst | 67 +- scripts/Makefile.spl | 2 + tools/binman/btool/openssl.py | 244 ++ tools/binman/entries.rst | 113 + tools/binman/etype/ti_board_config.py | 269 ++ tools/binman/etype/ti_secure.py | 82 + tools/binman/etype/ti_secure_rom.py | 250 ++ tools/binman/etype/x509_cert.py | 87 +- tools/binman/ftest.py | 84 + tools/binman/pyproject.toml | 2 +- tools/binman/test/277_ti_board_cfg.dts | 11 + .../binman/test/278_ti_board_cfg_combined.dts | 25 + .../binman/test/279_ti_board_cfg_no_type.dts | 11 + tools/binman/test/279_ti_secure.dts | 17 + .../binman/test/280_ti_board_cfg_no_file.dts | 11 + tools/binman/test/280_ti_secure_rom.dts | 17 + .../281_ti_board_cfg_combined_no_file.dts | 13 + .../test/281_ti_secure_rom_combined.dts | 25 + .../test/282_ti_secure_rom_combined_a.dts | 24 + .../test/283_ti_secure_rom_combined_b.dts | 24 + .../test/284_ti_secure_rom_combined_c.dts | 21 + tools/binman/test/285_ti_secure_a.dts | 17 + tools/binman/test/286_ti_secure_b.dts | 18 + tools/binman/test/288_ti_secure_rom_a.dts | 19 + tools/binman/test/289_ti_secure_rom_b.dts | 18 + tools/binman/test/yaml/config.yaml | 19 + tools/binman/test/yaml/schema.yaml | 51 + tools/binman/test/yaml/schema_notype.yaml | 40 + tools/k3_fit_atf.sh | 123 - tools/k3_gen_x509_cert.sh | 262 -- 90 files changed, 22488 insertions(+), 564 deletions(-) create mode 100644 arch/arm/dts/k3-am625-sk-binman.dtsi create mode 100644 arch/arm/dts/k3-am62a-sk-binman.dtsi create mode 100644 arch/arm/dts/k3-am64x-binman.dtsi create mode 100644 arch/arm/dts/k3-am65x-binman.dtsi create mode 100644 arch/arm/dts/k3-j7200-binman.dtsi create mode 100644 arch/arm/dts/k3-j721e-binman.dtsi create mode 100644 arch/arm/dts/k3-j721s2-binman.dtsi create mode 100644 board/ti/am62ax/board-cfg.yaml create mode 100644 board/ti/am62ax/pm-cfg.yaml create mode 100644 board/ti/am62ax/rm-cfg.yaml create mode 100644 board/ti/am62ax/sec-cfg.yaml create mode 100644 board/ti/am62x/board-cfg.yaml create mode 100644 board/ti/am62x/pm-cfg.yaml create mode 100644 board/ti/am62x/rm-cfg.yaml create mode 100644 board/ti/am62x/sec-cfg.yaml create mode 100644 board/ti/am64x/board-cfg.yaml create mode 100644 board/ti/am64x/pm-cfg.yaml create mode 100644 board/ti/am64x/rm-cfg.yaml create mode 100644 board/ti/am64x/sec-cfg.yaml create mode 100644 board/ti/am65x/board-cfg.yaml create mode 100644 board/ti/am65x/pm-cfg.yaml create mode 100644 board/ti/am65x/rm-cfg.yaml create mode 100644 board/ti/am65x/sec-cfg.yaml create mode 100644 board/ti/common/schema.yaml create mode 100644 board/ti/j721e/board-cfg.yaml create mode 100644 board/ti/j721e/board-cfg_j7200.yaml create mode 100644 board/ti/j721e/pm-cfg.yaml create mode 100644 board/ti/j721e/pm-cfg_j7200.yaml create mode 100644 board/ti/j721e/rm-cfg.yaml create mode 100644 board/ti/j721e/rm-cfg_j7200.yaml create mode 100644 board/ti/j721e/sec-cfg.yaml create mode 100644 board/ti/j721e/sec-cfg_j7200.yaml create mode 100644 board/ti/j721s2/board-cfg.yaml create mode 100644 board/ti/j721s2/pm-cfg.yaml create mode 100644 board/ti/j721s2/rm-cfg.yaml create mode 100644 board/ti/j721s2/sec-cfg.yaml create mode 100644 board/ti/keys/custMpk.pem create mode 100644 board/ti/keys/ti-degenerate-key.pem create mode 100644 tools/binman/etype/ti_board_config.py create mode 100644 tools/binman/etype/ti_secure.py create mode 100644 tools/binman/etype/ti_secure_rom.py create mode 100644 tools/binman/test/277_ti_board_cfg.dts create mode 100644 tools/binman/test/278_ti_board_cfg_combined.dts create mode 100644 tools/binman/test/279_ti_board_cfg_no_type.dts create mode 100644 tools/binman/test/279_ti_secure.dts create mode 100644 tools/binman/test/280_ti_board_cfg_no_file.dts create mode 100644 tools/binman/test/280_ti_secure_rom.dts create mode 100644 tools/binman/test/281_ti_board_cfg_combined_no_file.dts create mode 100644 tools/binman/test/281_ti_secure_rom_combined.dts create mode 100644 tools/binman/test/282_ti_secure_rom_combined_a.dts create mode 100644 tools/binman/test/283_ti_secure_rom_combined_b.dts create mode 100644 tools/binman/test/284_ti_secure_rom_combined_c.dts create mode 100644 tools/binman/test/285_ti_secure_a.dts create mode 100644 tools/binman/test/286_ti_secure_b.dts create mode 100644 tools/binman/test/288_ti_secure_rom_a.dts create mode 100644 tools/binman/test/289_ti_secure_rom_b.dts create mode 100644 tools/binman/test/yaml/config.yaml create mode 100644 tools/binman/test/yaml/schema.yaml create mode 100644 tools/binman/test/yaml/schema_notype.yaml delete mode 100755 tools/k3_fit_atf.sh delete mode 100755 tools/k3_gen_x509_cert.sh -- 2.34.1

8 68