February 2023 - U-Boot

[RFC PATCH 00/17] sunxi: rework pinctrl and add T113s support
by Andre Przywara 21 Jun '23

21 Jun '23

Hi, this is some early attempt at supporting the new SoC series that covers the Allwinner D1 siblings R528 and T113s. They all share the same die, although the D1 and D1s use RISC-V cores, which requires more plumbing, to use the sunxi code across two architectures. Getting the R528 support in should help a bit in sorting out what's new peripheral code and what is architecture dependent. IIUC, Samuel has that running, although with some hacks, the number of which this series tries to reduce. The most interesting part of this is the pincontroller rework, this tackles two issues: - For the first time in the history of mainline Allwinner support the pincontroller changed the register layout. The code here tries to abstract the differences away, so both variants can share the code peacefully. - For the above mentioned reason, the pincontroller code is quite old, and is mostly spread out across arch/arm, in a pre-DM style, even though we have real DM support in U-Boot proper. We need the non-DM version for the (ARM-only?) legacy SPL, so can't get rid of that completely. This series also tries to modernise that code, and moves it into board/sunxi/, where it can be more easily shared with RISC-V. The preliminary MangoPi MQ-R bits on top are mostly for illustration purposes, and in case someone wants to give it a try. For some probably stupid reason MMC doesn't work, although the driver loads fine. Also this omits the DRAM code, although there is some GPLed code out there, which can be lifted into here, with some extra work. I would mostly appreciate to have some opinion on the pinctrl patches: I understand that patch 03/17 isn't strictly necessary, but I always disliked U-Boot's "use C structs to model MMIO register frames" approach, so thought now is the time to get rid of that ;-) Also I am unsure about patch 06/17, which seems like a step back (spreading per-SoC data over several files), but I actually aim at getting rid of cpu_sun[x]i.h altogether, since we should not really need it, except for some exceptions. The third patch I would like to hear feedback about is patch 08/17. Finally patch 14/17 would deserve some extra pair of eyes. Please let me know if you have any opinions! Cheers, Andre P.S. I understand there is some code to support those SoCs out there, apologies if I just re-implemented some of it. Please point me to patches that seem upstream-worthy, and I will happily integrate them in here, potentially replacing some of my patches. Andre Przywara (15): sunxi: remove CONFIG_SATAPWR sunxi: remove CONFIG_MACPWR pinctrl: sunxi: remove struct sunxi_gpio pinctrl: sunxi: add GPIO in/out wrappers pinctrl: sunxi: move pinctrl code and remove GPIO_EXTRA_HEADER pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h pinctrl: sunxi: add new D1 pinctrl support sunxi: introduce NCAT2 generation model pinctrl: sunxi: add Allwinner D1 pinctrl description sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup sunxi: clock: support D1/R528 PLL6 clock sunxi: add early Allwinner R528/T113 SoC support sunxi: refactor serial base addresses to avoid asm/arch/cpu.h arm: sunxi: add Allwinner T113s devicetree stub sunxi: add preliminary MangoPi MQ-R board support Samuel Holland (2): clk: sunxi: Add support for the D1 CCU riscv: dts: allwinner: Add the D1/D1s SoC devicetree arch/arm/Kconfig | 3 +- arch/arm/cpu/armv7/sunxi/sram.c | 1 + arch/arm/cpu/armv8/fel_utils.S | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/sun8i-t113s-mangopi-mq-r.dts | 54 ++ arch/arm/dts/sun8i-t113s.dtsi | 59 ++ arch/arm/include/asm/arch-sunxi/clock.h | 3 +- .../include/asm/arch-sunxi/clock_sun50i_h6.h | 8 + arch/arm/include/asm/arch-sunxi/cpu.h | 2 + arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 17 - .../include/asm/arch-sunxi/cpu_sun50i_h6.h | 7 - arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 9 - .../include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 49 + arch/arm/include/asm/arch-sunxi/mmc.h | 2 +- arch/arm/include/asm/arch-sunxi/prcm.h | 2 +- arch/arm/include/asm/arch-sunxi/serial.h | 32 + arch/arm/include/asm/arch-sunxi/timer.h | 2 +- arch/arm/mach-sunxi/Kconfig | 51 +- arch/arm/mach-sunxi/Makefile | 2 +- arch/arm/mach-sunxi/board.c | 9 +- arch/arm/mach-sunxi/clock_sun50i_h6.c | 38 +- arch/arm/mach-sunxi/cpu_info.c | 2 + arch/arm/mach-sunxi/dram_suniv.c | 2 +- arch/arm/mach-sunxi/gtbus_sun9i.c | 1 + arch/arm/mach-sunxi/pinmux.c | 78 -- arch/arm/mach-sunxi/spl_spi_sunxi.c | 1 + arch/arm/mach-sunxi/timer.c | 1 + arch/riscv/dts/sun20i-d1.dtsi | 66 ++ arch/riscv/dts/sun20i-d1s.dtsi | 76 ++ arch/riscv/dts/sunxi-d1-t113.dtsi | 15 + arch/riscv/dts/sunxi-d1s-t113.dtsi | 844 ++++++++++++++++++ board/sunxi/Makefile | 2 + board/sunxi/board.c | 25 +- board/sunxi/chip.c | 2 +- board/sunxi/dram_sun8i_r528.c | 9 + board/sunxi/pinctrl.c | 94 ++ common/spl/Kconfig | 2 +- configs/A10-OLinuXino-Lime_defconfig | 1 - configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 - configs/A20-OLinuXino-Lime2_defconfig | 1 - configs/A20-OLinuXino-Lime_defconfig | 1 - configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 - configs/A20-OLinuXino_MICRO_defconfig | 1 - configs/A20-Olimex-SOM-EVB_defconfig | 1 - configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 - configs/A20-Olimex-SOM204-EVB_defconfig | 1 - configs/Bananapi_M2_Ultra_defconfig | 1 - configs/Bananapi_defconfig | 1 - configs/Bananapro_defconfig | 1 - configs/Cubieboard2_defconfig | 1 - configs/Cubieboard_defconfig | 1 - configs/Cubietruck_defconfig | 1 - configs/Itead_Ibox_A20_defconfig | 1 - configs/Lamobo_R1_defconfig | 2 - configs/Linksprite_pcDuino3_Nano_defconfig | 1 - configs/Linksprite_pcDuino3_defconfig | 1 - configs/Mele_A1000_defconfig | 1 - configs/Orangepi_defconfig | 1 - configs/Orangepi_mini_defconfig | 1 - configs/Sinovoip_BPI_M3_defconfig | 1 - configs/bananapi_m1_plus_defconfig | 1 - configs/bananapi_m2_plus_h3_defconfig | 1 - configs/bananapi_m2_plus_h5_defconfig | 1 - configs/i12-tvbox_defconfig | 1 - configs/jesurun_q5_defconfig | 1 - configs/mangopi_mq_r_defconfig | 12 + configs/mixtile_loftq_defconfig | 1 - configs/nanopi_m1_plus_defconfig | 1 - configs/nanopi_neo_plus2_defconfig | 1 - configs/nanopi_r1s_h5_defconfig | 1 - configs/orangepi_pc2_defconfig | 1 - configs/orangepi_plus2e_defconfig | 1 - configs/orangepi_plus_defconfig | 2 - configs/orangepi_win_defconfig | 1 - configs/pine_h64_defconfig | 1 - configs/zeropi_defconfig | 1 - drivers/ata/ahci_sunxi.c | 9 + drivers/clk/sunxi/Kconfig | 6 + drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_d1.c | 101 +++ drivers/gpio/axp_gpio.c | 1 + drivers/gpio/sunxi_gpio.c | 30 +- drivers/i2c/sun6i_p2wi.c | 2 +- drivers/i2c/sun8i_rsb.c | 2 +- drivers/mmc/sunxi_mmc.c | 12 +- drivers/net/sun8i_emac.c | 9 +- drivers/net/sunxi_emac.c | 10 +- drivers/pinctrl/sunxi/Kconfig | 5 + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 43 +- drivers/video/hitachi_tx18d42vm_lcd.c | 1 + drivers/video/ssd2828.c | 1 - drivers/video/sunxi/sunxi_display.c | 1 + drivers/video/sunxi/sunxi_lcd.c | 1 + include/configs/sunxi-common.h | 2 +- include/dt-bindings/clock/sun20i-d1-ccu.h | 156 ++++ include/dt-bindings/clock/sun20i-d1-r-ccu.h | 19 + include/dt-bindings/reset/sun20i-d1-ccu.h | 77 ++ include/dt-bindings/reset/sun20i-d1-r-ccu.h | 16 + .../arch-sunxi/gpio.h => include/sunxi_gpio.h | 102 ++- 99 files changed, 1936 insertions(+), 296 deletions(-) create mode 100644 arch/arm/dts/sun8i-t113s-mangopi-mq-r.dts create mode 100644 arch/arm/dts/sun8i-t113s.dtsi create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h create mode 100644 arch/arm/include/asm/arch-sunxi/serial.h delete mode 100644 arch/arm/mach-sunxi/pinmux.c create mode 100644 arch/riscv/dts/sun20i-d1.dtsi create mode 100644 arch/riscv/dts/sun20i-d1s.dtsi create mode 100644 arch/riscv/dts/sunxi-d1-t113.dtsi create mode 100644 arch/riscv/dts/sunxi-d1s-t113.dtsi create mode 100644 board/sunxi/dram_sun8i_r528.c create mode 100644 board/sunxi/pinctrl.c create mode 100644 configs/mangopi_mq_r_defconfig create mode 100644 drivers/clk/sunxi/clk_d1.c create mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h create mode 100644 include/dt-bindings/clock/sun20i-d1-r-ccu.h create mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h create mode 100644 include/dt-bindings/reset/sun20i-d1-r-ccu.h rename arch/arm/include/asm/arch-sunxi/gpio.h => include/sunxi_gpio.h (74%) -- 2.35.5

6 61

[PATCH] usb: eth: lan78xx: Fix logic in lan78xx_read_otp() to avoid a warning
by Tom Rini 20 Jun '23

20 Jun '23

In lan78xx_read_otp() we want to know if sig is LAN78XX_OTP_INDICATOR_1 or LAN78XX_OTP_INDICATOR_2. In the case of matching the first one we set offset to itself, and clang warns about this. Rework the logic so that if sig is the second indicator we adjust the offset as today and if it does not match the first indicator we return -EINVAL Cc: Marek Vasut <marex(a)denx.de> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- drivers/usb/eth/lan78xx.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/usb/eth/lan78xx.c b/drivers/usb/eth/lan78xx.c index e34ad2603fbb..d147412990de 100644 --- a/drivers/usb/eth/lan78xx.c +++ b/drivers/usb/eth/lan78xx.c @@ -146,11 +146,9 @@ static int lan78xx_read_otp(struct usb_device *udev, u32 offset, ret = lan78xx_read_raw_otp(udev, 0, 1, &sig); if (!ret) { - if (sig == LAN78XX_OTP_INDICATOR_1) - offset = offset; - else if (sig == LAN78XX_OTP_INDICATOR_2) + if (sig == LAN78XX_OTP_INDICATOR_2) offset += 0x100; - else + else if (sig != LAN78XX_OTP_INDICATOR_1) return -EINVAL; ret = lan78xx_read_raw_otp(udev, offset, length, data); if (ret) -- 2.17.1

2 2

[PATCH] spl: spl-nor: return error if no valid image was loaded
by Mario Kicherer 20 Jun '23

20 Jun '23

If only FIT images are enabled and loading the FIT image fails, spl_nor_load_image() should return an error instead of zero. Without this patch: >>SPL: board_init_r() spl_init Trying to boot from NOR Unsupported OS image.. Jumping nevertheless.. image entry point: 0x0 With patch: >>SPL: board_init_r() spl_init Trying to boot from NOR SPL: failed to boot from all boot devices (err=-6) .### ERROR ### Please RESET the board ### Signed-off-by: Mario Kicherer <dev(a)kicherer.org> --- common/spl/spl_nor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index ffb3566d89..e75127b275 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -120,6 +120,6 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, &hdr); } - return 0; + return -EINVAL; } SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image); -- 2.34.1

2 1

[PATCH] spl: spl_nor: use panic instead of hang if booting fails
by Mario Kicherer 20 Jun '23

20 Jun '23

On systems without a watchdog, using hang() prevents a system to recover from an error. For example, a board could implement a boot counter to switch to an alternative load address after some failed tries. Signed-off-by: Mario Kicherer <dev(a)kicherer.org> --- common/spl/spl.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/common/spl/spl.c b/common/spl/spl.c index 2855cdd117..d1aa2fb8a9 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -822,11 +822,10 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (ret) { if (CONFIG_IS_ENABLED(SHOW_ERRORS) && CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT)) - printf(SPL_TPL_PROMPT "failed to boot from all boot devices (err=%d)\n", - ret); + panic(SPL_TPL_PROMPT "failed to boot from all boot devices (err=%d)\n", + ret); else - puts(SPL_TPL_PROMPT "failed to boot from all boot devices\n"); - hang(); + panic_str(SPL_TPL_PROMPT "failed to boot from all boot devices\n"); } spl_perform_fixups(&spl_image); -- 2.34.1

2 1

[PATCH] Revert "lib: sparse: Make CHUNK_TYPE_RAW buffer aligned"
by Gary Bisson 17 Jun '23

17 Jun '23

This reverts commit 62649165cb02ab95b57360bb362886935f524f26. The patch decreased the write performance quite a bit. Here is an example on an i.MX 8M Quad platform. - Before the revert: Sending sparse 'vendor' 1/2 (516436 KB) OKAY [ 5.113s] Writing 'vendor' OKAY [128.335s] Sending sparse 'vendor' 2/2 (76100 KB) OKAY [ 0.802s] Writing 'vendor' OKAY [ 27.902s] - After the revert: Sending sparse 'vendor' 1/2 (516436 KB) OKAY [ 5.310s] Writing 'vendor' OKAY [ 18.041s] Sending sparse 'vendor' 2/2 (76100 KB) OKAY [ 1.244s] Writing 'vendor' OKAY [ 2.663s] Considering that the patch only moves buffer around to avoid a warning message about misaligned buffers, let's keep the best performances. Signed-off-by: Gary Bisson <gary.bisson(a)boundarydevices.com> Signed-off-by: Troy Kisky <troy.kisky(a)boundarydevices.com> --- lib/image-sparse.c | 69 ++++++---------------------------------------- 1 file changed, 8 insertions(+), 61 deletions(-) diff --git a/lib/image-sparse.c b/lib/image-sparse.c index 5ec0f94ab3e..d80fdbbf58e 100644 --- a/lib/image-sparse.c +++ b/lib/image-sparse.c @@ -46,66 +46,9 @@ #include <asm/cache.h> #include <linux/math64.h> -#include <linux/err.h> static void default_log(const char *ignored, char *response) {} -static lbaint_t write_sparse_chunk_raw(struct sparse_storage *info, - lbaint_t blk, lbaint_t blkcnt, - void *data, - char *response) -{ - lbaint_t n = blkcnt, write_blks, blks = 0, aligned_buf_blks = 100; - uint32_t *aligned_buf = NULL; - - if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { - write_blks = info->write(info, blk, n, data); - if (write_blks < n) - goto write_fail; - - return write_blks; - } - - aligned_buf = memalign(ARCH_DMA_MINALIGN, info->blksz * aligned_buf_blks); - if (!aligned_buf) { - info->mssg("Malloc failed for: CHUNK_TYPE_RAW", response); - return -ENOMEM; - } - - while (blkcnt > 0) { - n = min(aligned_buf_blks, blkcnt); - memcpy(aligned_buf, data, n * info->blksz); - - /* write_blks might be > n due to NAND bad-blocks */ - write_blks = info->write(info, blk + blks, n, aligned_buf); - if (write_blks < n) { - free(aligned_buf); - goto write_fail; - } - - blks += write_blks; - data += n * info->blksz; - blkcnt -= n; - } - - free(aligned_buf); - return blks; - -write_fail: - if (IS_ERR_VALUE(write_blks)) { - printf("%s: Write failed, block #" LBAFU " [" LBAFU "] (%lld)\n", - __func__, blk + blks, n, (long long)write_blks); - info->mssg("flash write failure", response); - return write_blks; - } - - /* write_blks < n */ - printf("%s: Write failed, block #" LBAFU " [" LBAFU "]\n", - __func__, blk + blks, n); - info->mssg("flash write failure(incomplete)", response); - return -1; -} - int write_sparse_image(struct sparse_storage *info, const char *part_name, void *data, char *response) { @@ -209,11 +152,15 @@ int write_sparse_image(struct sparse_storage *info, return -1; } - blks = write_sparse_chunk_raw(info, blk, blkcnt, - data, response); - if (blks < 0) + blks = info->write(info, blk, blkcnt, data); + /* blks might be > blkcnt (eg. NAND bad-blocks) */ + if (blks < blkcnt) { + printf("%s: %s" LBAFU " [" LBAFU "]\n", + __func__, "Write failed, block #", + blk, blks); + info->mssg("flash write failure", response); return -1; - + } blk += blks; bytes_written += ((u64)blkcnt) * info->blksz; total_blocks += chunk_header->chunk_sz; -- 2.35.1

4 6

[PATCH] bootstd: Make BOOTSTD_FULL depend on BOOTSTD
by Simon Glass 14 Jun '23

14 Jun '23

Move BOOTSTD_FULL down in the file so that it can be enabled only when BOOTSTD is enabled. This prevents a build error if BOOTSTD is disabled but BOOTSTD_FULL is enabled. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- boot/Kconfig | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/boot/Kconfig b/boot/Kconfig index 5f491625c82..47952bbba23 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -371,19 +371,6 @@ config BOOTSTD U-Boot) - bootflow - a description of how to boot (owned by the distro) -config BOOTSTD_FULL - bool "Enhanced features for standard boot" - default y if SANDBOX - help - This enables various useful features for standard boot, which are not - essential for operation: - - - bootdev, bootmeth commands - - extra features in the bootflow command - - support for selecting the ordering of bootmeths ("bootmeth order") - - support for selecting the ordering of bootdevs using the devicetree - as well as the "boot_targets" environment variable - config SPL_BOOTSTD bool "Standard boot support in VPL" depends on SPL && SPL_DM && SPL_OF_CONTROL && SPL_BLK @@ -406,6 +393,19 @@ config VPL_BOOTSTD if BOOTSTD +config BOOTSTD_FULL + bool "Enhanced features for standard boot" + default y if SANDBOX + help + This enables various useful features for standard boot, which are not + essential for operation: + + - bootdev, bootmeth commands + - extra features in the bootflow command + - support for selecting the ordering of bootmeths ("bootmeth order") + - support for selecting the ordering of bootdevs using the devicetree + as well as the "boot_targets" environment variable + config BOOTSTD_DEFAULTS bool "Select some common defaults for standard boot" depends on BOOTSTD -- 2.39.2.637.g21b0678d19-goog

3 2

Setting MAC address from I2C EEPROM - debug / commands? (Xilinx)
by David Antliff 12 Jun '23

12 Jun '23

Hi, I'm looking to extract the board's MAC address from serial I2C EEPROM at boot time, so I'm trying to work out how I can tell if U-Boot is actually able to communicate with this EEPROM, outside of manual i2c commands. I have set CONFIG_ZYNQ_MAC_IN_EEPROM and CONFIG_ZYNQ_MAC_IN_EEPROM however I'm not completely sure that this is working with UltraScale+ Zynq MPSoC boards - I'm using a ZCU208. There's no log message on the U-Boot console to say that there was an attempt to read the MAC address, and with ethaddr unset, this variable is set by U-Boot to the value taken from the device tree rather than EEPROM: ethernet@ff0e0000 { ... local-mac-address = [00 0a 35 00 22 01]; ... I would expect it to be 00 0a 35 07 60 1c based on the contents of the EEPROM. I would like to understand how to debug this. I read that the command "eeprom" has been deprecated for some time (I don't have it enabled), with some I2C serial EEPROM devices now supported by the "Driver Model" - aka DM. Thus I did find: > dm uclass ... uclass 39: i2c_eeprom 0 eeprom@54 @ 7dd21420 ... And I'm able to communicate with the device via commands like: ZynqMP> i2c md 54 0.2 40 200000 0000: 5a 43 55 32 30 38 ff ff ff ff ff ff ff ff ff ff ZCU208.......... 0010: ff 41 30 32 38 33 32 32 30 34 31 34 33 33 32 38 .A02832204143328 0020: 31 2e 33 00 0a 35 07 60 1c 00 0a 35 07 60 1d 00 1.3..5.`...5.`.. 0030: 0a 35 07 60 1e 00 0a 35 07 60 1f 41 08 ff ff ff .5.`...5.`.A.... The MAC address is 6 bytes starting at offset 0x23 (00 0a 35 07 60 1c). My question is - is the 'i2c' command now the accepted and best way to interact with an I2C EEPROM? Or is there another command I can enable (other than "eeprom") that will provide a generic interface for accessing EEPROMs and prove that U-Boot can "see" this device? The EEPROM device in question is an M24128. CONFIG_SYS_I2C_EEPROM_ADDR=0x54 CONFIG_SYS_I2C_EEPROM_BUS=6 CONFIG_SYS_EEPROM_SIZE=16384 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x23 CONFIG_ZYNQ_MAC_IN_EEPROM=y U-Boot 2021.01 (Xilinx fork: git://github.com/Xilinx/u-boot-xlnx.git) P.S. if this is better directed to Xilinx or the Xilinx community then I'm happy to do that, but in case it's a more generic U-Boot issue I thought it best to ask here first. Please don't flame me for using Xilinx, I'm trying to do my best with what I'm given. -- David.

4 11

[PATCH] spl: spl_fit: add weak prototype for fpga_load
by Eugen Hristev 09 Jun '23

09 Jun '23

In case OPTIMIZE_DEBUG is set, unused code will not be optimized out, hence the reference to fpga_load will be compiled. if DM_FPGA and SPL_FPGA are not set, the build will fail with : aarch64-none-linux-gnu-ld.bfd: common/spl/spl_fit.o: in function `spl_fit_upload_fpga': u-boot/common/spl/spl_fit.c:595: undefined reference to `fpga_load' By adding a weak prototype, build is successful. Signed-off-by: Eugen Hristev <eugen.hristev(a)collabora.com> --- common/spl/spl_fit.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index c51482b3b659..ca2e337b1ec4 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -570,6 +570,12 @@ static void warn_deprecated(const char *msg) printf("\tSee doc/uImage.FIT/source_file_format.txt\n"); } +__weak int fpga_load(int devnum, const void *buf, size_t bsize, + bitstream_type bstype, int flags) +{ + return 0; +} + static int spl_fit_upload_fpga(struct spl_fit_info *ctx, int node, struct spl_image_info *fpga_image) { -- 2.34.1

1 1

[PATCH v5 0/2] arm: dts: rockchip: rk3399: usb: ehci: Fix EHCI probe in rk3399 to access peripherals by USB 2.
by Xavier Drudis Ferran 04 Jun '23

04 Jun '23

arch/arm/dts/rk3399.dtsi has a node usb_host0_ehci: usb@fe380000 { compatible = "generic-ehci"; with clocks: clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, <&u2phy0>; The first 2 refer to nodes with class UCLASS_CLK, but &u2phy0 has class UCLASS_PHY. u2phy0: usb2phy@e450 { compatible = "rockchip,rk3399-usb2phy"; Since clk_get_bulk() only looks for devices with UCLASS_CLK, it fails with -ENODEV and then ehci_usb_probe() aborts. The consequence is peripherals connected to a USB 2 port (e.g. in a Rock Pi 4 one of the two ports nearer the edge) not being detected. They're detected if CONFIG_USB_OHCI_GENERIC is selected in Kconfig, because ohci_usb_probe() does not abort when one clk_get_by_index() fails, but then they work in USB 1 mode,. rk3399.dtsi comes from linux and the u2phy0 was added[1] to the clock list in: commit b5d1c57299734f5b54035ef2e61706b83041f20c Author: William wu <wulf(a)rock-chips.com> Date: Wed Dec 21 18:41:05 2016 +0800 arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399 We found that the suspend process was blocked when it run into ehci/ohci module due to clk-480m of usb2-phy was disabled. [...] Suspend concerns don't apply to U-Boot, and the problem with U-Boot failing to probe EHCI doesn't apply to linux, because in linux rockchip_usb2phy_clk480m_register makes u2phy0 a proper clock provider when called by rockchip_usb2phy_probe(). So I can think of a few alternative solutions: 1- Change ehci_usb_probe() to make it more similar to ohci_usb_probe(), and survive failure to get one clock. Looks a little harder, and I don't know whether it could break something if it ignored a clock that was important for something else than suspend. (tried in v2) 2- Change rk3399.dtsi effecttively reverting the linux commit b5d1c57299734f5b54035ef2e61706b83041f20c. This dealigns the .dtsi from linux and seems fragile at the next synchronisation. 3- Change the clock list in rk3399-u-boot.dtsi or somewhere else. This survives .dts* sync but may survive "too much" and miss some change from linux that we might want. (tried in v1) 4- Enable CONFIG_USB_OHCI_GENERIC and use the ports in USB 1 mode. This would need to be made for all boards using rk3399. In a simple test reading one file from USB storage it gave 769.5 KiB/s instead of 20.5 MiB/s with solution 2. 5- Trying to replicate linux and have usb2phy somehow provide a clk, or have a separate clock device for usb2phy in addition to the phy device. (tried in v3 and this v5, v4 did it wrong) This series is a third attempt to implement option 5 as Marek Vasut requested in December 5th. Options 1 and 3 didn't get through[2,3]. The first patch in the series (identical to v3) just registers usb2phy as a clock driver, without any specific operations, so that ehci-generic.c finds it and is happy. It worked in my tests on a Rock Pi 4 B+ (rk3399). Since Marek Vasut objected to an operationless driver[4], the second patch adds enable and disable operations adapted from linux prepare and unprepare operations (and round_rate(), which doesn't seem very useful anyway since it's a fixed clock). Since there're no users of this clock in u-boot, I can't see any difference in my tests with only the first patch or both, so I can't be sure it really works if it's ever needed, but it's hopefully more complete. Links: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/ [2] https://patchwork.ozlabs.org/project/uboot/patch/20220701185959.GC1700@begu… [3] https://patchwork.ozlabs.org/project/uboot/patch/Y44+ayJfUlI08ptM@localhost… [4] https://patchwork.ozlabs.org/project/uboot/patch/Y5IWpjYLB4aXMy9o@localhost… Cc: Simon Glass <sjg(a)chromium.org> Cc: Philipp Tomsich <philipp.tomsich(a)vrull.eu> Cc: Kever Yang <kever.yang(a)rock-chips.com> Cc: Lukasz Majewski <lukma(a)denx.de> Cc: Sean Anderson <seanga2(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Christoph Fritz <chf.fritz(a)googlemail.com> Signed-off-by: Xavier Drudis Ferran <xdrudis(a)tinet.cat> --- Changes: v5: fixes a bug that Christoph Fritz discovered, consisting in the wrong eror code returned when enabling or disabling the clock because property_enable() returns an error code in linux but the modified register value in U-Boot. This caused the clk disable to abort before freeing the clock and it apparently left things bad enough to cause a hang or a reset. v4: move v3 to one patch in the series and add a second patch to add operations to enable disable the usb2phy 480Mhz clock. Also, honour clock-output-names for what is worth. v3: implement option 5 (bind usb2phy as a clk driver too) instead of option 1 (ehci-generic.c tolerates missing clocks). v2: implement option 1 (ehci-generic.c tolerates missing clocks) instead of option 3 (change dts node to remove the missing clock).

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[PATCH] arm: dts: ast2600: Add I2C pinctrl
by Eddie James 01 Jun '23

01 Jun '23

Set the pinctrl groups for each I2C bus. These are essential to I2C operating correctly. Signed-off-by: Eddie James <eajames(a)linux.ibm.com> --- arch/arm/dts/ast2600.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index 64074309b7..ef5b131ac0 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -833,6 +833,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; status = "disabled"; }; @@ -846,6 +848,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_default>; status = "disabled"; }; @@ -859,6 +863,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; }; i2c3: i2c@200 { @@ -871,6 +877,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; }; i2c4: i2c@280 { @@ -883,6 +891,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; }; i2c5: i2c@300 { @@ -895,6 +905,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; }; i2c6: i2c@380 { @@ -907,6 +919,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; }; i2c7: i2c@400 { @@ -919,6 +933,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; }; i2c8: i2c@480 { @@ -931,6 +947,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; }; i2c9: i2c@500 { @@ -943,6 +961,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; status = "disabled"; }; @@ -956,6 +976,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; status = "disabled"; }; @@ -969,6 +991,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; status = "disabled"; }; @@ -982,6 +1006,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; status = "disabled"; }; @@ -995,6 +1021,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; status = "disabled"; }; @@ -1008,6 +1036,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c15_default>; status = "disabled"; }; @@ -1021,6 +1051,8 @@ bus-frequency = <100000>; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_APB2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c16_default>; status = "disabled"; }; @@ -1246,6 +1278,7 @@ function = "I2C1"; groups = "I2C1"; }; + pinctrl_i2c2_default: i2c2_default { function = "I2C2"; groups = "I2C2"; -- 2.31.1

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