February 2023 - U-Boot

[RFC PATCH] mxs: Don't enable 4P2 reg if mx28 is powered only from DCDC_BATT without 5V
by Alan Kay 19 Dec '23

19 Dec '23

mxs_power_enable_4p2() was added to mxs_batt_boot() in 'commit a0f97610757d ("ARM: mxs: Enable DCDC converter for battery boot")' to enable DCDC converter when board is powered from 5V and has detected sufficient battery voltage. This involves enabling 4P2 regulator and there is a code in mxs_power_enable_4p2() that disables VDDIO, VDDA, VDDD outputs of the DCDC converter and enables BO for each power rail e.g. setbits_le32(&power_regs->hw_power_vddioctrl, POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); In case the mx28 is powered by the 5V source and linear regulators are supplying power to the VDDIO, VDDA, VDDD rails there is no issue. However if the mx28 is powered by the DCDC_BATT source only without 5V, disabling the DCDC converter outputs causes brownout power down. The proposed solution is not to call mxs_power_enable_4p2() at all if the mx28 is powered by the DCDC_BATT source only. There is no reason to enable 4P2 regulator in this case and setup of all registers is done in mxs_batt_boot(). Also there is no need to enable 5V brownout in mxs_power_init() in this case. Please consider if this is acceptable and I will submit a proper patch. Signed-off-by: Alan Kay <alan(a)londelec.com> --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index c33170f06d..c8feadce54 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -752,7 +752,9 @@ static void mxs_batt_boot(void) POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); +#ifndef CONFIG_SPL_MXS_NO_VDD5V_SOURCE mxs_power_enable_4p2(); +#endif } /** @@ -1267,7 +1269,9 @@ void mxs_power_init(void) POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); +#ifndef CONFIG_SPL_MXS_NO_VDD5V_SOURCE writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); +#endif early_delay(1000); } -- 2.25.1

4 6

[PATCH v1 0/2] Fix host tools build without LIBCRYPTO support
by Paul-Erwan Rio 13 Dec '23

13 Dec '23

A target-independent configuration exists to enable/disable crypto feature when building the host tools. But the crypto-free build is broken. Paul-Erwan Rio (2): tools: kwbimage: disable secure boot build without LIBCRYPTO support tools: fix build without LIBCRYPTO support include/image.h | 2 +- tools/Kconfig | 1 + tools/fit_image.c | 2 +- tools/image-host.c | 2 ++ tools/kwbimage.c | 18 ++++++++++++++++++ tools/mkimage.c | 5 +++-- 6 files changed, 26 insertions(+), 4 deletions(-) -- 2.39.0

5 10

[PATCH] mtd: spi-nor-core: Implement spi_nor_read_sfdp_dma_unsafe() for sfdp parse
by Vaishnav Achath 12 Dec '23

12 Dec '23

During SFDP header parse and BFPT parse, structures in stack are used to perform spi_nor_read_sfdp() which expects a dma-safe buffer. This commit introduces spi_nor_read_sfdp_dma_unsafe() to wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer which is the same implementation in Linux (drivers/mtd/spi-nor/sfdp.c). Signed-off-by: Vaishnav Achath <vaishnav.a(a)ti.com> --- drivers/mtd/spi/spi-nor-core.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 3b7c817c02..90d05da1d8 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2022,6 +2022,36 @@ read_err: return ret; } +/** + * spi_nor_read_sfdp_dma_unsafe() - read Serial Flash Discoverable Parameters. + * @nor: pointer to a 'struct spi_nor' + * @addr: offset in the SFDP area to start reading data from + * @len: number of bytes to read + * @buf: buffer where the SFDP data are copied into + * + * Wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer as @buf is now not + * guaranteed to be dma-safe. + * + * Return: -ENOMEM if kmalloc() fails, the return code of spi_nor_read_sfdp() + * otherwise. + */ +static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr, + size_t len, void *buf) +{ + void *dma_safe_buf; + int ret; + + dma_safe_buf = kmalloc(len, GFP_KERNEL); + if (!dma_safe_buf) + return -ENOMEM; + + ret = spi_nor_read_sfdp(nor, addr, len, dma_safe_buf); + memcpy(buf, dma_safe_buf, len); + kfree(dma_safe_buf); + + return ret; +} + /* Fast Read settings. */ static void @@ -2195,7 +2225,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, bfpt_header->length * sizeof(u32)); addr = SFDP_PARAM_HEADER_PTP(bfpt_header); memset(&bfpt, 0, sizeof(bfpt)); - err = spi_nor_read_sfdp(nor, addr, len, &bfpt); + err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt); if (err < 0) return err; @@ -2480,7 +2510,7 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, int i, err; /* Get the SFDP header. */ - err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header); + err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(header), &header); if (err < 0) return err; -- 2.17.1

4 4

[PATCH v1 1/1] Makefile.lib: Always rebuild DSDT
by Andy Shevchenko 09 Dec '23

09 Dec '23

The dsdt.asl is usually combined out of several files that are included in the main one. Whenever we change the content of any of such files, build system is not able to recognize them. Hence the easiest way is to force DSDT rebuild each time we run make. Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- scripts/Makefile.lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 07696e86bb54..8c3c893b398a 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -441,7 +441,7 @@ cmd_acpi_c_asl= \ iasl -p $@ -tc $(ASL_TMP) $(if $(KBUILD_VERBOSE:1=), >/dev/null) && \ mv $(patsubst %.c,%.hex,$@) $@ -$(obj)/dsdt.c: $(src)/dsdt.asl +$(obj)/dsdt.c: $(src)/dsdt.asl FORCE $(call cmd,acpi_c_asl) $(Q)sed -i -e "s,dsdt_aml_code,AmlCode," $@ -- 2.33.0

5 9

[PATCH] pci: ecm generic: use dev_read_() interface
by Mayuresh Chitale 10 Nov '23

10 Nov '23

Use dev_read_() api instead of the fdtdec API to fetch the host controller's reg property value. This is similar to the other host controller drivers such as Sifive, Rockchip etc. Without this change, enabling CONFIG_OF_LIVE breaks the PCIe enumeration on Qemu Risc-V virt machine. The issue is described in the link below: Link: https://source.denx.de/u-boot/custodians/u-boot-dm/-/issues/1 Signed-off-by: Mayuresh Chitale <mchitale(a)ventanamicro.com> --- drivers/pci/pcie_ecam_generic.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c index 1a9f9aec2e..f0effe0001 100644 --- a/drivers/pci/pcie_ecam_generic.c +++ b/drivers/pci/pcie_ecam_generic.c @@ -132,19 +132,14 @@ static int pci_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf, static int pci_generic_ecam_of_to_plat(struct udevice *dev) { struct generic_ecam_pcie *pcie = dev_get_priv(dev); - struct fdt_resource reg_res; - DECLARE_GLOBAL_DATA_PTR; - int err; - - err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg", - 0, &reg_res); - if (err < 0) { - pr_err("\"reg\" resource not found\n"); - return err; - } - - pcie->size = fdt_resource_size(&reg_res); - pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE); + fdt_addr_t addr; + fdt_size_t size; + + addr = dev_read_addr_size(dev, "reg", &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + pcie->size = size; + pcie->cfg_base = map_physmem(addr, pcie->size, MAP_NOCACHE); return 0; } -- 2.34.1

3 5

[PATCH] dfu: add CONFIG_DFU_NAME_MAX_SIZE configuration
by Jaehoon Chung 07 Nov '23

07 Nov '23

Add CONFIG_DFU_NAME_MAX_SIZE to change the proper size. If name is longer than default size, it can do wrong behavior during updating image. So it need to change the proper maximum size. This patch is proviced the solution to change value with configuration. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/dfu/Kconfig | 9 +++++++++ include/dfu.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 8d7f13dcb0b5..a181f0b8d7ba 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -111,5 +111,14 @@ config SYS_DFU_MAX_FILE_SIZE the buffer once we've been given the whole file. Define this to the maximum filesize (in bytes) for the buffer. If undefined it defaults to the CONFIG_SYS_DFU_DATA_BUF_SIZE. + +config DFU_NAME_MAX_SIZE + int "Size of the name to be added in dfu entity" + default 32 + depends on DFU + help + This value is used to maximum size. If name is longer than default size, + we need to change the proper maximum size. + endif endmenu diff --git a/include/dfu.h b/include/dfu.h index dcb9cd9d799a..948596f367d9 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -99,7 +99,7 @@ struct virt_internal_data { int dev_num; }; -#define DFU_NAME_SIZE 32 +#define DFU_NAME_SIZE CONFIG_DFU_NAME_MAX_SIZE #ifndef DFU_DEFAULT_POLL_TIMEOUT #define DFU_DEFAULT_POLL_TIMEOUT 0 #endif -- 2.25.1

3 8

[PATCH] net: dw_eth_qos: Add 64-bit addressing
by Ley Foon Tan 06 Nov '23

06 Nov '23

Set upper 32bit address for DMA descriptors and buffer address to support 64-bit addressing. Signed-off-by: Ley Foon Tan <leyfoon.tan(a)starfivetech.com> --- drivers/net/dwc_eth_qos.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index afc47b56ff..a21dbbda72 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -745,6 +745,7 @@ static int eqos_start(struct udevice *dev) u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl; ulong last_rx_desc; ulong desc_pad; + ulong addr64; debug("%s(dev=%p):\n", __func__, dev); @@ -1008,25 +1009,25 @@ static int eqos_start(struct udevice *dev) for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) { struct eqos_desc *rx_desc = eqos_get_desc(eqos, i, true); - rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf + - (i * EQOS_MAX_PACKET_SIZE)); + + addr64 = (ulong)(eqos->rx_dma_buf + (i * EQOS_MAX_PACKET_SIZE)); + rx_desc->des0 = lower_32_bits(addr64); + rx_desc->des1 = upper_32_bits(addr64); rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; mb(); eqos->config->ops->eqos_flush_desc(rx_desc); - eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf + - (i * EQOS_MAX_PACKET_SIZE), - EQOS_MAX_PACKET_SIZE); + eqos->config->ops->eqos_inval_buffer((void *)addr64, EQOS_MAX_PACKET_SIZE); } - writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress); - writel((ulong)eqos_get_desc(eqos, 0, false), - &eqos->dma_regs->ch0_txdesc_list_address); + addr64 = (ulong)eqos_get_desc(eqos, 0, false); + writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_haddress); + writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_address); writel(EQOS_DESCRIPTORS_TX - 1, &eqos->dma_regs->ch0_txdesc_ring_length); - writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress); - writel((ulong)eqos_get_desc(eqos, 0, true), - &eqos->dma_regs->ch0_rxdesc_list_address); + addr64 = (ulong)eqos_get_desc(eqos, 0, true); + writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_haddress); + writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_address); writel(EQOS_DESCRIPTORS_RX - 1, &eqos->dma_regs->ch0_rxdesc_ring_length); @@ -1131,8 +1132,8 @@ static int eqos_send(struct udevice *dev, void *packet, int length) eqos->tx_desc_idx++; eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX; - tx_desc->des0 = (ulong)eqos->tx_dma_buf; - tx_desc->des1 = 0; + tx_desc->des0 = lower_32_bits((ulong)eqos->tx_dma_buf); + tx_desc->des1 = upper_32_bits((ulong)eqos->tx_dma_buf); tx_desc->des2 = length; /* * Make sure that if HW sees the _OWN write below, it will see all the @@ -1205,14 +1206,17 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) for (idx = eqos->rx_desc_idx - idx_mask; idx <= eqos->rx_desc_idx; idx++) { + ulong addr64; + rx_desc = eqos_get_desc(eqos, idx, true); rx_desc->des0 = 0; + rx_desc->des1 = 0; mb(); eqos->config->ops->eqos_flush_desc(rx_desc); eqos->config->ops->eqos_inval_buffer(packet, length); - rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf + - (idx * EQOS_MAX_PACKET_SIZE)); - rx_desc->des1 = 0; + addr64 = (ulong)(eqos->rx_dma_buf + (idx * EQOS_MAX_PACKET_SIZE)); + rx_desc->des0 = lower_32_bits(addr64); + rx_desc->des1 = upper_32_bits(addr64); rx_desc->des2 = 0; /* * Make sure that if HW sees the _OWN write below, -- 2.25.1

2 1

[PATCH] rpi: Use OF_BOARD rather than OF_EMBED
by Peter Robinson 23 Sep '23

23 Sep '23

The use of OF_EMBED isn't recommended for standard use and the OF_BOARD is actually a better fit for the Raspberry Pi as the prior firmware provides a DT that can be used by U-Boot and the subsequent OS too, but it still allows the loading of a DT from disk as well if users wish to use the upstream kernel DT. Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> --- configs/rpi_0_w_defconfig | 2 +- configs/rpi_2_defconfig | 2 +- configs/rpi_3_32b_defconfig | 2 +- configs/rpi_3_b_plus_defconfig | 2 +- configs/rpi_3_defconfig | 2 +- configs/rpi_4_32b_defconfig | 1 + configs/rpi_4_defconfig | 1 + configs/rpi_arm64_defconfig | 1 + configs/rpi_defconfig | 2 +- 9 files changed, 9 insertions(+), 6 deletions(-) diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index 5249b29d76c..8c217848ca2 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -23,7 +23,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 154284765f4..bfc5679fb7e 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -24,7 +24,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index ef1f25d2ad7..54cdcee980a 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -23,7 +23,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index 154615d78a1..3008c7a1c18 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -22,7 +22,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index f0cf7f8e236..f7b9108ba00 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -22,7 +22,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig index 713b2ee231c..fa20ab767fe 100644 --- a/configs/rpi_4_32b_defconfig +++ b/configs/rpi_4_32b_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y +CONFIG_OF_BOARD=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 24f70b14fe8..741d4dbbbf4 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y +CONFIG_OF_BOARD=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index 1d1ff12a58c..5e1195dd786 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y +CONFIG_OF_BOARD=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 28b92b14456..1504093eddf 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -23,7 +23,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -- 2.39.2

3 2

PSCI: prefetch abort with Mainline linux (even with rockchip u-boot)
by Jagan Teki 13 Sep '23

13 Sep '23

Hi Kever and Heiko, Rockchip 32-bit SoC, like rv1126 seems to depend on PSCI to bring SMP in linux. With rockchip u-boot and Mainline U-Boot the psci in linux-next triggers the abort. (note that I have added rockchip_smcc and enabled PSCI in u-boot) [ 0.000000] Booting Linux on physical CPU 0xf00 [ 0.000000] Linux version 6.1.0-rc1-00029-gb09e57e6064a (j@j-ThinkPad-E14-Gen-2) (arm-linux-gnueabihf-gcc (GCC) 11.0.1 20210310 (experimental) [master revision 5987d8a79cda1069c774e5c302d5597310270026], GNU ld (Linaro_Binutils-2021.03) 2.36.50.20210310) #12 SMP Sat Oct 22 19:44:56 IST 2022 [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d [ 0.000000] CPU: div instructions available: patching division code [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] OF: fdt: Machine model: Edgeble Neu2 IO Board [ 0.000000] earlycon: uart8250 at MMIO32 0xff570000 (options '') [ 0.000000] printk: bootconsole [uart8250] enabled [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] efi: UEFI not found. [ 0.000000] cma: Reserved 64 MiB at 0x7c000000 [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000000000000-0x000000002fffffff] [ 0.000000] Normal empty [ 0.000000] HighMem [mem 0x0000000030000000-0x000000007fffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000000000000-0x000000007fffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000007fffffff] [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] Bad mode in prefetch abort handler detected [ 0.000000] Internal error: Oops - bad mode: 0 [#1] SMP ARM [ 0.000000] Modules linked in: [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 6.1.0-rc1-00029-gb09e57e6064a #12 [ 0.000000] Hardware name: Generic DT based system [ 0.000000] PC is at 0x133fd468 [ 0.000000] LR is at __invoke_psci_fn_smc+0x38/0x58 [ 0.000000] pc : [<133fd468>] lr : [<c0eb20f0>] psr: 600001d6 [ 0.000000] sp : c1e01e68 ip : c1e01ec0 fp : 80000200 [ 0.000000] r10: c1e01f58 r9 : 7fffffff r8 : c1e09410 [ 0.000000] r7 : 00000000 r6 : 00000000 r5 : 00000000 r4 : 00000000 [ 0.000000] r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : 84000000 [ 0.000000] Flags: nZCv IRQs off FIQs off Mode MON_32 ISA ARM Segment none [ 0.000000] Control: 10c5387d Table: 0020406a DAC: c1e09980 [ 0.000000] Register r0 information: non-paged memory [ 0.000000] Register r1 information: NULL pointer [ 0.000000] Register r2 information: NULL pointer [ 0.000000] Register r3 information: NULL pointer [ 0.000000] Register r4 information: NULL pointer [ 0.000000] Register r5 information: NULL pointer [ 0.000000] Register r6 information: NULL pointer [ 0.000000] Register r7 information: NULL pointer [ 0.000000] Register r8 information: non-slab/vmalloc memory [ 0.000000] Register r9 information: non-paged memory [ 0.000000] Register r10 information: non-slab/vmalloc memory [ 0.000000] Register r11 information: non-paged memory [ 0.000000] Register r12 information: non-slab/vmalloc memory [ 0.000000] Process swapper (pid: 0, stack limit = 0x(ptrval)) [ 0.000000] Stack: (0xc1e01e68 to 0xc1e02000) [ 0.000000] 1e60: 84000000 00000000 00000000 00000000 00000000 00000000 [ 0.000000] 1e80: 00000000 00000000 c1e09410 7fffffff c1e01f58 80000200 c1e01ec0 c1e01e68 [ 0.000000] 1ea0: c0eb20f0 133fd468 600001d6 ffffffff c1e09980 00000000 c20891c0 c1b1c168 [ 0.000000] 1ec0: 00000000 00000000 00000000 00000000 c1e01edc 00000000 c20891c0 c1245ac8 [ 0.000000] 1ee0: ff8005a8 00000000 c1d2fca0 00000000 eefea2fc c1c93594 eefea2fc c1e09980 [ 0.000000] 1f00: c20891c0 c1b1c168 c1e09410 c1c93a10 eefea2fc c1c939d8 c1d2fbdc 00000000 [ 0.000000] 1f20: 7fffffff c1caf854 c1e0afa0 c1c04c44 00000000 c1e01f4c c1e01f50 00000000 [ 0.000000] 1f40: c1e09980 c198cfec c1e01f9c 00000000 80000000 c1e09980 ffffffff ffffffff [ 0.000000] 1f60: c2089064 08300000 410fc075 10c5387d 00000000 c039de88 c1e01f9c 00000000 [ 0.000000] 1f80: c1e09980 c1c00420 c1e04ec0 c1e09980 c2089064 08300000 410fc075 10c5387d [ 0.000000] 1fa0: 00000000 c1c00b08 00000000 00000000 00000000 00000000 00000000 00000000 [ 0.000000] 1fc0: 00000000 c1cc8a6c 00000000 00000000 00000000 c1c00420 00000051 10c0387d [ 0.000000] 1fe0: 00000000 08300000 410fc075 10c5387d 00000000 00000000 00000000 00000000 [ 0.000000] __invoke_psci_fn_smc from 0xc1e01e68 [ 0.000000] Code: bad PC value Any comments? Thanks, Jagan.

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[PATCH v3 0/9] New boards support: db845c and qcs404-evb
by Sumit Garg 11 Sep '23

11 Sep '23

Add support for two new boards db845c and qcs404-evb: - db845c is a 96boards compliant platform aka RB3 based on Qualcomm SDM845 SoC. - qcs404-evb is an evaluation board from Qualcomm based on QCS404 SoC. Both these platforms have one thing in common that u-boot is chain-loaded in 64-bit mode via Android Boot Loader (ABL) which is an EFI application. For further details on chain-loading refer to platform specific documentation: - doc/board/qualcomm/sdm845.rst - doc/board/qualcomm/qcs404.rst Changes in v3: - Add clocks re-initialization for UART and eMMC for qcs404-evb. - Pick up Ramon's review tag for patches 1-7. Changes in v2: - Added patch #1 to fix DT node overrides in starqltechn-uboot.dtsi. - Updated patch #2 commit description. - Fixed a typo (s/96Board/96Boards/) in patch #5. Sumit Garg (9): board: starqltechn: Align DT node overrides with sdm845.dtsi arm64: dts: sdm845: Remove redundant u-boot DT properties clocks: sdm845: Import qcom,gcc-sdm845.h uart: sdm845: Fix debug UART pinmux board: qualcomm: Add support for dragonboard845c mmc: msm_sdhci: Add SDCC version 5.0.0 support pinctrl: qcom: Add pinctrl driver for QCS404 SoC clocks: qcom: Add clock driver for QCS404 SoC board: qualcomm: Add support for QCS404 EVB arch/arm/dts/Makefile | 1 + arch/arm/dts/dragonboard845c-uboot.dtsi | 37 +++ arch/arm/dts/dragonboard845c.dts | 44 ++++ arch/arm/dts/qcs404-evb-uboot.dtsi | 24 ++ arch/arm/dts/qcs404-evb.dts | 81 ++++++ arch/arm/dts/sdm845.dtsi | 8 +- arch/arm/dts/starqltechn-uboot.dtsi | 18 +- arch/arm/dts/starqltechn.dts | 2 +- arch/arm/mach-snapdragon/Kconfig | 25 ++ arch/arm/mach-snapdragon/Makefile | 3 + arch/arm/mach-snapdragon/clock-qcs404.c | 79 ++++++ arch/arm/mach-snapdragon/clock-sdm845.c | 3 +- arch/arm/mach-snapdragon/clock-snapdragon.c | 1 + .../include/mach/sysmap-qcs404.h | 40 +++ arch/arm/mach-snapdragon/pinctrl-qcs404.c | 55 ++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 + arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 + arch/arm/mach-snapdragon/sysmap-qcs404.c | 31 +++ board/qualcomm/dragonboard845c/Kconfig | 12 + board/qualcomm/dragonboard845c/MAINTAINERS | 6 + board/qualcomm/dragonboard845c/Makefile | 9 + board/qualcomm/dragonboard845c/db845c.its | 63 +++++ .../dragonboard845c/dragonboard845c.c | 9 + board/qualcomm/qcs404-evb/Kconfig | 15 ++ board/qualcomm/qcs404-evb/MAINTAINERS | 6 + board/qualcomm/qcs404-evb/Makefile | 6 + board/qualcomm/qcs404-evb/qcs404-evb.c | 33 +++ board/qualcomm/qcs404-evb/qcs404-evb.its | 64 +++++ configs/dragonboard845c_defconfig | 28 ++ configs/qcs404evb_defconfig | 39 +++ doc/board/qualcomm/index.rst | 1 + doc/board/qualcomm/qcs404.rst | 79 ++++++ doc/board/qualcomm/sdm845.rst | 100 ++++++- drivers/mmc/msm_sdhci.c | 96 ++++--- include/configs/dragonboard845c.h | 28 ++ include/configs/qcs404-evb.h | 27 ++ include/dt-bindings/clock/qcom,gcc-qcs404.h | 180 +++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 246 ++++++++++++++++++ 38 files changed, 1439 insertions(+), 62 deletions(-) create mode 100644 arch/arm/dts/dragonboard845c-uboot.dtsi create mode 100644 arch/arm/dts/dragonboard845c.dts create mode 100644 arch/arm/dts/qcs404-evb-uboot.dtsi create mode 100644 arch/arm/dts/qcs404-evb.dts create mode 100644 arch/arm/mach-snapdragon/clock-qcs404.c create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h create mode 100644 arch/arm/mach-snapdragon/pinctrl-qcs404.c create mode 100644 arch/arm/mach-snapdragon/sysmap-qcs404.c create mode 100644 board/qualcomm/dragonboard845c/Kconfig create mode 100644 board/qualcomm/dragonboard845c/MAINTAINERS create mode 100644 board/qualcomm/dragonboard845c/Makefile create mode 100644 board/qualcomm/dragonboard845c/db845c.its create mode 100644 board/qualcomm/dragonboard845c/dragonboard845c.c create mode 100644 board/qualcomm/qcs404-evb/Kconfig create mode 100644 board/qualcomm/qcs404-evb/MAINTAINERS create mode 100644 board/qualcomm/qcs404-evb/Makefile create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.c create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.its create mode 100644 configs/dragonboard845c_defconfig create mode 100644 configs/qcs404evb_defconfig create mode 100644 doc/board/qualcomm/qcs404.rst create mode 100644 include/configs/dragonboard845c.h create mode 100644 include/configs/qcs404-evb.h create mode 100644 include/dt-bindings/clock/qcom,gcc-qcs404.h create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm845.h -- 2.25.1

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