December 2023 - U-Boot

[PATCH 0/2] docs: AM62x: Remove SW_PRNG Flag for OPTEE
by Dhruva Gole 05 Dec '23

05 Dec '23

The CFG_WITH_SOFTWARE_PRNG option was needed once when there were some issues with system crashes/ hangs after a suspend-resume cycle. However this seems to no longer be the case with newer firmwares, and this config is not needed for basic boot support of the SoC either, hence remove it from the docs. Cc: Kamlesh <kamlesh(a)ti.com> Cc: Vibhore Vardhan <vibhore(a)ti.com> Cc: Wadim Egorov <w.egorov(a)phytec.de> Dhruva Gole (2): doc: board: beagle: am62x_beagleplay: Delete SW_PRNG flag for OPTEE doc: board: ti: am62x_sk: Remove SW_PRNG Flag for OPTEE doc/board/beagle/am62x_beagleplay.rst | 1 - doc/board/ti/am62x_sk.rst | 1 - 2 files changed, 2 deletions(-) -- 2.34.1

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[PATCH v2] riscv: Add support for AMD/Xilinx MicroBlaze V
by Michal Simek 05 Dec '23

05 Dec '23

MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. The patch contains initial wiring and configuration for initial HW design with memory, cpu, interrupt controller, timers and uartlite console (interrupt controller is listed but U-Boot is not using it). Provided DT is just describing one configuration and should be taken only as example. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- Changes in v2: - Extend commit message - DT changes, add interrupt controller, check agains dt schema - The patch for amd,mbv32 compatible string is here https://lore.kernel.org/r/d442d916204d26f82c1c3a924a4cdfb117960e1b.16992706… - The patch for board compatibility is here https://lore.kernel.org/r/50c277c92c41a582ef171fb75efc6a6a4f860be2.16992716… xlnx,xps-intc-1.00.a driver exists in the Linux kernel but DT binding is missing. That's something what we need to work on. arch/arm64/boot/dts/xilinx/xilinx-mbv32.dtb: /axi/interrupt-controller@41200000: failed to match any schema with compatible: ['xlnx,xps-intc-1.00.a'] Public annoucement is available here if someone is interested. https://www.xilinx.com/products/design-tools/microblaze-v.html?utm_source=m… --- arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 2 + arch/riscv/dts/xilinx-mbv32.dts | 106 +++++++++++++++++++++++++++ board/xilinx/Kconfig | 3 +- board/xilinx/common/board.c | 5 ++ board/xilinx/mbv/Kconfig | 28 +++++++ board/xilinx/mbv/MAINTAINERS | 7 ++ board/xilinx/mbv/Makefile | 5 ++ board/xilinx/mbv/board.c | 11 +++ configs/xilinx_mbv32_defconfig | 30 ++++++++ configs/xilinx_mbv32_smode_defconfig | 32 ++++++++ include/configs/xilinx_mbv.h | 6 ++ 12 files changed, 238 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/dts/xilinx-mbv32.dts create mode 100644 board/xilinx/mbv/Kconfig create mode 100644 board/xilinx/mbv/MAINTAINERS create mode 100644 board/xilinx/mbv/Makefile create mode 100644 board/xilinx/mbv/board.c create mode 100644 configs/xilinx_mbv32_defconfig create mode 100644 configs/xilinx_mbv32_smode_defconfig create mode 100644 include/configs/xilinx_mbv.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6d0d812ddb55..67126d96af89 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -39,6 +39,9 @@ config TARGET_TH1520_LPI4A bool "Support Sipeed's TH1520 Lichee PI 4A Board" select SYS_CACHE_SHIFT_6 +config TARGET_XILINX_MBV + bool "Support AMD/Xilinx MicroBlaze V" + endchoice config SYS_ICACHE_OFF @@ -82,6 +85,7 @@ source "board/sifive/unmatched/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" source "board/thead/th1520_lpi4a/Kconfig" +source "board/xilinx/mbv/Kconfig" # platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index be6c8a422729..b05bb5607f06 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,8 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb +dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb + include $(srctree)/scripts/Makefile.dts targets += $(dtb-y) diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts new file mode 100644 index 000000000000..6a6b8b694bd1 --- /dev/null +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for AMD MicroBlaze V + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek(a)amd.com> + */ + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "AMD MicroBlaze V 32bit"; + compatible = "amd,mbv"; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <102000000>; + cpu_0: cpu@0 { + compatible = "amd,mbv32", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa = "rv32imafdc"; + i-cache-size = <32768>; + d-cache-size = <32768>; + clock-frequency = <102000000>; + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x20000000>; + }; + + clk102: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <102000000>; + }; + + axi: axi { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + bootph-all; + + axi_intc: interrupt-controller@41200000 { + compatible = "xlnx,xps-intc-1.00.a"; + reg = <0x41200000 0x1000>; + interrupt-controller; + interrupt-parent = <&cpu0_intc>; + #interrupt-cells = <2>; + kind-of-intr = <0>; + }; + + xlnx_timer0: timer@41c00000 { + compatible = "xlnx,xps-timer-1.00.a"; + reg = <0x41c00000 0x1000>; + interrupt-parent = <&axi_intc>; + interrupts = <1 2>; + bootph-all; + xlnx,one-timer-only = <0>; + clock-names = "s_axi_aclk"; + clocks = <&clk102>; + }; + + xlnx_timer1: timer@41c20000 { + compatible = "xlnx,xps-timer-1.00.a"; + reg = <0x41c20000 0x1000>; + interrupt-parent = <&axi_intc>; + interrupts = <0 2>; + xlnx,one-timer-only = <0>; + clock-names = "s_axi_aclk"; + clocks = <&clk102>; + }; + + uart0: serial@40600000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x40600000 0x1000>; + interrupt-parent = <&axi_intc>; + interrupts = <2 2>; + bootph-all; + clocks = <&clk102>; + current-speed = <115200>; + xlnx,data-bits = <8>; + xlnx,use-parity = <0>; + }; + }; +}; diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 4f0776e8bd95..843198fa0da8 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -51,10 +51,11 @@ config XILINX_OF_BOARD_DTB_ADDR config BOOT_SCRIPT_OFFSET hex "Boot script offset" - depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE + depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE || TARGET_XILINX_MBV default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE default 0x3E80000 if ARCH_ZYNQMP default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET + default 0 if TARGET_XILINX_MBV help Specifies distro boot script offset in NAND/QSPI/NOR flash. diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 9309b071269f..12a877c71549 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -652,6 +652,11 @@ int embedded_dtb_select(void) #endif #if defined(CONFIG_LMB) + +#ifndef MMU_SECTION_SIZE +#define MMU_SECTION_SIZE (1 * 1024 * 1024) +#endif + phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { phys_size_t size; diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig new file mode 100644 index 000000000000..4bc9f72c541b --- /dev/null +++ b/board/xilinx/mbv/Kconfig @@ -0,0 +1,28 @@ +if TARGET_XILINX_MBV + +config SYS_BOARD + default "mbv" + +config SYS_VENDOR + default "xilinx" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "xilinx_mbv" + +config TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80400000 if RISCV_SMODE && ARCH_RV32I + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select GENERIC_RISCV + imply BOARD_LATE_INIT + imply CMD_SBI + imply CMD_PING + +source "board/xilinx/Kconfig" + +endif diff --git a/board/xilinx/mbv/MAINTAINERS b/board/xilinx/mbv/MAINTAINERS new file mode 100644 index 000000000000..445654fe740e --- /dev/null +++ b/board/xilinx/mbv/MAINTAINERS @@ -0,0 +1,7 @@ +XILINX MicroBlaze V BOARD +M: Michal Simek <michal.simek(a)amd.com> +S: Maintained +F: arch/riscv/dts/xilinx-mbv* +F: board/xilinx/mbv/ +F: configs/xilinx_mbv* +F: include/configs/xilinx_mbv.h diff --git a/board/xilinx/mbv/Makefile b/board/xilinx/mbv/Makefile new file mode 100644 index 000000000000..e2fc0c69715f --- /dev/null +++ b/board/xilinx/mbv/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# (C) Copyright 2023, Advanced Micro Devices, Inc. + +obj-y += board.o diff --git a/board/xilinx/mbv/board.c b/board/xilinx/mbv/board.c new file mode 100644 index 000000000000..ccf4395d6ace --- /dev/null +++ b/board/xilinx/mbv/board.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek(a)amd.com> + */ + +int board_init(void) +{ + return 0; +} diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig new file mode 100644 index 000000000000..2689495057b0 --- /dev/null +++ b/configs/xilinx_mbv32_defconfig @@ -0,0 +1,30 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x21200000 +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" +CONFIG_DEBUG_UART_BASE=0x40600000 +CONFIG_DEBUG_UART_CLOCK=1000000 +CONFIG_SYS_CLK_FREQ=100000000 +CONFIG_BOOT_SCRIPT_OFFSET=0x0 +CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_DEBUG_UART=y +CONFIG_TARGET_XILINX_MBV=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMD_MII is not set +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_MTD=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_XILINX_UARTLITE=y +CONFIG_XILINX_TIMER=y +CONFIG_PANIC_HANG=y diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig new file mode 100644 index 000000000000..c724d1bad742 --- /dev/null +++ b/configs/xilinx_mbv32_smode_defconfig @@ -0,0 +1,32 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x21200000 +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" +CONFIG_DEBUG_UART_BASE=0x40600000 +CONFIG_DEBUG_UART_CLOCK=1000000 +CONFIG_SYS_CLK_FREQ=100000000 +CONFIG_BOOT_SCRIPT_OFFSET=0x0 +CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_TARGET_XILINX_MBV=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMD_MII is not set +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_MTD=y +CONFIG_DEBUG_UART_UARTLITE=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_XILINX_UARTLITE=y +# CONFIG_RISCV_TIMER is not set +CONFIG_XILINX_TIMER=y +CONFIG_PANIC_HANG=y diff --git a/include/configs/xilinx_mbv.h b/include/configs/xilinx_mbv.h new file mode 100644 index 000000000000..dba398aeec49 --- /dev/null +++ b/include/configs/xilinx_mbv.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek(a)amd.com> + */ -- 2.36.1

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[PATCH v4 0/8] Move framebuffer reservation for SPL to RAM end
by Devarsh Thakkar 05 Dec '23

05 Dec '23

Move video memory reservation for SPL at end of RAM so that it does not interefere with reservations for next stage so that the next stage need not have holes in between for passed regions and instead it can maintain continuity in reservations. Also catch the bloblist before starting reservations to avoid the same problem. While at it, also fill missing fields in video handoff struct before passing it to next stage. This is as per discussions at : For moving SPL framebuffer reservation at end of RAM: https://lore.kernel.org/all/CAPnjgZ3xSoe_G3yrqwuAvoiVjUfZ+YQgkOR0ZTVXGT9VK8… For filling missing video handoff fields : https://lore.kernel.org/all/CAPnjgZ1Hs0rNf0JDirp6YPsOQ5=QqQSP9g9qRwLoOASUV8… Changelog: V2: - Make a generic function to reserve video memory at SPL stage. - Add debug prints while skipping framebuffer allocation at uboot. - Correct commenting style as suggested. V3: - Change spl_reserve_video to spl_reserve_video_from_ram_top which enforce framebuffer reservation from end of RAM. - Use gd->ram_top instead of local ram_top and update gd->reloc_addr after each reservation. - Print error message on framebuffer reservation. - Update SPL doc with spl splash screen specific info. V4: - Split patches into atomic commits. - Remove duplicate check for video blob passed addresses and error out if invalid address/size received from blob. - Improve SPL documentation memory reservation scheme and print message for video memory reservation from bloblist. - Add Reviewed-By. Test logs: https://gist.github.com/devarsht/6a748b1d69bd2a4b60695a5e7776db73 Devarsh Thakkar (8): spl: Enforce framebuffer reservation from end of RAM arm: mach-k3: common: Reserve video memory from end of the RAM board: ti: am62x: evm: Remove video_setup from spl_board_init common/board_f: Catch bloblist before starting resevations video: Skip framebuffer reservation if already reserved video: Fill video handoff in video post probe doc: spl: Add info for missing Kconfigs doc: spl: Add info regarding memory reservation arch/arm/mach-k3/common.c | 17 ++++++++++----- board/ti/am62x/evm.c | 18 ---------------- common/board_f.c | 41 +++++++++++++++++++++++++++++++----- common/spl/spl.c | 19 +++++++++++++++++ doc/develop/spl.rst | 37 ++++++++++++++++++++++++++++++++ drivers/video/video-uclass.c | 39 +++++++++++++++++++++++----------- include/spl.h | 10 +++++++++ 7 files changed, 141 insertions(+), 40 deletions(-) -- 2.34.1

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[PATCH v2 0/6] Move framebuffer reservation for SPL to RAM end
by Devarsh Thakkar 05 Dec '23

05 Dec '23

Move video memory reservation for SPL at end of RAM so that it does not interefere with reservations for next stage so that the next stage need not have holes in between for passed regions and instead it can maintain continuity in reservations. Also catch the bloblist before starting reservations to avoid the same problem. While at it, also fill missing fields in video handoff struct before passing it to next stage. This is as per discussions at : For moving SPL framebuffer reservation at end of RAM: https://lore.kernel.org/all/CAPnjgZ3xSoe_G3yrqwuAvoiVjUfZ+YQgkOR0ZTVXGT9VK8… For filling missing video handoff fields : https://lore.kernel.org/all/CAPnjgZ1Hs0rNf0JDirp6YPsOQ5=QqQSP9g9qRwLoOASUV8… Changelog: V2: - Make a generic function to reserve video memory at SPL stage - Add debug prints while skipping framebuffer allocation at uboot - Correct commenting style as suggested V3: - Change spl_reserve_video to spl_reserve_video_from_ram_top which enforce framebuffer reservation from end of RAM - Use gd->ram_top instead of local ram_top and update gd->reloc_addr after each reservation - Print error message on framebuffer reservation - Update SPL doc with spl splash screen specific info Test logs (at tip of U-Boot 2024.01-rc1 + these patches): https://gist.github.com/devarsht/6a748b1d69bd2a4b60695a5e7776db73 Devarsh Thakkar (6): arm: mach-k3: common: Reserve video memory from end of the RAM board: ti: am62x: evm: Remove video_setup from spl_board_init common/board_f: Catch bloblist before starting resevations video: Skip framebuffer reservation if already reserved video: Fill video handoff in video post probe doc: spl: Add info regarding memory reservation and missing Kconfigs arch/arm/mach-k3/common.c | 17 ++++++++++----- board/ti/am62x/evm.c | 18 ---------------- common/board_f.c | 33 +++++++++++++++++++++++++--- common/spl/spl.c | 27 +++++++++++++++++++++++ doc/develop/spl.rst | 22 +++++++++++++++++++ drivers/video/video-uclass.c | 42 +++++++++++++++++++++++++++--------- include/spl.h | 6 ++++++ 7 files changed, 129 insertions(+), 36 deletions(-) -- 2.34.1

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[PATCH] rockchip: rk3328: Set efuse auto mode and timing control
by Jonas Karlman 05 Dec '23

05 Dec '23

Reading from efuse return zero when mainline TF-A is used. => dump_efuse 00000000: 00 00 00 00 .... 00000004: 00 00 00 00 .... 00000008: 00 00 00 00 .... 0000000c: 00 00 00 00 .... 00000010: 00 00 00 00 .... 00000014: 00 00 00 00 .... 00000018: 00 00 00 00 .... 0000001c: 00 00 00 00 .... However, when vendor TF-A blobs is used reading from efuse works. Change to use auto mode, enable finish and auto access err interrupts and set timing control using same values that vendor TF-A blob use to fix this. With this efuse can be read when either of mainline TF-A or vendor blob is used. => dump_efuse 00000000: 52 4b 33 82 RK3. 00000004: 00 fe 21 55 ..!U 00000008: 52 4b 57 34 RKW4 0000000c: 35 30 32 39 5029 00000010: 00 00 00 00 .... 00000014: 08 25 0c 0f .%.. 00000018: 02 0d 08 00 .... 0000001c: 00 00 f0 00 .... Signed-off-by: Jonas Karlman <jonas(a)kwiboo.se> --- arch/arm/mach-rockchip/rk3328/rk3328.c | 34 ++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index de17b8868273..edb22a58fc67 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -19,6 +19,22 @@ DECLARE_GLOBAL_DATA_PTR; #define GRF_BASE 0xFF100000 #define UART2_BASE 0xFF130000 #define FW_DDR_CON_REG 0xFF7C0040 +#define EFUSE_NS_BASE 0xFF260000 + +#define EFUSE_MOD 0x0000 +#define EFUSE_INT_CON 0x0014 +#define EFUSE_T_CSB_P 0x0028 +#define EFUSE_T_PGENB_P 0x002C +#define EFUSE_T_LOAD_P 0x0030 +#define EFUSE_T_ADDR_P 0x0034 +#define EFUSE_T_STROBE_P 0x0038 +#define EFUSE_T_CSB_R 0x003C +#define EFUSE_T_PGENB_R 0x0040 +#define EFUSE_T_LOAD_R 0x0044 +#define EFUSE_T_ADDR_R 0x0048 +#define EFUSE_T_STROBE_R 0x004C + +#define EFUSE_TIMING(s, l) (((s) << 16) | (l)) const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000", @@ -54,6 +70,24 @@ int arch_cpu_init(void) /* Disable the ddr secure region setting to make it non-secure */ rk_setreg(FW_DDR_CON_REG, 0x200); + + /* Use efuse auto mode */ + writel(0x46, EFUSE_NS_BASE + EFUSE_MOD); + + /* Enable efuse finish and auto access err interrupt */ + writel(0x07, EFUSE_NS_BASE + EFUSE_INT_CON); + + /* Set efuse timing control */ + writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_CSB_P); + writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_PGENB_P); + writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_LOAD_P); + writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_ADDR_P); + writel(EFUSE_TIMING(2, 240), EFUSE_NS_BASE + EFUSE_T_STROBE_P); + writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_CSB_R); + writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_PGENB_R); + writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_LOAD_R); + writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_ADDR_R); + writel(EFUSE_TIMING(2, 3), EFUSE_NS_BASE + EFUSE_T_STROBE_R); #endif return 0; } -- 2.42.0

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[PATCH v5 00/17] Introduce initial TI's J784S4 and AM69 support
by Apurva Nandan 05 Dec '23

05 Dec '23

Hello Everyone! This series will introduce basic support (SD and UART) support for Texas Instruments J784S4 EVM. The J784S4 SoC device tree patches are taken from kernel patch submissions and will be updated as they are accepted and merged to the kernel tree. All other patches are specific to SPL and u-boot and do not have dependency on other trees. Appreciate a review for acceptance to u-boot tree. Here are some of the salient features of the J784S4 automotive grade application processor: The J784S4 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive, ADAS and industrial applications requiring AI at the network edge. This SoC extends the K3 Jacinto 7 family of SoCs with focus on raising performance and integration while providing interfaces, memory architecture and compute performance for multi-sensor, high concurrency applications. Some highlights of this SoC are: * Up to 8 Cortex-A72s, four clusters of lockstep capable dual Cortex-R5F MCUs, 4 C7x floating point vector DSPs with Matrix Multiply Accelerator(MMA) for deep learning and CNN. * 3D GPU: Automotive grade IMG BXS-4-64 MC1 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Three CSI2.0 4L RX plus two CSI2.0 4L TX, two DSI Tx, one eDP/DP and one DPI interface. * Integrated gigabit ethernet switch, up to 8 ports (TDA4VH), two ports support 10Gb USXGMII; Two 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, Up to 20 MCANs, among other peripherals. See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022) for further details: http://www.ti.com/lit/zip/spruj52 In addtion, the J784S4 EVM board is designed for TI J784S4 SoC. It supports the following interfaces: * 32 GB DDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode * x1 Input Audio Jack, x1 Output Audio Jack * x1 USB2.0 Hub with two Type A host and x1 USB 3.1 Type-C Port * x2 4L PCIe connector * x1 UHS-1 capable micro-SD card slot * 512 Mbit OSPI flash, 1 Gbit Octal NAND flash, 512 Mbit QSPI flash, UFS flash. * x6 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin User Expansion Connector * x2 ENET Expansion Connector, x1 GESI expander, x2 Display connector * x1 15-pin CSI header * x6 MCAN instances Schematics: https://www.ti.com/lit/zip/sprr458 bootlog: https://gist.githubusercontent.com/apurvanandan1997/2116d3eb4f2e8d50d5601c5… Changes in v5: 1) Incorporated Andrew Davis' "Move R5 specific code into new r5/ directory" and "Move board selection to mach-k3" series changes. 2) Incorporated Neha Francis' "Move to using templated FITs" series changes. 3) Synced device tree files with Linux v6.7-rc1 4) Changed ti_mmc to mmc1 target from bootstd 5) Updated doc based on review comments 6) Removed remoteproc support from the series 7) Splitted board files patch into smaller patches 8) Trimmed j784s4.env to necessary variables 9) Used fdtdec_setup_mem_size_base fdtdec_setup_memory_banksize in evm.c 10) Trimmed down evm.c to essential header files. 11) Switched to multi-dtb fit compilation with config fragments Link to v4: https://lore.kernel.org/u-boot/20231001165545.494212-1-a-nandan@ti.com/ Changes in v4: 1) Cleaned up Copyright and SPDX identifiers 2) Synced the device trees to Linux v6.6-rc1 tag 3) Added cleanup patch for sorting SoC JTAG ID entries 4) Removed EEPROM board detect from evm.c and added am69 config fragments 5) Updated MAINTAINERS files and commit messages 6) Removed struct renaming in ti_k3_r5f_rproc driver Link to v3: https://lore.kernel.org/u-boot/20230908110551.861575-1-a-nandan@ti.com/ Changes in v3: 1) Added AM69 SK support in the series 2) Switched from distroboot to bootstd support 3) Added remoteproc support for J784S4 4) Added documentation for both SoCs 5) Added binman support 6) Removed unnecessarry nodes from r5-evm.dts and evm-u-boot.dtsi 7) Added HS device support 8) Added env file for environement variables 9) Removed ti-serdes-mux bindings 10) Cleaned up all files and synced with latest 11) Addressed all previous review comments Note: The base dts files have been sync from next-20230905 linux tag as per review comment received on previous re-roll: https://lore.kernel.org/u-boot/20230321155227.GV8135@bill-the-cat/ Link to v2: https://lore.kernel.org/u-boot/20230321141028.24456-1-hnagalla@ti.com/ Changes in v2: - Refactored environement scripts to 'j784s4.env' and removed scripts not needed for basic board bootup. - Imported the J7874S4 basic device tree files from v6.2 linux kernel. - Moved j784s4 clock definitions and clock data into one patch/commit. - coalesce board commits into one commit. Apurva Nandan (14): arm: dts: Introduce j784s4 dts from linux kernel arm: dts: Add bootph-all for memory node arm: mach-k3: Add basic support for J784S4 SoC definition arm: mach-k3: Sort SoC JTAG_ID entries soc: ti: k3-socinfo: Add entry for J784S4 SoC arm: mach-k3: j784s4: Add clk and power support drivers: dma: Add support for J784S4 SoC board: ti: j784s4: Add board support for J784S4 EVM board: ti: j748s4: Add board config yaml files board: ti: j784s4: Add boot environment variables arm: dts: Introduce j784s4 u-boot dts files configs: j784s4_evm: Add defconfig for j784s4 evm board doc: board: ti: k3: Add J784S4 EVM and AM69 SK documentation board: ti: j784s4: Add MAINTAINERS file Dasnavis Sabiya (3): arm: dts: Introduce am69-sk dts from linux kernel arm: dts: Introduce am69-sk u-boot dts files configs: Add am69_sk_* defconfig fragments arch/arm/dts/Makefile | 4 + arch/arm/dts/k3-am69-r5-sk.dts | 105 + arch/arm/dts/k3-am69-sk-u-boot.dtsi | 25 + arch/arm/dts/k3-am69-sk.dts | 901 ++ arch/arm/dts/k3-j784s4-binman.dtsi | 435 + arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi | 8757 ++++++++++++++++ arch/arm/dts/k3-j784s4-ddr.dtsi | 8858 +++++++++++++++++ arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 25 + arch/arm/dts/k3-j784s4-evm.dts | 982 ++ arch/arm/dts/k3-j784s4-main.dtsi | 2068 ++++ arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi | 743 ++ arch/arm/dts/k3-j784s4-r5-evm.dts | 105 + arch/arm/dts/k3-j784s4-thermal.dtsi | 101 + arch/arm/dts/k3-j784s4.dtsi | 294 + arch/arm/mach-k3/Kconfig | 17 +- arch/arm/mach-k3/Makefile | 2 + arch/arm/mach-k3/arm64-mmu.c | 52 + arch/arm/mach-k3/include/mach/hardware.h | 13 +- .../mach-k3/include/mach/j784s4_hardware.h | 60 + arch/arm/mach-k3/include/mach/j784s4_spl.h | 47 + arch/arm/mach-k3/include/mach/spl.h | 4 + arch/arm/mach-k3/j784s4/Kconfig | 35 + arch/arm/mach-k3/j784s4_fdt.c | 15 + arch/arm/mach-k3/j784s4_init.c | 338 + arch/arm/mach-k3/r5/Makefile | 1 + arch/arm/mach-k3/r5/j784s4/Makefile | 7 + arch/arm/mach-k3/r5/j784s4/clk-data.c | 428 + arch/arm/mach-k3/r5/j784s4/dev-data.c | 98 + board/ti/j784s4/MAINTAINERS | 25 + board/ti/j784s4/Makefile | 7 + board/ti/j784s4/board-cfg.yaml | 37 + board/ti/j784s4/evm.c | 38 + board/ti/j784s4/j784s4.env | 19 + board/ti/j784s4/pm-cfg.yaml | 13 + board/ti/j784s4/rm-cfg.yaml | 3058 ++++++ board/ti/j784s4/sec-cfg.yaml | 380 + board/ti/j784s4/tifs-rm-cfg.yaml | 2656 +++++ configs/am69_sk_a72.config | 3 + configs/am69_sk_r5.config | 3 + configs/j784s4_evm_a72_defconfig | 180 + configs/j784s4_evm_r5_defconfig | 163 + doc/board/ti/j784s4_evm.rst | 303 + doc/board/ti/k3.rst | 1 + drivers/clk/ti/clk-k3.c | 6 + drivers/dma/ti/Makefile | 1 + drivers/dma/ti/k3-psil-j784s4.c | 166 + drivers/dma/ti/k3-psil-priv.h | 1 + drivers/dma/ti/k3-psil.c | 2 + drivers/firmware/ti_sci_static_data.h | 34 + drivers/power/domain/ti-power-domain.c | 6 + drivers/ram/Kconfig | 2 +- drivers/soc/soc_ti_k3.c | 3 + include/configs/j784s4_evm.h | 20 + include/k3-clk.h | 1 + include/k3-dev.h | 1 + 55 files changed, 31637 insertions(+), 12 deletions(-) create mode 100644 arch/arm/dts/k3-am69-r5-sk.dts create mode 100644 arch/arm/dts/k3-am69-sk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am69-sk.dts create mode 100644 arch/arm/dts/k3-j784s4-binman.dtsi create mode 100644 arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi create mode 100644 arch/arm/dts/k3-j784s4-ddr.dtsi create mode 100644 arch/arm/dts/k3-j784s4-evm-u-boot.dtsi create mode 100644 arch/arm/dts/k3-j784s4-evm.dts create mode 100644 arch/arm/dts/k3-j784s4-main.dtsi create mode 100644 arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi create mode 100644 arch/arm/dts/k3-j784s4-r5-evm.dts create mode 100644 arch/arm/dts/k3-j784s4-thermal.dtsi create mode 100644 arch/arm/dts/k3-j784s4.dtsi create mode 100644 arch/arm/mach-k3/include/mach/j784s4_hardware.h create mode 100644 arch/arm/mach-k3/include/mach/j784s4_spl.h create mode 100644 arch/arm/mach-k3/j784s4/Kconfig create mode 100644 arch/arm/mach-k3/j784s4_fdt.c create mode 100644 arch/arm/mach-k3/j784s4_init.c create mode 100644 arch/arm/mach-k3/r5/j784s4/Makefile create mode 100644 arch/arm/mach-k3/r5/j784s4/clk-data.c create mode 100644 arch/arm/mach-k3/r5/j784s4/dev-data.c create mode 100644 board/ti/j784s4/MAINTAINERS create mode 100644 board/ti/j784s4/Makefile create mode 100644 board/ti/j784s4/board-cfg.yaml create mode 100644 board/ti/j784s4/evm.c create mode 100644 board/ti/j784s4/j784s4.env create mode 100644 board/ti/j784s4/pm-cfg.yaml create mode 100644 board/ti/j784s4/rm-cfg.yaml create mode 100644 board/ti/j784s4/sec-cfg.yaml create mode 100644 board/ti/j784s4/tifs-rm-cfg.yaml create mode 100644 configs/am69_sk_a72.config create mode 100644 configs/am69_sk_r5.config create mode 100644 configs/j784s4_evm_a72_defconfig create mode 100644 configs/j784s4_evm_r5_defconfig create mode 100644 doc/board/ti/j784s4_evm.rst create mode 100644 drivers/dma/ti/k3-psil-j784s4.c create mode 100644 include/configs/j784s4_evm.h -- 2.34.1

7 28

[PATCH v2] timer: starfive: Add Starfive timer support
by Kuan Lim Lee 05 Dec '23

05 Dec '23

Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee(a)starfivetech.com> Signed-off-by: Wei Liang Lim <weiliang.lim(a)starfivetech.com> Changes for v2: - correct driver name, comment, variable --- drivers/timer/Kconfig | 7 +++ drivers/timer/Makefile | 1 + drivers/timer/starfive-timer.c | 96 ++++++++++++++++++++++++++++++++++ 3 files changed, 104 insertions(+) create mode 100644 drivers/timer/starfive-timer.c diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 915b2af160..a98be9dfae 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -326,4 +326,11 @@ config XILINX_TIMER Select this to enable support for the timer found on any Xilinx boards (axi timer). +config STARFIVE_TIMER + bool "Starfive timer support" + depends on TIMER + help + Select this to enable support for the timer found on + Starfive SoC. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 1ca74805fd..1ef814970b 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -34,3 +34,4 @@ obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o +obj-$(CONFIG_STARFIVE_TIMER) += starfive-timer.o diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c new file mode 100644 index 0000000000..b9ba33277e --- /dev/null +++ b/drivers/timer/starfive-timer.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 StarFive, Inc. All rights reserved. + * Author: Kuan Lim Lee <kuanlim.lee(a)starfivetech.com> + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <time.h> +#include <timer.h> +#include <asm/io.h> +#include <dm/device-internal.h> +#include <linux/err.h> + +#define STF_TIMER_INT_STATUS 0x00 +#define STF_TIMER_CTL 0x04 +#define STF_TIMER_LOAD 0x08 +#define STF_TIMER_ENABLE 0x10 +#define STF_TIMER_RELOAD 0x14 +#define STF_TIMER_VALUE 0x18 +#define STF_TIMER_INT_CLR 0x20 +#define STF_TIMER_INT_MASK 0x24 + +struct starfive_timer_priv { + void __iomem *base; + u32 timer_size; +}; + +static u64 notrace starfive_get_count(struct udevice *dev) +{ + struct starfive_timer_priv *priv = dev_get_priv(dev); + + /* Read decrement timer value and convert to increment value */ + return priv->timer_size - readl(priv->base + STF_TIMER_VALUE); +} + +static const struct timer_ops starfive_ops = { + .get_count = starfive_get_count, +}; + +static int starfive_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct starfive_timer_priv *priv = dev_get_priv(dev); + int timer_channel; + struct clk clk; + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + timer_channel = dev_read_u32_default(dev, "channel", 0); + priv->base = priv->base + (0x40 * timer_channel); + + /* Get clock rate from channel selectecd*/ + ret = clk_get_by_index(dev, timer_channel, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + uc_priv->clock_rate = clk_get_rate(&clk); + + /* + * Initiate timer, channel 0 + * Unmask Interrupt Mask + */ + writel(0, priv->base + STF_TIMER_INT_MASK); + /* Single run mode Setting */ + if (dev_read_bool(dev, "single-run")) + writel(1, priv->base + STF_TIMER_CTL); + /* Set Reload value */ + priv->timer_size = dev_read_u32_default(dev, "timer-size", -1U); + writel(priv->timer_size, priv->base + STF_TIMER_LOAD); + /* Enable to start timer */ + writel(1, priv->base + STF_TIMER_ENABLE); + + return 0; +} + +static const struct udevice_id starfive_ids[] = { + { .compatible = "starfive,jh8100-timers" }, + { } +}; + +U_BOOT_DRIVER(jh8100_starfive_timer) = { + .name = "starfive_timer", + .id = UCLASS_TIMER, + .of_match = starfive_ids, + .probe = starfive_probe, + .ops = &starfive_ops, + .priv_auto = sizeof(struct starfive_timer_priv), +}; -- 2.34.1

2 1

[PATCH 0/3] binman: Add support for TI_DM entry
by Neha Malcom Francis 05 Dec '23

05 Dec '23

This series adds support for the TI_DM entry and moves all K3 platforms to using the same. With this feature introduced, if TI_DM argument is provided binman picks the pathname it provides; else, it defaults to picking up the ti-dm.bin file. This makes it flexible for users to build tispl.bin with custom DM binaries. Boot logs: https://gist.github.com/nehamalcom/37ce8a32e37ddf3e1afcc4c8bd941159 Neha Malcom Francis (3): binman: etype: dm: Add entry type for TI DM arm: dts: k3-*-binman: Move to using ti-dm entry type doc: board: ti: k3: Mention TI_DM argument Makefile | 1 + arch/arm/dts/k3-am625-sk-binman.dtsi | 4 ++-- .../dts/k3-am625-verdin-wifi-dev-binman.dtsi | 4 ++-- arch/arm/dts/k3-am62a-sk-binman.dtsi | 4 ++-- arch/arm/dts/k3-j7200-binman.dtsi | 4 ++-- arch/arm/dts/k3-j721e-binman.dtsi | 4 ++-- arch/arm/dts/k3-j721s2-binman.dtsi | 4 ++-- doc/board/ti/k3.rst | 7 ++++++ tools/binman/entries.rst | 14 ++++++++++++ tools/binman/etype/ti_dm.py | 22 +++++++++++++++++++ tools/binman/ftest.py | 7 ++++++ tools/binman/test/225_ti_dm.dts | 13 +++++++++++ 12 files changed, 76 insertions(+), 12 deletions(-) create mode 100644 tools/binman/etype/ti_dm.py create mode 100644 tools/binman/test/225_ti_dm.dts -- 2.34.1

2 5

[PATCH] sunxi: dts: arm64: update emac for Orange Pi Zero 3
by Andre Przywara 05 Dec '23

05 Dec '23

From: Chukun Pan <amadeus(a)jmu.edu.cn> The current emac setting is not suitable for Orange Pi Zero 3, move it back to Orange Pi Zero 2 DT. Also update phy mode and delay values for emac on Orange Pi Zero 3. With these changes, Ethernet now looks stable. Fixes: 95c3b0635ea4 ("sunxi: dts: arm64: update devicetree files from Linux-v6.6-rc6") Signed-off-by: Chukun Pan <amadeus(a)jmu.edu.cn> Reviewed-by: Jernej Skrabec <jernej.skrabec(a)gmail.com> --- Hi, this is a port of the corresponding Linux patch, that fixes Ethernet on that board. The patch is in Linux' sunxi/fixes-for-6.7 queue, awaiting a merge anytime soon. For me this indeed fixes Ethernet operation in U-Boot on that board. Cheers, Andre arch/arm/dts/sun50i-h616-orangepi-zero.dtsi | 3 --- arch/arm/dts/sun50i-h616-orangepi-zero2.dts | 3 +++ arch/arm/dts/sun50i-h618-orangepi-zero3.dts | 2 ++ 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi index 15290e6892f..fc7315b9440 100644 --- a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi +++ b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi @@ -68,10 +68,7 @@ &emac0 { pinctrl-names = "default"; pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; phy-handle = <&ext_rgmii_phy>; - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts index d83852e72f0..b5d713926a3 100644 --- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts @@ -13,6 +13,9 @@ }; &emac0 { + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + phy-mode = "rgmii"; phy-supply = <&reg_dcdce>; }; diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts index 00fe28caac9..b3b1b869212 100644 --- a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts +++ b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts @@ -13,6 +13,8 @@ }; &emac0 { + allwinner,tx-delay-ps = <700>; + phy-mode = "rgmii-rxid"; phy-supply = <&reg_dldo1>; }; -- 2.35.8

1 0

EFI memory allocation
by Simon Glass 05 Dec '23

05 Dec '23

Hi Heinrich, Ilias, I had a bit of a look at how memory is allocated in EFI. I see that efi_memory_init() is called quite early in U-Boot. It sometimes allocates memory for a bounce buffer, placing it somewhere in memory. How do we know that that memory is free and not being used by U-Boot? To answer my own question, it excludes U-Boot's malloc() region from the map, so that it cannot overwrite that. But then, what if we use lmb and start loading images into memory. Won't that conflict with EFI? I also see that efi_allocate_pages() is called to allocate memory in the EFI code. But this just grabs memory from 'anywhere'...it doesn't respect the U-Boot malloc region. It seems to me that most of the memory allocation in EFI should be done using malloc(). Of course the boot services need to efi_allocate_pages(), etc., but I am not sure that the internal tables should be skipping malloc()? What do you think? Regards, Simon

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