December 2023 - U-Boot

[PATCH 09/30] mtd: spi-nor-ids: Add support for W25Q02NW
by Tejas Bhumkar 06 Dec '23

06 Dec '23

From: Algapally Santosh Sagar <santoshsagar.algapally(a)amd.com> Add support for Winbond 256MB flash W25Q02NW which supports 4byte opcodes and also dual and quad read. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally(a)amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)amd.com> Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> --- drivers/mtd/spi/spi-nor-ids.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index cb39c99fa8..7876874f97 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -519,6 +519,12 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q02nw", 0xef8022, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4B_OPCODES | + SPI_NOR_MULTI_DIE) + }, { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -- 2.27.0

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[PATCH 08/30] mtd: spi-nor: Update block protection flags for flash parts
by Tejas Bhumkar 06 Dec '23

06 Dec '23

From: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> The block protection flags for Gigadevice, Spansion, and ISSI flash memory have been modified. Additionally, new flags for SPI_NOR_OCTAL_DTR_READ and octal DTR page programming have been introduced for Micron OSPI flashes. Furthermore, the flashes mt35xu01g and mt35xu02g have been incorporated into the CONFIG_SPI_FLASH_MT35XU configuration, so that in driver mt35xu512aba_fixups will be applied. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> --- drivers/mtd/spi/spi-nor-ids.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3cb132dcff..cb39c99fa8 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -122,9 +122,9 @@ const struct flash_info spi_nor_ids[] = { {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) }, {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K | - SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB)}, {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K | - SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB)}, {INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128, SECT_4K | @@ -191,7 +191,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) + SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, /* adding these 1.8V OSPI flash parts */ {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K | @@ -212,11 +213,11 @@ const struct flash_info spi_nor_ids[] = { { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_HAS_TB) }, { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, @@ -233,7 +234,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, - SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | + SPI_NOR_HAS_TB) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ @@ -312,11 +314,15 @@ const struct flash_info spi_nor_ids[] = { { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, #ifdef CONFIG_SPI_FLASH_MT35XU - { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, - { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, + { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, + USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) }, + { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, + USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) }, + { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, + USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) }, + { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, + USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) }, #endif /* CONFIG_SPI_FLASH_MT35XU */ - { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, - { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ /* Spansion/Cypress -- single (large) sector size only, at least @@ -325,8 +331,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, - { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, - { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR | SPI_NOR_HAS_TB) }, + { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR | SPI_NOR_HAS_TB) }, { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, @@ -334,7 +340,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, - { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR | SPI_NOR_HAS_TB) }, { INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) }, -- 2.27.0

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[PATCH 07/30] spi: mtd: Use split reads if multi-die flag is set
by Tejas Bhumkar 06 Dec '23

06 Dec '23

From: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Some flash devices have multiple dies in it & has die cross over issue. When SPI_NOR_MULTI_DIE flag is set in flash id table use it to enable split reads to avoid above issue. Define SPI_NOR_MULTI_DIE new flag to flash id flags. Remove SPI_FLASH_SPLIT_READ config and related code from the zynq and zynqmp qspi drivers as it is redundant. Signed-off-by: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> --- drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/spi-nor-core.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 9c09f97ce2..2cbdea60b0 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -70,6 +70,7 @@ struct flash_info { #define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */ #define SPI_NOR_OCTAL_DTR_READ BIT(17) /* Flash supports Octal DTR Read */ #define SPI_NOR_OCTAL_DTR_PP BIT(18) /* Flash supports Octal DTR page program */ +#define SPI_NOR_MULTI_DIE BIT(19) /* Flash has multi dies & need split reads*/ }; extern const struct flash_info spi_nor_ids[]; diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 63f78baaf4..ace5da9591 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -4485,6 +4485,9 @@ int spi_nor_scan(struct spi_nor *nor) if (info->flags & SPI_NOR_NO_ERASE) mtd->flags |= MTD_NO_ERASE; + if (info->flags & SPI_NOR_MULTI_DIE) + nor->spi->multi_die = true; + nor->page_size = params.page_size; mtd->writebufsize = nor->page_size; -- 2.27.0

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[PATCH 06/30] mtd: spi-nor: Enable DTR octal flash program
by Tejas Bhumkar 06 Dec '23

06 Dec '23

From: Ashok Reddy Soma <ashok.reddy.soma(a)amd.com> Define a flag SPI_NOR_OCTAL_DTR_PP and if enabled in spi-nor-ids table, enable octal DTR page program in the framework. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)amd.com> Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> --- drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/spi-nor-core.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index d3ef69ec74..9c09f97ce2 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -69,6 +69,7 @@ struct flash_info { #define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */ #define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */ #define SPI_NOR_OCTAL_DTR_READ BIT(17) /* Flash supports Octal DTR Read */ +#define SPI_NOR_OCTAL_DTR_PP BIT(18) /* Flash supports Octal DTR page program */ }; extern const struct flash_info spi_nor_ids[]; diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f6e7592458..63f78baaf4 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3026,7 +3026,8 @@ static int spi_nor_init_params(struct spi_nor *nor, * Since xSPI Page Program opcode is backward compatible with * Legacy SPI, use Legacy SPI opcode there as well. */ - if (CONFIG_IS_ENABLED(SPI_FLASH_DTR_ENABLE)) { + if (CONFIG_IS_ENABLED(SPI_FLASH_DTR_ENABLE) && info->flags & SPI_NOR_OCTAL_DTR_PP) { + params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR], SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); } -- 2.27.0

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[PATCH 05/30] mtd: spi-nor: Add support for cross die read in dual flash configuration
by Tejas Bhumkar 06 Dec '23

06 Dec '23

From: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> In a dual parallel configuration, halve the read offset. Determine whether the read offset points to the lower or upper flash in a dual stacked configuration and set the corresponding flags accordingly. Include support for cases where the read involves an odd number of bytes. Extend support for cross-die reads in flash memory devices that contain multiple dies within them. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> --- drivers/mtd/spi/spi-nor-core.c | 61 ++++++++++++++++++++++++++++++---- include/spi.h | 3 +- 2 files changed, 56 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e505648e5d..f6e7592458 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1503,11 +1503,8 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, struct spi_nor *nor = mtd_to_spi_nor(mtd); int ret; u32 offset = from; - u32 stack_shift = 0; - u32 read_len = 0; - u32 rem_bank_len = 0; - u8 bank; - u8 is_ofst_odd = 0; + u32 bank_size, stack_shift = 0, read_len = 0, rem_bank_len = 0; + u8 bank, cur_bank, nxt_bank, is_ofst_odd = 0; dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); @@ -1541,6 +1538,40 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, } } + if (nor->addr_width == 4) { + /* + * Some flash devices like N25Q512 have multiple dies + * in it. Read operation in these devices is bounded + * by its die segment. In a continuous read, across + * multiple dies, when the last byte of the selected + * die segment is read, the next byte read is the + * first byte of the same die segment. This is Die + * cross over issue. So to handle this issue, split + * a read transaction, that spans across multiple + * banks, into one read per bank. Bank size is 16MB + * for single and dual stacked mode and 32MB for dual + * parallel mode. + */ + if (nor->spi && nor->spi->multi_die) { + bank_size = SZ_16M; + if (nor->flags & SNOR_F_HAS_PARALLEL) + bank_size <<= 1; + cur_bank = offset / bank_size; + nxt_bank = (offset + len) / bank_size; + if (cur_bank != nxt_bank) + rem_bank_len = (bank_size * + (cur_bank + 1)) - + offset; + else + rem_bank_len = (mtd->size >> + stack_shift) - + offset; + } else { + rem_bank_len = (mtd->size >> stack_shift) - + offset; + } + } + if (nor->flags & SNOR_F_HAS_PARALLEL) offset /= 2; @@ -1552,6 +1583,15 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, #endif } + if (len < rem_bank_len) + read_len = len; + else + read_len = rem_bank_len; + + ret = spi_nor_wait_till_ready(nor); + if (ret) + goto read_err; + ret = nor->read(nor, offset, read_len, buf); if (ret == 0) { /* We shouldn't see 0-length reads */ @@ -1561,8 +1601,15 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, if (ret < 0) goto read_err; - *retlen += ret; - buf += ret; + if (is_ofst_odd == 1) { + memcpy(buf, (buf + 1), (len - 1)); + *retlen += (ret - 1); + buf += ret - 1; + is_ofst_odd = 0; + } else { + *retlen += ret; + buf += ret; + } from += ret; len -= ret; } diff --git a/include/spi.h b/include/spi.h index eb015ecbf5..9014066ee3 100644 --- a/include/spi.h +++ b/include/spi.h @@ -165,7 +165,7 @@ struct spi_slave { unsigned int max_write_size; void *memory_map; - u8 flags; + u32 flags; #define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */ #define SPI_XFER_END BIT(1) /* Deassert CS after transfer */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) @@ -179,6 +179,7 @@ struct spi_slave { */ bool multi_cs_cap; u32 bytemode; + bool multi_die; /* flash with multiple dies */ }; /** -- 2.27.0

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[PATCH 04/30] mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes
by Tejas Bhumkar 06 Dec '23

06 Dec '23

From: Ashok Reddy Soma <ashok.reddy.soma(a)amd.com> Enable mt35xu512aba_fixups for all mt35 series flashes to work in DTR mode, and return after nor->fixups is updated, otherwise it will get overwritten with macronix_octal_fixups. This flash works in DTR mode only if CONFIG_SPI_FLASH_MT35XU is enabled and SPI_NOR_OCTAL_DTR_READ flag is set in id table. Additionally, a new flag, "SPI_XFER_SET_DDR," has been introduced to instruct the Ospi controller driver to switch to DDR mode. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)amd.com> Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> --- drivers/mtd/spi/spi-nor-core.c | 8 +++++++- include/spi.h | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 8949dab548..e505648e5d 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3991,6 +3991,7 @@ static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor) if (ret) return ret; + nor->spi->flags |= SPI_XFER_SET_DDR; buf = SPINOR_MT_OCT_DTR; op = (struct spi_mem_op) SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), @@ -4305,8 +4306,13 @@ void spi_nor_set_fixups(struct spi_nor *nor) #endif #ifdef CONFIG_SPI_FLASH_MT35XU - if (!strcmp(nor->info->name, "mt35xu512aba")) + if (!strcmp(nor->info->name, "mt35xu512aba") || + !strcmp(nor->info->name, "mt35xl512aba") || + !strcmp(nor->info->name, "mt35xu01g") || + !strcmp(nor->info->name, "mt35xu02g")) { nor->fixups = &mt35xu512aba_fixups; + return; + } #endif #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX) diff --git a/include/spi.h b/include/spi.h index 6bc8808bb9..eb015ecbf5 100644 --- a/include/spi.h +++ b/include/spi.h @@ -171,6 +171,7 @@ struct spi_slave { #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) #define SPI_XFER_U_PAGE BIT(4) #define SPI_XFER_STACKED BIT(5) +#define SPI_XFER_SET_DDR BIT(6) /* * Flag indicating that the spi-controller has multi chip select * capability and can assert/de-assert more than one chip select -- 2.27.0

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[PATCH 03/30] arm64: versal: Enable defconfig for Micron octal flashes
by Tejas Bhumkar 06 Dec '23

06 Dec '23

The Micron MT35 series octal flashes can be activated through the configuration option CONFIG_SPI_FLASH_MT35XU. To ensure their detection, enable this option in the default defconfig for octal flashes. Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 6a2c03ccdd..ec7caacca0 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -95,6 +95,7 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000 CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_MT35XU=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y -- 2.27.0

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[PATCH 01/30] mtd: spi-nor: Add config to enable flash DTR
by Tejas Bhumkar 06 Dec '23

06 Dec '23

From: T Karthik Reddy <t.karthik.reddy(a)amd.com> The spi-nor framework will set up the flash parameters by reading the flash id table flags, which include cmd opcodes, address width, dummy bytes, and bus width. In case, flash supports octal DTR mode and the controller does not support the DTR. There is no process to switch back to SDR mode. To avoid this issue, create a Kconfig option SPI_FLASH_DTR_ENABLE to explicitly specify to enable/disable flash DTR support. This config is disabled by default. Do not initialize the mt35xu512aba post sfdp fixups unless SPI_FLASH_DTR_ENABLE is enabled to avoid configuring DTR. Signed-off-by: T Karthik Reddy <t.karthik.reddy(a)amd.com> Co-developed-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar(a)amd.com> --- drivers/mtd/spi/Kconfig | 7 +++++++ drivers/mtd/spi/spi-nor-core.c | 12 +++++++++--- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 732b076045..e0898074a2 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -202,6 +202,13 @@ config SPI_FLASH_MT35XU because the fixup hooks for this flash add extra size overhead. Boards that don't use the flash can disable this to save space. +config SPI_FLASH_DTR_ENABLE + bool "Enable Flash DTR support" + help + Select this config to enable DTR mode by spi-nor framework. + This config provides an option to explicitly enable/disable the DTR + support even though the flash id flags specify flash supports DTR mode. + config SPI_FLASH_SST bool "SST SPI flash support" help diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 5c3ffc80eb..473d9f41f3 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2962,7 +2962,8 @@ static int spi_nor_init_params(struct spi_nor *nor, SNOR_PROTO_1_1_8); } - if (info->flags & SPI_NOR_OCTAL_DTR_READ) { + if (CONFIG_IS_ENABLED(SPI_FLASH_DTR_ENABLE) && + info->flags & SPI_NOR_OCTAL_DTR_READ) { params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR], 0, 20, SPINOR_OP_READ_FAST, @@ -2978,8 +2979,10 @@ static int spi_nor_init_params(struct spi_nor *nor, * Since xSPI Page Program opcode is backward compatible with * Legacy SPI, use Legacy SPI opcode there as well. */ - spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR], - SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); + if (CONFIG_IS_ENABLED(SPI_FLASH_DTR_ENABLE)) { + spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR], + SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); + } if (info->flags & SPI_NOR_QUAD_READ) { params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; @@ -4011,6 +4014,9 @@ static void mt35xu512aba_default_init(struct spi_nor *nor) static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor, struct spi_nor_flash_parameter *params) { + if (!CONFIG_IS_ENABLED(SPI_FLASH_DTR_ENABLE)) + return; + /* Set the Fast Read settings. */ params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR], -- 2.27.0

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[PATCH v2 0/3] rpi5: initial support
by Dmitry Malkin 05 Dec '23

05 Dec '23

These patches bring initial boot support for RPI5. Without it the latest master fails with the message: > DRAM: mbox: Timeout waiting for response > bcm2835: Could not query ARM memory size With those patches and rpi_arm64_defconfig (with disabled CONFIG_VIDEO_BCM2835) I'm able to get a working u-boot prompt (over serial). FDT comes from firmware (EEPROM). > U-Boot 2024.01-rc3-00003 > > DRAM: 1016 MiB (effective 8 GiB) > mbox: Header response code invalid > bcm2835: Could not query board revision > FDT model : Raspberry Pi 5 Model B Rev 1.0 > Core: 14 devices, 7 uclasses, devicetree: board > MMC: > Loading Environment from FAT... ** Bad device specification mmc 0 ** > In: serial,usbkbd > Out: serial,vidconsole > Err: serial,vidconsole > Net: No ethernet found. > starting USB... > No working controllers found > Hit any key to stop autoboot: 0 > No working controllers found > No ethernet found. > No ethernet found. > U-Boot> These patches are based on v2024.01-rc3 and tested with RPI5 8GB. Known issues: * CONFIG_VIDEO_BCM2835 doesn't work. * MBOX get board revision (0x10002) doesn't work (the response status is 0x8000_0001). Looks like a number of tags doesn't work anymore (board/serial/MAC) but could be fetched from FW FDT. v2: explicitly set .data section for rpi_bcm283x_mbox_addr due to relocation issue update memory map with VPU range add a patch to get human readable model from FW FDT Dmitry Malkin (3): rpi5: add initial memory map for bcm2712 rpi5: add alternative way to get MBOX address via FDT node rpi5: get_board is no longer works. Print model name from FW FDT arch/arm/mach-bcm283x/include/mach/base.h | 1 + arch/arm/mach-bcm283x/include/mach/mbox.h | 4 +-- arch/arm/mach-bcm283x/init.c | 40 ++++++++++++++++++++++- board/raspberrypi/rpi/rpi.c | 6 ++++ 4 files changed, 48 insertions(+), 3 deletions(-) -- 2.40.1

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[PATCH v7 0/2] arm64: Add a build target for Flat Image Tree
by Simon Glass 05 Dec '23

05 Dec '23

Flat Image Tree (FIT) is a widely used file format for packaging a kernel and associated devicetree files[1]. It is not specific to any one bootloader, as it is supported by U-Boot, coreboot, Linuxboot, Tianocore and Barebox. This series adds support for building a FIT as part of the kernel build. This makes it easy to try out the kernel - just load the FIT onto your tftp server and it will run automatically on any supported arm64 board. The script is written in Python, since it is easy to build a FIT using the Python libfdt bindings. For now, no attempt is made to compress files in parallel, so building the 900-odd files takes a while, about 6 seconds with my testing. The series also includes a few minor clean-up patches. [1] https://github.com/open-source-firmware/flat-image-tree Changes in v7: - Drop the kbuild tag - Add Image as a dependency of image.fit - Drop kbuild tag - Add dependency on dtbs - Drop unnecessary path separator for dtbs - Rebase to -next Changes in v6: - Drop the unwanted .gz suffix Changes in v5: - Drop patch previously applied - Correct compression rule which was broken in v4 Changes in v4: - Use single quotes for UIMAGE_NAME Changes in v3: - Drop temporary file image.itk - Drop patch 'Use double quotes for image name' - Drop double quotes in use of UIMAGE_NAME - Drop unnecessary CONFIG_EFI_ZBOOT condition for help - Avoid hard-coding "arm64" for the DT architecture Changes in v2: - Drop patch previously applied - Add .gitignore file - Move fit rule to Makefile.lib using an intermediate file - Drop dependency on CONFIG_EFI_ZBOOT - Pick up .dtb files separately from the kernel - Correct pylint too-many-args warning for write_kernel() - Include the kernel image in the file count - Add a pointer to the FIT spec and mention of its wide industry usage - Mention the kernel version in the FIT description Simon Glass (2): arm64: Add BOOT_TARGETS variable arm64: boot: Support Flat Image Tree MAINTAINERS | 7 + arch/arm64/Makefile | 13 +- arch/arm64/boot/.gitignore | 1 + arch/arm64/boot/Makefile | 6 +- scripts/Makefile.lib | 13 ++ scripts/make_fit.py | 289 +++++++++++++++++++++++++++++++++++++ 6 files changed, 326 insertions(+), 3 deletions(-) create mode 100755 scripts/make_fit.py -- 2.43.0.rc2.451.g8631bc7472-goog

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