December 2023 - U-Boot

[PATCH v2 0/9] acpi: add ACPI support on QEMU ARM and RISC-V
by Heinrich Schuchardt 18 Dec '23

18 Dec '23

QEMU 8.1.2 can create ACPI tables for the ARM and RISC-V architectures Allow passing them through to the operating system. Provide a new config fragment that enables this. v2: consider ARM architecture too invoke write_acpi_tables() via EVT_LAST_STAGE_INIT Heinrich Schuchardt (9): acpi: Kconfig symbol CONFIG_QFW_ACPI acpi: carve out qfw_acpi.c arrm: add ACPI fields to global data risc-v: add ACPI fields to global data acpi: enable writing ACPI tables on QEMU risc-v: add support for QEMU firmware tables riscv: allow usage of ACPI configs: qemu: add config fragment for ACPI arm: enable support for QEMU firmware tables MAINTAINERS | 1 + arch/Kconfig | 1 + arch/arm/include/asm/global_data.h | 4 + arch/riscv/include/asm/global_data.h | 4 + board/emulation/configs/acpi.config | 3 + board/emulation/qemu-arm/Kconfig | 1 + board/emulation/qemu-riscv/Kconfig | 2 + doc/board/emulation/acpi.rst | 23 +++ doc/board/emulation/index.rst | 1 + drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 1 + drivers/misc/qfw.c | 240 ----------------------- drivers/misc/qfw_acpi.c | 281 +++++++++++++++++++++++++++ lib/acpi/Makefile | 2 +- lib/acpi/acpi_writer.c | 4 +- 15 files changed, 332 insertions(+), 243 deletions(-) create mode 100644 board/emulation/configs/acpi.config create mode 100644 doc/board/emulation/acpi.rst create mode 100644 drivers/misc/qfw_acpi.c -- 2.40.1

4 19

[PATHv1 0/9] net fixes prior lwip
by Maxim Uvarov 18 Dec '23

18 Dec '23

Add small net fixes prior lwip patch. CI for this patch set: https://dev.azure.com/u-boot/u-boot/_build/results?buildId=7460&view=results Maxim Uvarov (9): test_net: print out net list net: sandbox: fix NULL pointer derefences net/smc911x: fix return from smc911x_send sandbox: eth-raw-os: successful return code is 0 driver/net/rtl8139: remove debug print mach-socfpga: do not overlap defines with lwip bcm_ns3: fix overlap define with lwip omap3: rename mem_init Makefile: add dtbs to clean Makefile | 3 ++- arch/arm/include/asm/arch-omap3/mem.h | 2 +- arch/arm/mach-omap2/omap3/board.c | 2 +- arch/arm/mach-omap2/omap3/emif4.c | 4 ++-- arch/arm/mach-omap2/omap3/sdrc.c | 6 +++--- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 6 ------ arch/arm/mach-socfpga/wrap_handoff_soc64.c | 9 +++++++++ arch/sandbox/cpu/eth-raw-os.c | 2 +- drivers/net/rtl8139.c | 2 +- drivers/net/sandbox.c | 3 +++ drivers/net/smc911x.c | 2 +- include/configs/bcm_ns3.h | 6 +++--- test/py/tests/test_net.py | 2 ++ 13 files changed, 29 insertions(+), 20 deletions(-) -- 2.30.2

3 12

[PATCH 1/1] cmd: CONFIG_CMD_BOOTEFI_HELLO_COMPILE dependencies
by Heinrich Schuchardt 18 Dec '23

18 Dec '23

CONFIG_EFI_LOADER cannot be chosen for ARM v7m. Remove the superfluous dependency on CONFIG_CPU_V7M=n. Fixes: b20bb09b2108 ("efi_loader: restrict EFI_LOADER to armv7 and armv8 on ARM") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- cmd/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index 748b959961..0ae5bcd981 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -373,7 +373,7 @@ config CMD_BOOTEFI_BOOTMGR config CMD_BOOTEFI_HELLO_COMPILE bool "Compile a standard EFI hello world binary for testing" - depends on CMD_BOOTEFI && !CPU_V7M + depends on CMD_BOOTEFI default y help This compiles a standard EFI hello world application with U-Boot so -- 2.40.1

3 2

[PATCH v6 0/9] Qualcomm PMIC fixes
by Caleb Connolly 18 Dec '23

18 Dec '23

This series addresses some long-standing issues with the SPMI arb driver, the PMIC, and the PMIC GPIO. It fixes compatibility with upstream Linux devicetrees, and simplifies pwrkey/resin support by rewriting the pon driver to be a button driver rather than a GPIO driver. Existing users are adjusted to use the new button driver in their oard init code. This series is based on the pinctrl [1] and clock [2] cleanup series. There may be some DTS conflicts applying it standalone. [1]: https://lore.kernel.org/u-boot/20231106-b4-qcom-pinctrl-v2-0-406e8d8689ca@l… [2]: https://lore.kernel.org/u-boot/20231103-b4-qcom-clk-v3-0-8d2d460ece84@linar… --- Changes in v6: - Drop spurious change to qcom_pmic_gpio udevice_id table that was left in by mistake - Drop bank-name property from qcs404-evb.dts that was missed previously - Link to v5: https://lore.kernel.org/r/20231130-b4-qcom-dt-compat-v5-0-41500e237ad0@lina… Changes in v5: - Split "rework pwrkey driver into a button driver" into multiple commits - Split "qcom_pmic: fix support for upstream DT" into multiple commits - Link to v4: https://lore.kernel.org/r/20231128-b4-qcom-dt-compat-v4-0-949d0982d1de@lina… Changes in v4: * Remove some now unsupported DT binding docs * Fix qcs404 SPMI arb dts * Link to v3: https://lore.kernel.org/r/20231114-b4-qcom-dt-compat-v3-0-88a92f8f00ba@lina… Changes in v3: * Remove now-unneeded header includes in dragonboard{410,820}c-uboot.dtsi * Drop non-standard DTS support from PMIC GPIO driver * Also remove old gpio-keys nodes from starqltechn-uboot.dtsi * Link to v2: https://lore.kernel.org/r/20231108-b4-qcom-dt-compat-v2-0-713233c72948@lina… Changes in v2: * Avoid using non-standard "label" and "linux,code" properties for buttons * Add missing sdm845 DTS parts * Put button driver in drivers/button * Link to v1: https://lore.kernel.org/r/20231106-b4-qcom-dt-compat-v1-0-0ccbb7841241@lina… --- Caleb Connolly (9): gpio: qcom_pmic: fix silent dev_read_addr downcast button: qcom-pmic: introduce Qualcomm PMIC button driver mach-snapdragon: switch to PMIC button driver gpio: qcom_pmic: drop pon GPIO driver gpio: qcom_pmic: support upstream DT dts: qcom: adjust pmic gpio to use upstream bindings gpio: qcom_pmic: drop gpio-count property spmi: msm: fix register range names pmic: qcom: dont use dev_read_addr to get USID MAINTAINERS | 1 + arch/arm/dts/dragonboard410c-uboot.dtsi | 11 -- arch/arm/dts/dragonboard410c.dts | 25 +++- arch/arm/dts/dragonboard820c-uboot.dtsi | 12 -- arch/arm/dts/dragonboard820c.dts | 26 ++-- arch/arm/dts/dragonboard845c-uboot.dtsi | 11 -- arch/arm/dts/dragonboard845c.dts | 4 + arch/arm/dts/qcs404-evb.dts | 10 +- arch/arm/dts/sdm845.dtsi | 28 ++-- arch/arm/dts/starqltechn-uboot.dtsi | 10 -- arch/arm/dts/starqltechn.dts | 20 +-- arch/arm/mach-snapdragon/Kconfig | 3 + arch/arm/mach-snapdragon/init_sdm845.c | 45 ++----- board/qualcomm/dragonboard410c/dragonboard410c.c | 31 ++--- board/qualcomm/dragonboard820c/dragonboard820c.c | 29 ++-- doc/device-tree-bindings/gpio/pm8916_gpio.txt | 48 ------- doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt | 94 ------------- doc/device-tree-bindings/spmi/spmi-msm.txt | 26 ---- drivers/button/Kconfig | 9 ++ drivers/button/Makefile | 1 + drivers/button/button-qcom-pmic.c | 165 +++++++++++++++++++++++ drivers/gpio/Kconfig | 5 +- drivers/gpio/qcom_pmic_gpio.c | 138 +++++-------------- drivers/power/pmic/pmic_qcom.c | 13 +- drivers/spmi/spmi-msm.c | 46 +++---- 25 files changed, 337 insertions(+), 474 deletions(-) --- base-commit: 11b868d152760a49895e051c285926a0461abcef // Caleb (they/them)

2 15

[PATCH v2 1/1] arm64: zynqmp: Enable usb3 for k24 som
by Neal Frager 18 Dec '23

18 Dec '23

Currently, the u-boot zynqmp psgtr driver is not connected to the usb dwc3 driver. Without this, the only way for u-boot to be able to use usb3 is if the psgtr serdes clocking is already enabled in the psu_init_gpl.c. This patch enables the psgtr serdes for usb3 use, so the u-boot dwc3 driver will work properly on boards based on the k24 som. In addition, this patch correctly configures mio76 and mio77 as gpio pins which are used as reset gpio pins on the kd240 starter kit. This patch is needed for enabling u-boot to load an OS on the kd240 starter kit by either usb3 or the sd card interface connected over the usb3 to sd card bridge. Signed-off-by: Neal Frager <neal.frager(a)amd.com> --- V1->V2: - rebased patch to latest u-boot master branch - improved git commit message --- .../zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c | 283 +++++++++++++++++- 1 file changed, 270 insertions(+), 13 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c index 166e61431b..591f093752 100644 --- a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c @@ -72,6 +72,18 @@ static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); } +static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) +{ + Xil_Out32(0xFD409914, 0xF3); + Xil_Out32(0xFD409940, 0xF3); + Xil_Out32(0xFD409990, 0x20); + Xil_Out32(0xFD409924, 0x37); + return 1; +} + static unsigned long psu_pll_init_data(void) { psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); @@ -528,8 +540,8 @@ static unsigned long psu_mio_init_data(void) psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U); psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U); psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02020U); psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); @@ -569,21 +581,16 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U); psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); - psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); - psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); - psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000080U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000010U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000004U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); @@ -591,13 +598,111 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x01000000U); + psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x01000000U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0100U); mask_delay(1); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0000U); mask_delay(5); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0100U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + + serdes_illcalib(0, 0, 3, 0, 0, 0, 0, 0); + psu_mask_write(0xFD410014, 0x00000007U, 0x00000003U); + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD40A3E4, 0x00000010U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); return 1; } @@ -911,6 +1016,157 @@ static unsigned long psu_ddr_phybringup_data(void) return 1; } +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int rdata = 0; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + + rdata = Xil_In32(0xFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0xFD40289C, rdata); + int count = 0; + do { + if (count == 1100000) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + } while ((rdata & 0x0000000E) != 0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + xil_printf("#SERDES initialization timed out\n\r"); + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if (p_code >= 0x26 && p_code <= 0x3C) + match_pmos_code[p_code - 0x26] += 1; + + if (n_code >= 0x26 && n_code <= 0x3C) + match_nmos_code[n_code - 0x26] += 1; + + if (i_code >= 0xC && i_code <= 0x12) + match_ical_code[i_code - 0xC] += 1; + + if (r_code >= 0x6 && r_code <= 0xC) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + static void init_peripheral(void) { psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); @@ -927,6 +1183,7 @@ int psu_init(void) status &= psu_ddr_init_data(); status &= psu_ddr_phybringup_data(); status &= psu_peripherals_init_data(); + status &= init_serdes(); init_peripheral(); status &= psu_afi_config(); -- 2.25.1

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[PATCH v2] net: wget: Support non-default HTTP port
by Marek Vasut 18 Dec '23

18 Dec '23

Currently the wget command is hard wired to HTTP port 80. This is inconvenient, as it is extremely easy to start trivial HTTP server as an unprivileged user using e.g. python http module to serve the files, but such a server has to run on one of the higher ports: " $ python3 -m http.server -d $(pwd) 8080 " Make it possible to configure HTTP server port the same way it is possible to configure TFTP server port, using environment variable 'httpdstp' (similar to 'tftpdstp'). Retain port 80 as the default fallback port. This way, users can start their own trivial server and conveniently download whatever files they need into U-Boot. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> Cc: Duncan Hare <DuncanCHare(a)yahoo.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Ramon Fried <rfried.dev(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> --- V2: Update documentation --- doc/usage/cmd/wget.rst | 3 ++- doc/usage/environment.rst | 4 ++++ include/net/wget.h | 1 - net/wget.c | 14 ++++++++++---- 4 files changed, 16 insertions(+), 6 deletions(-) diff --git a/doc/usage/cmd/wget.rst b/doc/usage/cmd/wget.rst index e1e7f8d8145..8e7383b6c60 100644 --- a/doc/usage/cmd/wget.rst +++ b/doc/usage/cmd/wget.rst @@ -16,7 +16,8 @@ Description The wget command is used to download a file from an HTTP server. wget command will use HTTP over TCP to download files from an HTTP server. -Currently it can only download image from an HTTP server hosted on port 80. +By default the destination port is 80 and the source port is pseudo-random. +The environment variable *httpdstp* can be used to set the destination port. address memory address for the data downloaded diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index c57b717caaf..82b6ea7b6e7 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -306,6 +306,10 @@ ethrotate anything other than "no", U-Boot does go through all available network interfaces. +httpdstp + If this is set, the value is used for HTTP's TCP + destination port instead of the default port 80. + netretry When set to "no" each network operation will either succeed or fail without retrying. diff --git a/include/net/wget.h b/include/net/wget.h index da0920de118..6714f7ea573 100644 --- a/include/net/wget.h +++ b/include/net/wget.h @@ -17,6 +17,5 @@ enum wget_state { }; #define DEBUG_WGET 0 /* Set to 1 for debug messages */ -#define SERVER_PORT 80 #define WGET_RETRY_COUNT 30 #define WGET_TIMEOUT 2000UL diff --git a/net/wget.c b/net/wget.c index 6ae2237a0a8..817c5ebd5d0 100644 --- a/net/wget.c +++ b/net/wget.c @@ -19,6 +19,9 @@ DECLARE_GLOBAL_DATA_PTR; +/* The default, change with environment variable 'httpdstp' */ +#define SERVER_PORT 80 + static const char bootfile1[] = "GET "; static const char bootfile3[] = " HTTP/1.0\r\n\r\n"; static const char http_eom[] = "\r\n\r\n"; @@ -134,19 +137,22 @@ static void wget_send_stored(void) int len = retry_len; unsigned int tcp_ack_num = retry_tcp_seq_num + (len == 0 ? 1 : len); unsigned int tcp_seq_num = retry_tcp_ack_num; + unsigned int server_port; uchar *ptr, *offset; + server_port = env_get_ulong("httpdstp", 10, SERVER_PORT) & 0xffff; + switch (current_wget_state) { case WGET_CLOSED: debug_cond(DEBUG_WGET, "wget: send SYN\n"); current_wget_state = WGET_CONNECTING; - net_send_tcp_packet(0, SERVER_PORT, our_port, action, + net_send_tcp_packet(0, server_port, our_port, action, tcp_seq_num, tcp_ack_num); packets = 0; break; case WGET_CONNECTING: pkt_q_idx = 0; - net_send_tcp_packet(0, SERVER_PORT, our_port, action, + net_send_tcp_packet(0, server_port, our_port, action, tcp_seq_num, tcp_ack_num); ptr = net_tx_packet + net_eth_hdr_size() + @@ -161,14 +167,14 @@ static void wget_send_stored(void) memcpy(offset, &bootfile3, strlen(bootfile3)); offset += strlen(bootfile3); - net_send_tcp_packet((offset - ptr), SERVER_PORT, our_port, + net_send_tcp_packet((offset - ptr), server_port, our_port, TCP_PUSH, tcp_seq_num, tcp_ack_num); current_wget_state = WGET_CONNECTED; break; case WGET_CONNECTED: case WGET_TRANSFERRING: case WGET_TRANSFERRED: - net_send_tcp_packet(0, SERVER_PORT, our_port, action, + net_send_tcp_packet(0, server_port, our_port, action, tcp_seq_num, tcp_ack_num); break; } -- 2.42.0

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[PATCH] arm: spl: Use separate fault handlers instead of a single common one
by Csókás Bence 18 Dec '23

18 Dec '23

It may be necessary to set breakpoints etc. on a specific fault handler in SPL. Add a Kconfig option to separate the different handlers into their own individual infinite loops. Signed-off-by: Csókás Bence <csokas.bence(a)prolan.hu> --- arch/arm/Kconfig | 9 +++++++++ arch/arm/lib/vectors.S | 18 ++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 328e2ddc33..a6ddbad30c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -79,6 +79,15 @@ config SPL_SYS_NO_VECTOR_TABLE depends on SPL bool +config SPL_USE_SEPARATE_FAULT_HANDLERS + bool "Use separate fault handlers instead of a single common one" + depends on !SPL_SYS_NO_VECTOR_TABLE && !ARM64 && !CPU_V7M + help + Instead of a common fault handler, generate a separate one for + undefined_instruction, software_interrupt, prefetch_abort etc. + This is for debugging purposes, when you want to set breakpoints + on them separately. + config LINUX_KERNEL_IMAGE_HEADER depends on ARM64 bool diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 7cf7d1636f..a14bca6fb8 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -138,11 +138,29 @@ _fiq: .word fiq #if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) .align 5 undefined_instruction: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b undefined_instruction +#endif software_interrupt: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b software_interrupt +#endif prefetch_abort: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b prefetch_abort +#endif data_abort: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b data_abort +#endif not_used: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b not_used +#endif irq: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b irq +#endif fiq: 1: b 1b /* hang and never return */ -- 2.25.1

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[ANN] U-Boot v2024.01-rc5 released
by Tom Rini 18 Dec '23

18 Dec '23

Hey all, It's release day and here is -rc5. At this point, I think we've got all the fixes I know of that are critical enough to come in for a release that's just over 3 weeks away, with many people on holidays during that time. If I'm wrong however, please speak up and let me know what still must come in now. In terms of a changelog, git log --merges v2024.01-rc4..v2024.01-rc5 contains what I've pulled but as always, better PR messages and tags will provide better results here. At this point we have one more -rc release on Tuesday, January 2nd, 2024 and then the final release a week later on January 8th, 2024. Thanks all! -- Tom

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[PATCH v2] mtd: spi-nor: Add IS25LP02G flash support
by Venkatesh Yadav Abbarapu 18 Dec '23

18 Dec '23

Add support for ISSI 256MB flash IS25LP02G. This part supports 4byte opcodes. It also supports dual and quad read. Signed-off-by: Sreekanth Sunnam <Sreekanth.Sunnam(a)amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- Changes in v2: - Fixed the name to Sreekanth Sunnam. --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3cb132dcff..9a73198227 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -217,6 +217,8 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp02g", 0x9d6022, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, -- 2.17.1

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[PATCH] mtd: spi-nor: Update block protection flags for ospi flash parts
by Venkatesh Yadav Abbarapu 18 Dec '23

18 Dec '23

Updating the block protection flags for Gigadevice gd25lx256e and ISSI is25wx256 OSPI flash parts. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- drivers/mtd/spi/spi-nor-ids.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 77eb9f352c..b939780889 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -191,7 +191,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) + SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, /* adding these 1.8V OSPI flash parts */ {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K | @@ -233,7 +234,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, - SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | + SPI_NOR_HAS_TB) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ -- 2.17.1

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