December 2023 - U-Boot

[PATCH v1] drivers: spi: Add MT25U01G part number for SPI NOR Flash
by Jit Loon Lim 14 Dec '23

14 Dec '23

MT25QU01 OPN with 4B OPCODE support is currently not supported in source code and the driver reuses the definition for "n25q00a" which has the same silicon ID but is a slower part. Adding mt25u01g definition to the source code to support a faster read response for MT25QU01 QSPI NOR Flash device. Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3ca46330bb..1b2e88cd26 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -311,6 +311,8 @@ const struct flash_info spi_nor_ids[] = { { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + { INFO6("mt25qu01g", 0x20bb21, 0x104400, 64 * 1024, 2048, SECT_4K | USE_FSR | +SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, -- 2.26.2

2 1

[PATCH] drivers: mtd: Add MT25QU128AB params
by seanedmond＠linux.microsoft.com 14 Dec '23

14 Dec '23

From: Godfrey Mwangi <godmwan(a)microsoft.com> Add Micron MT25QU128AB flash. Signed-off-by: Godfrey Mwangi <godmwan(a)microsoft.com> --- drivers/mtd/spi/spi-nor-ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4587215984..a99bb6125b 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -299,6 +299,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) }, { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) }, + { INFO("mt25qu128ab", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, -- 2.40.0

2 1

[PATCH v2] spi: cadence_qspi: Select flash subnode at runtime
by Udit Kumar 14 Dec '23

14 Dec '23

Currently spi driver gets flash parameter from first subnode. Few boards have more than one flash with different parameters and selection of flash is done by on board switch settings. In such case, uboot needs to be recompiled with updated device tree to align with board switch settings. This patch allows to select flash node at runtime. Boards those are supporting multiple flashes needs to implement cadence_qspi_get_subnode function and return correct flash node. Cc: Apurva Nandan <a-nandan(a)ti.com> Signed-off-by: Udit Kumar <u-kumar1(a)ti.com> Reviewed-by: Neha Malcom Francis <n-francis(a)ti.com> --- One of such platform is J721S2 EVM link https://www.ti.com/lit/pdf/spruj69 Fig 3.1, Page 18 has details of two flashes connected with one controller Change log: Changes in v2 - Corrected link in comment - removed extra space - Added Reviewed-by, after addressing v1 feedback - link to v1 https://lore.kernel.org/all/20230907092143.4110817-1-u-kumar1@ti.com/ drivers/spi/cadence_qspi.c | 7 ++++++- drivers/spi/cadence_qspi.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index cc3a54f295..eb7fbf83d0 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -40,6 +40,11 @@ __weak int cadence_qspi_versal_flash_reset(struct udevice *dev) return 0; } +__weak ofnode cadence_qspi_get_subnode(struct udevice *dev) +{ + return dev_read_first_subnode(dev); +} + static int cadence_spi_write_speed(struct udevice *bus, uint hz) { struct cadence_spi_priv *priv = dev_get_priv(bus); @@ -401,7 +406,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) plat->is_dma = dev_read_bool(bus, "cdns,is-dma"); /* All other parameters are embedded in the child node */ - subnode = dev_read_first_subnode(bus); + subnode = cadence_qspi_get_subnode(bus); if (!ofnode_valid(subnode)) { printf("Error: subnode with SPI flash config missing!\n"); return -ENODEV; diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 1c59d1a9d9..12825f8911 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -304,6 +304,7 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv); int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); int cadence_qspi_versal_flash_reset(struct udevice *dev); +ofnode cadence_qspi_get_subnode(struct udevice *dev); void cadence_qspi_apb_enable_linear_mode(bool enable); #endif /* __CADENCE_QSPI_H__ */ -- 2.34.1

2 1

[PATCH v1] spi: spi-nor-ids: add flash model w25q01/02 support
by Jim Liu 14 Dec '23

14 Dec '23

add flash w25q01jv, w25q01jvfim and w25q02jv support Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/mtd/spi/spi-nor-ids.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4587215984..fd74efe609 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -512,6 +512,16 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q01jvfim", 0xef7021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25q02jv", 0xef7022, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -- 2.25.1

2 1

[patch v1] arm add initial support for the Phytium Pe2201 Board board：phytium：add pe2201 folder，It initializes pcie, ddr and other aspects of phytium pe2201 board dts：add phytium_pe2201.dts，it is device tree of phytium pe2201 board, include pcie and uart node
by TracyMg_Li＠outlook.com 14 Dec '23

14 Dec '23

From: TracyMg_Li <TracyMg_Li(a)outlook.com> Signed-off-by: TracyMg_Li <TracyMg_Li(a)outlook.com> --- arch/arm/Kconfig | 8 ++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pe2201.dts | 43 +++++++ board/phytium/pe2201/Kconfig | 12 ++ board/phytium/pe2201/MAINTAINERS | 8 ++ board/phytium/pe2201/Makefile | 12 ++ board/phytium/pe2201/cpu.h | 64 +++++++++++ board/phytium/pe2201/ddr.c | 190 +++++++++++++++++++++++++++++++ board/phytium/pe2201/pcie.c | 60 ++++++++++ board/phytium/pe2201/pe2201.c | 92 +++++++++++++++ board/phytium/pe2201/pll.c | 75 ++++++++++++ board/phytium/pe2201/sec.c | 37 ++++++ configs/pe2201_defconfig | 40 +++++++ include/configs/pe2201.h | 32 ++++++ 14 files changed, 674 insertions(+) create mode 100644 arch/arm/dts/phytium-pe2201.dts create mode 100644 board/phytium/pe2201/Kconfig create mode 100644 board/phytium/pe2201/MAINTAINERS create mode 100644 board/phytium/pe2201/Makefile create mode 100644 board/phytium/pe2201/cpu.h create mode 100644 board/phytium/pe2201/ddr.c create mode 100644 board/phytium/pe2201/pcie.c create mode 100644 board/phytium/pe2201/pe2201.c create mode 100644 board/phytium/pe2201/pll.c create mode 100644 board/phytium/pe2201/sec.c create mode 100644 configs/pe2201_defconfig create mode 100644 include/configs/pe2201.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d812685c98..8a8f8805a0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2060,6 +2060,13 @@ config TARGET_POMELO Support for pomelo platform. It has 8GB Sdram, uart and pcie. +config TARGET_PE2201 + bool "Support Phytium PE2201 Platform" + select ARM64 + help + Support for pe2201 platform. + It has 2GB Sdram, uart and pcie. + config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2336,6 +2343,7 @@ source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" source "board/phytium/pomelo/Kconfig" +source "board/phytium/pe2201/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5fc888680b..ce2fc626b0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1469,6 +1469,7 @@ dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb +dtb-$(CONFIG_TARGET_PE2201) += phytium-pe2201.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb diff --git a/arch/arm/dts/phytium-pe2201.dts b/arch/arm/dts/phytium-pe2201.dts new file mode 100644 index 0000000000..e661e80f06 --- /dev/null +++ b/arch/arm/dts/phytium-pe2201.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Phytium pe2201 board + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ +/dts-v1/; + +/ { + model = "Phytium pe2201 Board"; + compatible = "phytium,pe2201"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + uart0: serial@2800c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800c000 0x0 0x1000>; + clock = <100000000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + }; +}; diff --git a/board/phytium/pe2201/Kconfig b/board/phytium/pe2201/Kconfig new file mode 100644 index 0000000000..f2f222b5d3 --- /dev/null +++ b/board/phytium/pe2201/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PE2201 + +config SYS_BOARD + default "pe2201" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "pe2201" + +endif diff --git a/board/phytium/pe2201/MAINTAINERS b/board/phytium/pe2201/MAINTAINERS new file mode 100644 index 0000000000..f583d631d2 --- /dev/null +++ b/board/phytium/pe2201/MAINTAINERS @@ -0,0 +1,8 @@ +PE2201 BOARD +M: lixinde <lixinde(a)phytium.com.cn> +M: weichangzheng <weichangzheng(a)phytium.com.cn> +S: Maintained +F: board/phytium/pe2201/* +F: include/configs/pe2201.h +F: configs/pe2201_defconfig +F: arch/arm/dts/phytium-pe2201.dts diff --git a/board/phytium/pe2201/Makefile b/board/phytium/pe2201/Makefile new file mode 100644 index 0000000000..5350f0f818 --- /dev/null +++ b/board/phytium/pe2201/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023, Phytium Technology Co., Ltd. +# lixinde <lixinde(a)phytium.com.cn> +# weichangzheng <weichangzheng(a)phytium.com.cn> +# + +obj-y += pe2201.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o diff --git a/board/phytium/pe2201/cpu.h b/board/phytium/pe2201/cpu.h new file mode 100644 index 0000000000..01adbb0a17 --- /dev/null +++ b/board/phytium/pe2201/cpu.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef _FT_PE2201_H +#define _FT_PE2201_H + +/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05 + +/* CPU RESET */ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8 + +/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460020 + +/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460021 +#define CFG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define X1X1X1X1 0x2 +#define X1X1 0x0 +#define EP_MODE 0x0 +#define RC_MODE 0x1 +#define GEN3 3 + +/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460024 +#define PARAM_MCU_VERSION 0x3 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x1 + +#define RDIMM_TYPE 0x1 +#define UDIMM_TYPE 0x2 +#define LPDDR4_TYPE 0x10 +#define DIMM_X8 0x1 +#define DIMM_X16 0x2 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC + +/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013 + +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void); + +#endif /* _FT_PE2201_H */ diff --git a/board/phytium/pe2201/ddr.c b/board/phytium/pe2201/ddr.c new file mode 100644 index 0000000000..549d211ccd --- /dev/null +++ b/board/phytium/pe2201/ddr.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct ddr_spd { + /***************** read from spd ******************/ + u8 dimm_type; /* 1: RDIMM; 2: UDIMM; 3: SODIMM; 4: LRDIMM */ + u8 data_width; /* 0: x4; 1: x8; 2: x16; 3: x32 */ + u8 mirror_type; /* 0: standard; 1: mirror */ + u8 ecc_type; /* 0: no-ecc; 1: ecc */ + u8 dram_type; /* 0xB: DDR3; 0xC: DDR4 */ + u8 rank_num; + u8 row_num; + u8 col_num; + + u8 bg_num; /* DDR4/DDR5 */ + u8 bank_num; + u16 module_manufacturer_id; + u16 taamin; + u16 trcdmin; + + u16 trpmin; + u16 trasmin; + u16 trcmin; + u16 tfawmin; /* only DDR3/DDR4 */ + + u16 trrd_smin; /* only DDR4 */ + u16 trrd_lmin; /* only DDR4 */ + u16 tccd_lmin; /* only DDR4 */ + u16 twrmin; + + u16 twtr_smin; /* only DDR4 */ + u16 twtr_lmin; /* only DDR4 */ + u32 trfc1min; + + u32 trfc2min; + u32 trfc4_rfcsbmin; /* DDR4: tRFC4min; DDR5: tRFCsbmin */ + u8 resv[8]; + + /***************** RCD control words ******************/ + u8 f0rc03; /* bit[3:2]:CS bit[1:0]:CA */ + u8 f0rc04; /* bit[3:2]:ODT bit[1:0]:CKE */ + u8 f0rc05; /* bit[3:2]:CLK-A side bit[1:0]:CLK-B side */ + u8 rcd_num; /* Registers used on RDIMM */ + + u8 lrdimm_resv[4]; + u8 lrdimm_resv1[8]; + u8 lrdimm_resv2[8]; +} __attribute((aligned(4))); + +struct mcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + + u8 ch_enable; + u8 resv1[7]; + + u64 misc_enable; + + u8 train_debug; + u8 train_recover; + u8 train_param_type; + u8 train_param_1; /* DDR4: cpu_odt */ + u8 train_param_2; /* DDR4: cpu_drv */ + u8 train_param_3; /* DDR4: mr_drv */ + u8 train_param_4; /* DDR4: rtt_nom */ + u8 train_param_5; /* DDR4: rtt_park */ + + u8 train_param_6; /* DDR4: rtt_wr */ + u8 resv2[7]; + + /***************** for LPDDR4 dq swap ******************/ + u32 data_byte_swap; + u32 slice0_dq_swizzle; + + u32 slice1_dq_swizzle; + u32 slice2_dq_swizzle; + + u32 slice3_dq_swizzle; + u32 slice4_dq_swizzle; + + u32 slice5_dq_swizzle; + u32 slice6_dq_swizzle; + + u32 slice7_dq_swizzle; + u8 resv3[4]; + u8 resv4[8]; + + struct ddr_spd ddr_spd_info; +} __attribute((aligned(4))); + +static void get_mcu_up_info_default(struct mcu_config *pm) +{ + pm->magic = PARAMETER_MCU_MAGIC; + pm->version = PARAM_MCU_VERSION; + pm->size = PARAM_MCU_SIZE; + pm->ch_enable = PARAM_CH_ENABLE; +} + +static u8 init_dimm_param(struct mcu_config *pm) +{ + debug("manual config dimm info...\n"); + pm->misc_enable = 0x2001; + pm->train_debug = 0x0; + pm->train_recover = 0x0; + pm->train_param_type = 0x0; + pm->train_param_1 = 0x0; + pm->train_param_2 = 0x0; + pm->train_param_3 = 0x0; + pm->train_param_4 = 0x0; + pm->train_param_5 = 0x0; + pm->train_param_6 = 0x0; + + pm->data_byte_swap = 0x76543210; + pm->slice0_dq_swizzle = 0x3145726; + + pm->slice1_dq_swizzle = 0x54176230; + pm->slice2_dq_swizzle = 0x57604132; + + pm->slice3_dq_swizzle = 0x20631547; + pm->slice4_dq_swizzle = 0x16057423; + + pm->slice5_dq_swizzle = 0x16057423; + pm->slice6_dq_swizzle = 0x16057423; + + pm->slice7_dq_swizzle = 0x16057423; + + pm->ddr_spd_info.dimm_type = RDIMM_TYPE; + pm->ddr_spd_info.data_width = DIMM_X16; + pm->ddr_spd_info.mirror_type = NO_MIRROR; + pm->ddr_spd_info.ecc_type = NO_ECC_TYPE; + pm->ddr_spd_info.dram_type = LPDDR4_TYPE; + pm->ddr_spd_info.rank_num = 0x1; + pm->ddr_spd_info.row_num = 0x10; + pm->ddr_spd_info.col_num = 0xa; + pm->ddr_spd_info.bg_num = 0x0; + pm->ddr_spd_info.bank_num = 0x8; + pm->ddr_spd_info.taamin = 0x0; + pm->ddr_spd_info.trcdmin = 0x0; + + pm->ddr_spd_info.trpmin = 0x0; + pm->ddr_spd_info.trasmin = 0x0; + pm->ddr_spd_info.trcmin = 0x0; + pm->ddr_spd_info.tfawmin = 0x0; + + pm->ddr_spd_info.trrd_smin = 0x0; + pm->ddr_spd_info.trrd_lmin = 0x0; + pm->ddr_spd_info.tccd_lmin = 0x0; + pm->ddr_spd_info.twrmin = 0x0; + + pm->ddr_spd_info.twtr_smin = 0x0; + pm->ddr_spd_info.twtr_lmin = 0x0; + + return 0; +} + +void get_default_mcu_info(u8 *data) +{ + get_mcu_up_info_default((struct mcu_config *)data); +} + +void fix_mcu_info(u8 *data) +{ + struct mcu_config *mcu_info = (struct mcu_config *)data; + + init_dimm_param(mcu_info); +} + +void ddr_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + get_default_mcu_info(buffer); + fix_mcu_info(buffer); + + arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("DRAM init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pe2201/pcie.c b/board/phytium/pe2201/pcie.c new file mode 100644 index 0000000000..34c38d2aee --- /dev/null +++ b/board/phytium/pe2201/pcie.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pcu_ctr { + u32 base_config[4]; + u32 equalization[4]; + u8 rev[72]; +} __attribute((aligned(4))); + +struct pcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 independent_tree; + u32 base_cfg; + u8 rev2[16]; + struct pcu_ctr ctr_cfg[2]; +} __attribute((aligned(4))); + +struct pcu_config const peu_base_info = { + .magic = PARAMETER_PCIE_MAGIC, + .version = 0x4, + .size = 0x100, + .independent_tree = CFG_INDEPENDENT_TREE, + .base_cfg = ((PCI_PEU1 | (X1X1X1X1 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X1X1 << 1))), + .ctr_cfg[0].base_config[0] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[1] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[2] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[0] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[1] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[2] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].equalization[0] = 0x7, + .ctr_cfg[0].equalization[1] = 0x7, + .ctr_cfg[0].equalization[2] = 0x7, + .ctr_cfg[1].equalization[0] = 0x7, + .ctr_cfg[1].equalization[1] = 0x7, + .ctr_cfg[1].equalization[2] = 0x7, +}; + +void pcie_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &peu_base_info, sizeof(peu_base_info)); + arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PCIE init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c new file mode 100644 index 0000000000..0e837b0f50 --- /dev/null +++ b/board/phytium/pe2201/pe2201.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include <asm/u-boot.h> +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int mach_cpu_init(void) +{ + check_reset(); + return 0; +} + +int board_early_init_f(void) +{ + pcie_init(); + return 0; +} + +int dram_init(void) +{ + debug("Phytium ddr init\n"); + ddr_init(); + + gd->mem_clk = 0; + gd->ram_size = PHYS_SDRAM_1_SIZE; + + sec_init(); + debug("PBF relocate done\n"); + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct arm_smccc_res res; + + debug("run in reset cpu\n"); + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("reset cpu error, %lx\n", res.a0); +} + +static struct mm_region pe2201_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x7b000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NS | PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = pe2201_mem_map; + +int last_stage_init(void) +{ + return 0; +} diff --git a/board/phytium/pe2201/pll.c b/board/phytium/pe2201/pll.c new file mode 100644 index 0000000000..f46435c74b --- /dev/null +++ b/board/phytium/pe2201/pll.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pll_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 clust0_pll; + u32 clust1_pll; + u32 clust2_pll; + u32 noc_pll; + u32 dmu_pll; +} __attribute((aligned(4))); + +struct pll_config const pll_base_info = { + .magic = PARAMETER_PLL_MAGIC, + .version = 0x2, + .size = 0x100, + .clust0_pll = 2000, + .clust1_pll = 2000, + .clust2_pll = 2000, + .noc_pll = 1800, + .dmu_pll = 600, +}; + +u32 get_reset_source(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res); + + return res.a0; +} + +void pll_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &pll_base_info, sizeof(pll_base_info)); + arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PLL init failed :0x%lx\n", res.a0); +} + +void check_reset(void) +{ + u32 rst; + + rst = get_reset_source(); + + switch (rst) { + case CPU_RESET_POWER_ON: + pll_init(); + break; + case CPU_RESET_PLL: + break; + case CPU_RESET_WATCH_DOG: + break; + default: + panic("other reset source\n"); + } +} diff --git a/board/phytium/pe2201/sec.c b/board/phytium/pe2201/sec.c new file mode 100644 index 0000000000..6a980d6ea6 --- /dev/null +++ b/board/phytium/pe2201/sec.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct common_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u64 core_bit_map; +} __attribute((aligned(4))); + +struct common_config const common_base_info = { + .magic = PARAMETER_COMMON_MAGIC, + .version = 0x1, + .core_bit_map = 0x3333, +}; + +void sec_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &common_base_info, sizeof(common_base_info)); + arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("SEC init failed :0x%lx\n", res.a0); +} diff --git a/configs/pe2201_defconfig b/configs/pe2201_defconfig new file mode 100644 index 0000000000..5a2f8f6f5e --- /dev/null +++ b/configs/pe2201_defconfig @@ -0,0 +1,40 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_PE2201=y +CONFIG_TEXT_BASE=0x38180000 +CONFIG_SYS_MALLOC_LEN=0x101000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30c1a000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="phytium-pe2201" +CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_PSCI_RESET is not set +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x90000000 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon=pl011,0x2800c000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pe2201#" +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_PCI=y +CONFIG_CMD_DM=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_BLK=y +# CONFIG_MMC is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_PHYTIUM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/pe2201.h b/include/configs/pe2201.h new file mode 100644 index 0000000000..ff24dc5ac6 --- /dev/null +++ b/include/configs/pe2201.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef __PE2201_CONFIG_H +#define __PE2201_CONFIG_H + +/* SDRAM Bank #1 start address */ +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x74000000 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* BOOT */ +#define BOOT_TARGET_DEVICES(func) \ + func(SCSI, scsi, 0) \ + +#include <config_distro_bootcmd.h> + +/* Initial environment variables */ +#define CFG_EXTRA_ENV_SETTINGS \ + "image=Image\0" \ + BOOTENV \ + "scriptaddr=0x90100000\0" \ + "kernel_addr_r=0x90200000\0" \ + "fdt_addr_r=0x95000000\0" \ + "boot_fit=no\0" \ + "fdtfile=phytium-pe2201.dtb\0" \ + +#endif -- 2.17.1

2 1

[PATCH v2 1/1] arm64: zynqmp: Add output-enable pins to SOMs
by Neal Frager 14 Dec '23

14 Dec '23

Now that the zynqmp pinctrl driver supports the tri-state registers, make sure that the pins requiring output-enable are configured appropriately for SOMs. Without it, all tristate setting for MIOs, which are not related to SOM itself, are using default configuration which is not correct setting. It means SDs, USBs, ethernet, etc. are not working properly. In past it was fixed through calling tristate configuration via bootcmd: usb_init=mw 0xFF180208 2020 kv260_gem3=mw 0xFF18020C 0xFC0 && gpio toggle gpio@ff0a000038 && \ gpio toggle gpio@ff0a000038 Signed-off-by: Neal Frager <neal.frager(a)amd.com> --- V1->V2: - remove output-enable from gem1 conf-rx pins --- arch/arm/dts/zynqmp-sck-kd-g-revA.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dts b/arch/arm/dts/zynqmp-sck-kd-g-revA.dts index 56f3128528..12865392a3 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dts @@ -175,6 +175,7 @@ conf-tx { pins = "MIO36"; bias-disable; + output-enable; }; mux { @@ -226,6 +227,7 @@ conf-bootstrap { pins = "MIO44", "MIO49"; bias-disable; + output-enable; low-power-disable; }; @@ -233,6 +235,7 @@ pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42", "MIO43"; bias-disable; + output-enable; low-power-enable; }; @@ -241,6 +244,7 @@ slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; mux-mdio { @@ -271,6 +275,7 @@ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + output-enable; drive-strength = <4>; slew-rate = <SLEW_RATE_SLOW>; }; @@ -298,6 +303,7 @@ pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; + output-enable; drive-strength = <4>; slew-rate = <SLEW_RATE_SLOW>; }; -- 2.25.1

3 2

[PATCH v6 0/6] spi-nor: Add parallel and stacked memories support
by Venkatesh Yadav Abbarapu 14 Dec '23

14 Dec '23

This series adds support for Xilinx qspi parallel and stacked memeories. In parallel mode, the current implementation assumes that a maximum of two flashes are connected. The QSPI controller splits the data evenly between both the flashes so, both the flashes that are connected in parallel mode should be identical. During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in nor->flags. In stacked mode the current implementation assumes that a maximum of two flashes are connected and both the flashes are of same make but can differ in sizes. So, except the sizes all other flash parameters of both the flashes are identical. Spi-nor will pass on the appropriate flash select flag to low level driver, and it will select pass all the data to that particular flash. Write operation in parallel mode are performed in page size * 2 chunks as each write operation results in writing both the flashes. For doubling the address space each operation is performed at addr/2 flash offset, where addr is the address specified by the user. Similarly for read and erase operations it will read from both flashes, so size and offset are divided by 2 and send to flash. Changes in v2: - Fixed the compilation issues. Changes in v3: - Fixed the CI issues. Changes in v4: - Removed the dio,dummy_bytes variables from zynq_qspi driver. - Fix the compilation issue by including the DM_SPI config. Changes in v5: - Fixed the issue reported by buildman. Changes in v6: - Fixed the issues reported while running the sandbox test cases. Ashok Reddy Soma (4): mtd: spi-nor: Add parallel and stacked memories support mtd: spi-nor: Add parallel memories support for read_sr and read_fsr mtd: spi-nor: Add parallel and stacked memories support in read_bar and write_bar spi: spi-uclass: Read chipselect and restrict capabilities Venkatesh Yadav Abbarapu (2): spi: zynqmp_gqspi: Add parallel memories support in GQSPI driver spi: zynq_qspi: Add parallel memories support in QSPI driver drivers/mtd/spi/sandbox.c | 2 +- drivers/mtd/spi/spi-nor-core.c | 401 +++++++++++++++++++++++++++++---- drivers/spi/altera_spi.c | 4 +- drivers/spi/atcspi200_spi.c | 2 +- drivers/spi/ath79_spi.c | 2 +- drivers/spi/atmel_spi.c | 6 +- drivers/spi/bcm63xx_hsspi.c | 42 ++-- drivers/spi/bcm63xx_spi.c | 6 +- drivers/spi/bcmbca_hsspi.c | 34 +-- drivers/spi/cf_spi.c | 6 +- drivers/spi/davinci_spi.c | 6 +- drivers/spi/fsl_dspi.c | 18 +- drivers/spi/fsl_espi.c | 4 +- drivers/spi/fsl_qspi.c | 4 +- drivers/spi/gxp_spi.c | 2 +- drivers/spi/mpc8xx_spi.c | 4 +- drivers/spi/mpc8xxx_spi.c | 10 +- drivers/spi/mscc_bb_spi.c | 4 +- drivers/spi/mxc_spi.c | 6 +- drivers/spi/npcm_fiu_spi.c | 14 +- drivers/spi/nxp_fspi.c | 2 +- drivers/spi/octeon_spi.c | 2 +- drivers/spi/omap3_spi.c | 4 +- drivers/spi/pic32_spi.c | 2 +- drivers/spi/rk_spi.c | 4 +- drivers/spi/rockchip_sfc.c | 2 +- drivers/spi/spi-aspeed-smc.c | 28 +-- drivers/spi/spi-mxic.c | 6 +- drivers/spi/spi-qup.c | 4 +- drivers/spi/spi-sifive.c | 6 +- drivers/spi/spi-sn-f-ospi.c | 2 +- drivers/spi/spi-sunxi.c | 6 +- drivers/spi/spi-synquacer.c | 4 +- drivers/spi/spi-uclass.c | 23 +- drivers/spi/stm32_qspi.c | 2 +- drivers/spi/stm32_spi.c | 4 +- drivers/spi/ti_qspi.c | 14 +- drivers/spi/xilinx_spi.c | 4 +- drivers/spi/zynq_qspi.c | 119 ++++++++-- drivers/spi/zynq_spi.c | 6 +- drivers/spi/zynqmp_gqspi.c | 141 ++++++++++-- include/linux/mtd/spi-nor.h | 12 + include/spi.h | 23 +- lib/acpi/acpi_device.c | 2 +- 44 files changed, 773 insertions(+), 226 deletions(-) -- 2.25.1

2 7

[GIT PULL] u-boot-riscv/master
by Leo Yu-Chi Liang(梁育齊) 14 Dec '23

14 Dec '23

Hi Tom, The following changes since commit 20d0464300c25db673cfb5e4539aa3767606d151: Merge tag 'u-boot-imx-20231212' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2023-12-12 16:33:57 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 8c785ddb7ae8d675faf558c81a29938cb0ec2b35: riscv: sifive: unmatched: migrate to text environment (2023-12-13 16:19:43 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18889 ---------------------------------------------------------------- - VisionFive2: Enable CONFIG_SYSRESET - StarFive: Modify starfive timer driver - AMD/Xilinx: Add MicroBlaze V support - Unmatched: Migrate to text environment ---------------------------------------------------------------- Jaehoon Chung (2): riscv: dts: jh7110: Add a gpio-restart node configs: visionfive2: Enable CONFIG_SYSRESET config Kuan Lim Lee (1): timer: starfive: Add Starfive timer support Michal Simek (1): riscv: Add support for AMD/Xilinx MicroBlaze V Yong-Xuan Wang (1): riscv: sifive: unmatched: migrate to text environment arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 2 + arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 5 ++ arch/riscv/dts/xilinx-mbv32.dts | 106 +++++++++++++++++++++++ board/sifive/unmatched/unmatched.env | 19 ++++ board/xilinx/Kconfig | 3 +- board/xilinx/common/board.c | 5 ++ board/xilinx/mbv/Kconfig | 28 ++++++ board/xilinx/mbv/MAINTAINERS | 7 ++ board/xilinx/mbv/Makefile | 5 ++ board/xilinx/mbv/board.c | 11 +++ configs/sifive_unmatched_defconfig | 2 +- configs/starfive_visionfive2_defconfig | 1 + configs/xilinx_mbv32_defconfig | 30 +++++++ configs/xilinx_mbv32_smode_defconfig | 32 +++++++ drivers/timer/starfive-timer.c | 16 ++-- include/configs/sifive-unmatched.h | 37 -------- include/configs/xilinx_mbv.h | 6 ++ 18 files changed, 273 insertions(+), 46 deletions(-) create mode 100644 arch/riscv/dts/xilinx-mbv32.dts create mode 100644 board/sifive/unmatched/unmatched.env create mode 100644 board/xilinx/mbv/Kconfig create mode 100644 board/xilinx/mbv/MAINTAINERS create mode 100644 board/xilinx/mbv/Makefile create mode 100644 board/xilinx/mbv/board.c create mode 100644 configs/xilinx_mbv32_defconfig create mode 100644 configs/xilinx_mbv32_smode_defconfig create mode 100644 include/configs/xilinx_mbv.h Best regards, Leo

3 3

Pull request: Please pull u-boot-imx-next-20231214
by Fabio Estevam 14 Dec '23

14 Dec '23

Hi Tom, Please pull this u-boot-imx material targetted for 'next', thanks. The following changes since commit be4a5f7c35685d228b3abc398a8d86c434274de5: test: bdinfo: Handle systems without getopt (2023-12-10 10:08:30 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-next-20231214 for you to fetch changes up to 6b73200aedb1d3fb0a52e2600bd6b1e3ff5e5faf: arm64: imx8mp: Enable TCP, IPv6, wget on Data Modul i.MX8M eDM SBC (2023-12-14 06:24:27 -0300) u-boot-imx-next-20231214 ------------------------ CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/18918 - Add TPM support for venice boards - Add networking support for imx93-evk - Enable TCP, IPv6, wget for DHCOM and Data Modul boards - Enable fastboot support for Toradex boards - Allow pico-imx7d to boot from SD - Enable fastboot for beacon imx8m beacon boards, disabled SYS_CONSOLE_IS_IN_ENV - Fix mxsboot to prevent NAND blocks being reported as bad - Add imx8mm PWM clock support - Several devicetree syncs with the kernel - Add support for i.MX8MP Polyhex Debix Model A SBC - Reworked ddr_load_train_firmware() to get a 50ms boot time improvement ---------------------------------------------------------------- Adam Ford (5): configs: imx8mp_beacon: Do not set SYS_CONSOLE_IS_IN_ENV configs: imx8mm_beacon: Enable fastboot downloading configs: imx8mm_beacon: Disable the WDT autostart configs: imx8mn_beacon: Do not set SYS_CONSOLE_IS_IN_ENV configs: imx8mn_beacon: Disable the WDT autostart Alessandro Rubini (1): tools: mxsboot: pre-fill buffer with 0xff, not 0 Arnaud Ferraris (2): librem5: properly set the `fdtfile` env variable librem5: Add addresses for compressed kernel load Benjamin Szőke (1): pico-imx7d: add baseboard SD card boot detect Cem Tenruh (1): arm: dts: imx8mm-phyboard-polis-rdk: Sync dts files with kernel Fabio Estevam (14): imx8qm_dmsse20a1: Improve SPL memory configuration imx7d-sdb: Sync devicetree with kernel 6.5-rc1 imx8mp_evk: Convert to DM_PMIC imx8mp_evk: Add myself to MAINTAINERS arm: dts: imx8mm: Sync with linux-next 20231019 arm: dts: imx8mn: Sync with linux-next 20231019 arm: dts: imx8mp: Sync with linux-next 20231019 phy: phy-imx8mq-usb: Remove .exit operation imx8mp_evk: Simplify Ethernet initialization imx8mp_evk: Remove unneeded header files clock_imx8mm: Add a stub for imx8mp_fec_interface_init() pico-imx7d: Remove board_phy_config() imx7d-pico-pi-u-boot.dtsi: Fix aliases indentation imx: imx-hab: Select SPL_DRIVERS_MISC in the SPL case Gilles Talis (1): imx: imx8mp: Add support for Polyhex Debix Model A SBC Hiago De Franco (2): apalis/colibri imx6/imx6ull/imx7: defconfig: Enable fastboot support board: apalis/colibri imx6/imx6ull/imx7: Add fastboot bootcmd support Hugo Villeneuve (4): imx8mn-var-som: add manufacturer to target description imx8mn_var_som: Add myself to MAINTAINERS imx8mn-var-som: Simplify FEC initialization MAINTAINERS: Remove non-working address from MAINTAINERS Igor Opaniuk (1): imx: imx8: ahab: refactor do_ahab_close command Marek Vasut (5): arm: mxs: Fix ICOLL macro name typo arm: mxs: Clear CPSR V bit to activate low vectors arm: imx6: Enable TCP, IPv6, wget on DH i.MX6 DHCOM arm64: imx8mp: Enable TCP, IPv6, wget on DH i.MX8MP DHCOM arm64: imx8mp: Enable TCP, IPv6, wget on Data Modul i.MX8M eDM SBC Nicolas Heemeryck (1): clk: imx8mn: add pwm clocks Ricardo Salveti (1): ARM: imx8ulp: support env in fat and ext4 Shawn Guo (1): ddr: imx: Save the FW loading if it hasn't changed Sébastien Szymanski (4): net: dwc_eth_qos: add i.MX93 support net: dwc_eth_qos: Add board_interface_eth_init() for i.MX93 net: phy: realtek: Add support for RTL8211F(D)(I)-VD-CG arm: dts: imx93-evk: remove wrong eqos compatible string Tim Harvey (2): arm: dts: imx8mm-venice-gw73xx: add TPM device arm: dts: imx8mp-venice-gw73xx: add TPM device arch/arm/cpu/arm926ejs/mxs/mxs.c | 4 + arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 8 +- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx7d-pico-pi-u-boot.dtsi | 11 +- arch/arm/dts/imx7d-sdb-u-boot.dtsi | 51 - arch/arm/dts/imx7d-sdb.dts | 73 +- ....dtsi => imx8mm-phyboard-polis-rdk-u-boot.dtsi} | 0 arch/arm/dts/imx8mm-phyboard-polis-rdk.dts | 460 +++++ arch/arm/dts/imx8mm-phycore-som.dtsi | 440 +++++ arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi | 7 + arch/arm/dts/imx8mm-venice-gw73xx.dtsi | 10 +- arch/arm/dts/imx8mm.dtsi | 153 +- arch/arm/dts/imx8mn.dtsi | 167 +- arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi | 141 ++ arch/arm/dts/imx8mp-debix-model-a.dts | 507 ++++++ arch/arm/dts/imx8mp-evk-u-boot.dtsi | 32 +- arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi | 9 + arch/arm/dts/imx8mp-venice-gw73xx.dtsi | 9 +- arch/arm/dts/imx8mp.dtsi | 542 +++++- arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 4 - arch/arm/dts/phycore-imx8mm.dts | 287 --- arch/arm/include/asm/arch-imx8/sys_proto.h | 1 + arch/arm/include/asm/arch-mxs/regs-base.h | 2 +- arch/arm/mach-imx/Kconfig | 1 + arch/arm/mach-imx/imx8/ahab.c | 45 +- arch/arm/mach-imx/imx8m/Kconfig | 10 +- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 7 + arch/arm/mach-imx/imx8ulp/soc.c | 28 +- arch/arm/mach-imx/imx9/clock.c | 53 + board/bsh/imx8mn_smm_s2/MAINTAINERS | 1 - board/freescale/imx8mp_evk/MAINTAINERS | 1 + board/freescale/imx8mp_evk/imx8mp_evk.c | 41 +- board/freescale/imx8mp_evk/spl.c | 50 +- board/freescale/imx93_evk/imx93_evk.c | 16 - board/freescale/mx7dsabresd/mx7dsabresd.c | 2 +- board/phytec/phycore_imx8mm/MAINTAINERS | 5 +- board/polyhex/imx8mp_debix_model_a/Kconfig | 15 + board/polyhex/imx8mp_debix_model_a/MAINTAINERS | 8 + board/polyhex/imx8mp_debix_model_a/Makefile | 13 + .../imx8mp_debix_model_a/imx8mp_debix_model_a.c | 55 + .../imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg | 9 + board/polyhex/imx8mp_debix_model_a/lpddr4_timing.c | 1843 ++++++++++++++++++++ board/polyhex/imx8mp_debix_model_a/spl.c | 129 ++ board/purism/librem5/librem5.c | 27 +- board/technexion/pico-imx7d/Makefile | 2 +- board/technexion/pico-imx7d/pico-imx7d.c | 88 +- board/technexion/pico-imx7d/spl.c | 91 +- board/toradex/apalis_imx6/apalis_imx6.c | 13 +- board/toradex/colibri-imx6ull/colibri-imx6ull.c | 13 +- board/toradex/colibri_imx6/colibri_imx6.c | 13 +- board/toradex/colibri_imx7/colibri_imx7.c | 14 +- board/variscite/imx8mn_var_som/MAINTAINERS | 2 +- board/variscite/imx8mn_var_som/imx8mn_var_som.c | 13 - configs/apalis_imx6_defconfig | 3 + configs/colibri-imx6ull-emmc_defconfig | 3 + configs/colibri-imx6ull_defconfig | 3 + configs/colibri_imx6_defconfig | 3 + configs/colibri_imx7_defconfig | 3 + configs/colibri_imx7_emmc_defconfig | 4 +- configs/dh_imx6_defconfig | 7 + configs/imx8mm_beacon_defconfig | 7 +- configs/imx8mm_data_modul_edm_sbc_defconfig | 5 + configs/imx8mn_beacon_defconfig | 2 + configs/imx8mp_beacon_defconfig | 1 + configs/imx8mp_data_modul_edm_sbc_defconfig | 5 + configs/imx8mp_debix_model_a_defconfig | 110 ++ configs/imx8mp_dhcom_pdk2_defconfig | 5 + configs/imx8mp_dhcom_pdk3_defconfig | 5 + configs/imx8mp_evk_defconfig | 12 +- configs/imx8qm_dmsse20a1_defconfig | 9 + configs/phycore-imx8mm_defconfig | 2 +- drivers/clk/imx/clk-imx8mn.c | 30 + drivers/ddr/imx/phy/helper.c | 7 + drivers/net/dwc_eth_qos.c | 4 + drivers/net/dwc_eth_qos_imx.c | 3 + drivers/net/phy/realtek.c | 14 + drivers/phy/phy-imx8mq-usb.c | 6 - include/configs/imx8mp_debix_model_a.h | 54 + include/configs/librem5.h | 2 + include/configs/pico-imx7d.h | 4 +- include/dt-bindings/clock/imx8mp-clock.h | 3 +- tools/mxsboot.c | 2 +- 82 files changed, 5200 insertions(+), 647 deletions(-) rename arch/arm/dts/{phycore-imx8mm-u-boot.dtsi => imx8mm-phyboard-polis-rdk-u-boot.dtsi} (100%) create mode 100644 arch/arm/dts/imx8mm-phyboard-polis-rdk.dts create mode 100644 arch/arm/dts/imx8mm-phycore-som.dtsi create mode 100644 arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-debix-model-a.dts delete mode 100644 arch/arm/dts/phycore-imx8mm.dts create mode 100644 board/polyhex/imx8mp_debix_model_a/Kconfig create mode 100644 board/polyhex/imx8mp_debix_model_a/MAINTAINERS create mode 100644 board/polyhex/imx8mp_debix_model_a/Makefile create mode 100644 board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c create mode 100644 board/polyhex/imx8mp_debix_model_a/imximage-8mp-lpddr4.cfg create mode 100644 board/polyhex/imx8mp_debix_model_a/lpddr4_timing.c create mode 100644 board/polyhex/imx8mp_debix_model_a/spl.c create mode 100644 configs/imx8mp_debix_model_a_defconfig create mode 100644 include/configs/imx8mp_debix_model_a.h

2 1

[PATCH] maintainers: rk3399: remove maintainer
by Shantur Rathore 14 Dec '23

14 Dec '23

Remove Akash Gajjar <akash(a)openedev.com> from MAINTAINERS as email is bouncing. Signed-off-by: Shantur Rathore <i(a)shantur.com> --- board/pine64/rockpro64_rk3399/MAINTAINERS | 1 - board/rockchip/evb_rk3399/MAINTAINERS | 1 - 2 files changed, 2 deletions(-) diff --git a/board/pine64/rockpro64_rk3399/MAINTAINERS b/board/pine64/rockpro64_rk3399/MAINTAINERS index 303db144aa..220ee21f23 100644 --- a/board/pine64/rockpro64_rk3399/MAINTAINERS +++ b/board/pine64/rockpro64_rk3399/MAINTAINERS @@ -1,5 +1,4 @@ ROCKPRO64 -M: Akash Gajjar <akash(a)openedev.com> M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained F: board/pine64/rockpro64_rk3399 diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index c7e412b54e..acdb840f20 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -93,7 +93,6 @@ F: configs/rock-4se-rk3399_defconfig F: arch/arm/dts/rk3399-rock-4se-u-boot.dtsi ROCK-PI-4 -M: Akash Gajjar <akash(a)openedev.com> M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained F: configs/rock-pi-4-rk3399_defconfig -- 2.40.1

3 3