December 2023 - U-Boot

[PATCH 1/2] clk: stm32f: fix setting of division factor for LCD_CLK
by Dario Binacchi 15 Dec '23

15 Dec '23

The value to be written to the register must be appropriately shifted, as is correctly done in other parts of the code. Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock") Signed-off-by: Dario Binacchi <dario.binacchi(a)amarulasolutions.com> --- drivers/clk/stm32/clk-stm32f.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c index ed7660196ef0..4c1864193357 100644 --- a/drivers/clk/stm32/clk-stm32f.c +++ b/drivers/clk/stm32/clk-stm32f.c @@ -530,7 +530,8 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate) /* set pll_saidivr with found value */ clrsetbits_le32(&regs->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK, - pllsaidivr_table[i]); + pllsaidivr_table[i] << + RCC_DCKCFGR_PLLSAIDIVR_SHIFT); return rate; } -- 2.42.0

2 5

[PATCH] ARM: dts: stm32f769-disco: rework ltdc node
by Dario Binacchi 15 Dec '23

15 Dec '23

With commit f479f5dbb7ac ("ARM: dts: stm32: add ltdc support on stm32f746 MCU"), which adds the 'ltdc' node in stm32f746.dtsi, we can simplify stm32f769-disco-uboot.dtsi and align stm32f769-disco.dtsi with the kernel version. Signed-off-by: Dario Binacchi <dario.binacchi(a)amarulasolutions.com> --- arch/arm/dts/stm32f769-disco-u-boot.dtsi | 23 +++++++++-------------- arch/arm/dts/stm32f769-disco.dts | 4 ++++ 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index 2c823cce98b4..add55c96e21f 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -70,22 +70,17 @@ }; }; }; + }; +}; - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - resets = <&rcc STM32F7_APB2_RESET(LTDC)>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; - - status = "okay"; - bootph-all; +&ltdc { + clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; + bootph-all; - ports { - port@0 { - dp_out: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; + ports { + port@0 { + dp_out: endpoint { + remote-endpoint = <&dsi_in>; }; }; }; diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts index 6f93fc7bcfcd..d63cd2ba7eb4 100644 --- a/arch/arm/dts/stm32f769-disco.dts +++ b/arch/arm/dts/stm32f769-disco.dts @@ -86,6 +86,10 @@ status = "okay"; }; +&ltdc { + status = "okay"; +}; + &rtc { status = "okay"; }; -- 2.42.0

2 3

[patch v2] ARM add initial support for the Phytium Pe2201 Board. Add pe2201 platform code and the device tree of pe2201 platform board. The initial support comprises the UART and PCIe.
by TracyMg_Li＠outlook.com 15 Dec '23

15 Dec '23

From: TracyMg_Li <TracyMg_Li(a)outlook.com> Signed-off-by: TracyMg_Li <TracyMg_Li(a)outlook.com> --- arch/arm/Kconfig | 7 ++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pe2201.dts | 43 +++++++ board/phytium/pe2201/Kconfig | 12 ++ board/phytium/pe2201/MAINTAINERS | 8 ++ board/phytium/pe2201/Makefile | 12 ++ board/phytium/pe2201/cpu.h | 64 +++++++++++ board/phytium/pe2201/ddr.c | 190 +++++++++++++++++++++++++++++++ board/phytium/pe2201/pcie.c | 60 ++++++++++ board/phytium/pe2201/pe2201.c | 92 +++++++++++++++ board/phytium/pe2201/pll.c | 75 ++++++++++++ board/phytium/pe2201/sec.c | 37 ++++++ configs/pe2201_defconfig | 40 +++++++ include/configs/pe2201.h | 32 ++++++ 14 files changed, 673 insertions(+) create mode 100644 arch/arm/dts/phytium-pe2201.dts create mode 100644 board/phytium/pe2201/Kconfig create mode 100644 board/phytium/pe2201/MAINTAINERS create mode 100644 board/phytium/pe2201/Makefile create mode 100644 board/phytium/pe2201/cpu.h create mode 100644 board/phytium/pe2201/ddr.c create mode 100644 board/phytium/pe2201/pcie.c create mode 100644 board/phytium/pe2201/pe2201.c create mode 100644 board/phytium/pe2201/pll.c create mode 100644 board/phytium/pe2201/sec.c create mode 100644 configs/pe2201_defconfig create mode 100644 include/configs/pe2201.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d812685c98..358c515a93 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2060,6 +2060,12 @@ config TARGET_POMELO Support for pomelo platform. It has 8GB Sdram, uart and pcie. +config TARGET_PE2201 + bool "Support Phytium PE2201 Platform" + select ARM64 + help + Support for pe2201 platform.It has 2GB Sdram, uart and pcie. + config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2336,6 +2342,7 @@ source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" source "board/phytium/pomelo/Kconfig" +source "board/phytium/pe2201/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5fc888680b..ce2fc626b0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1469,6 +1469,7 @@ dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb +dtb-$(CONFIG_TARGET_PE2201) += phytium-pe2201.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb diff --git a/arch/arm/dts/phytium-pe2201.dts b/arch/arm/dts/phytium-pe2201.dts new file mode 100644 index 0000000000..959584fbbb --- /dev/null +++ b/arch/arm/dts/phytium-pe2201.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Phytium pe2201 board + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ +/dts-v1/; + +/ { + model = "Phytium pe2201 Board"; + compatible = "phytium,pe2201"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + uart0: serial@2800c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2800c000 0x0 0x1000>; + clock = <100000000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + }; +}; diff --git a/board/phytium/pe2201/Kconfig b/board/phytium/pe2201/Kconfig new file mode 100644 index 0000000000..f2f222b5d3 --- /dev/null +++ b/board/phytium/pe2201/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PE2201 + +config SYS_BOARD + default "pe2201" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "pe2201" + +endif diff --git a/board/phytium/pe2201/MAINTAINERS b/board/phytium/pe2201/MAINTAINERS new file mode 100644 index 0000000000..f583d631d2 --- /dev/null +++ b/board/phytium/pe2201/MAINTAINERS @@ -0,0 +1,8 @@ +PE2201 BOARD +M: lixinde <lixinde(a)phytium.com.cn> +M: weichangzheng <weichangzheng(a)phytium.com.cn> +S: Maintained +F: board/phytium/pe2201/* +F: include/configs/pe2201.h +F: configs/pe2201_defconfig +F: arch/arm/dts/phytium-pe2201.dts diff --git a/board/phytium/pe2201/Makefile b/board/phytium/pe2201/Makefile new file mode 100644 index 0000000000..5350f0f818 --- /dev/null +++ b/board/phytium/pe2201/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023, Phytium Technology Co., Ltd. +# lixinde <lixinde(a)phytium.com.cn> +# weichangzheng <weichangzheng(a)phytium.com.cn> +# + +obj-y += pe2201.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o diff --git a/board/phytium/pe2201/cpu.h b/board/phytium/pe2201/cpu.h new file mode 100644 index 0000000000..01adbb0a17 --- /dev/null +++ b/board/phytium/pe2201/cpu.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef _FT_PE2201_H +#define _FT_PE2201_H + +/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05 + +/* CPU RESET */ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8 + +/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460020 + +/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460021 +#define CFG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define X1X1X1X1 0x2 +#define X1X1 0x0 +#define EP_MODE 0x0 +#define RC_MODE 0x1 +#define GEN3 3 + +/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460024 +#define PARAM_MCU_VERSION 0x3 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x1 + +#define RDIMM_TYPE 0x1 +#define UDIMM_TYPE 0x2 +#define LPDDR4_TYPE 0x10 +#define DIMM_X8 0x1 +#define DIMM_X16 0x2 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC + +/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013 + +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void); + +#endif /* _FT_PE2201_H */ diff --git a/board/phytium/pe2201/ddr.c b/board/phytium/pe2201/ddr.c new file mode 100644 index 0000000000..549d211ccd --- /dev/null +++ b/board/phytium/pe2201/ddr.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct ddr_spd { + /***************** read from spd ******************/ + u8 dimm_type; /* 1: RDIMM; 2: UDIMM; 3: SODIMM; 4: LRDIMM */ + u8 data_width; /* 0: x4; 1: x8; 2: x16; 3: x32 */ + u8 mirror_type; /* 0: standard; 1: mirror */ + u8 ecc_type; /* 0: no-ecc; 1: ecc */ + u8 dram_type; /* 0xB: DDR3; 0xC: DDR4 */ + u8 rank_num; + u8 row_num; + u8 col_num; + + u8 bg_num; /* DDR4/DDR5 */ + u8 bank_num; + u16 module_manufacturer_id; + u16 taamin; + u16 trcdmin; + + u16 trpmin; + u16 trasmin; + u16 trcmin; + u16 tfawmin; /* only DDR3/DDR4 */ + + u16 trrd_smin; /* only DDR4 */ + u16 trrd_lmin; /* only DDR4 */ + u16 tccd_lmin; /* only DDR4 */ + u16 twrmin; + + u16 twtr_smin; /* only DDR4 */ + u16 twtr_lmin; /* only DDR4 */ + u32 trfc1min; + + u32 trfc2min; + u32 trfc4_rfcsbmin; /* DDR4: tRFC4min; DDR5: tRFCsbmin */ + u8 resv[8]; + + /***************** RCD control words ******************/ + u8 f0rc03; /* bit[3:2]:CS bit[1:0]:CA */ + u8 f0rc04; /* bit[3:2]:ODT bit[1:0]:CKE */ + u8 f0rc05; /* bit[3:2]:CLK-A side bit[1:0]:CLK-B side */ + u8 rcd_num; /* Registers used on RDIMM */ + + u8 lrdimm_resv[4]; + u8 lrdimm_resv1[8]; + u8 lrdimm_resv2[8]; +} __attribute((aligned(4))); + +struct mcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + + u8 ch_enable; + u8 resv1[7]; + + u64 misc_enable; + + u8 train_debug; + u8 train_recover; + u8 train_param_type; + u8 train_param_1; /* DDR4: cpu_odt */ + u8 train_param_2; /* DDR4: cpu_drv */ + u8 train_param_3; /* DDR4: mr_drv */ + u8 train_param_4; /* DDR4: rtt_nom */ + u8 train_param_5; /* DDR4: rtt_park */ + + u8 train_param_6; /* DDR4: rtt_wr */ + u8 resv2[7]; + + /***************** for LPDDR4 dq swap ******************/ + u32 data_byte_swap; + u32 slice0_dq_swizzle; + + u32 slice1_dq_swizzle; + u32 slice2_dq_swizzle; + + u32 slice3_dq_swizzle; + u32 slice4_dq_swizzle; + + u32 slice5_dq_swizzle; + u32 slice6_dq_swizzle; + + u32 slice7_dq_swizzle; + u8 resv3[4]; + u8 resv4[8]; + + struct ddr_spd ddr_spd_info; +} __attribute((aligned(4))); + +static void get_mcu_up_info_default(struct mcu_config *pm) +{ + pm->magic = PARAMETER_MCU_MAGIC; + pm->version = PARAM_MCU_VERSION; + pm->size = PARAM_MCU_SIZE; + pm->ch_enable = PARAM_CH_ENABLE; +} + +static u8 init_dimm_param(struct mcu_config *pm) +{ + debug("manual config dimm info...\n"); + pm->misc_enable = 0x2001; + pm->train_debug = 0x0; + pm->train_recover = 0x0; + pm->train_param_type = 0x0; + pm->train_param_1 = 0x0; + pm->train_param_2 = 0x0; + pm->train_param_3 = 0x0; + pm->train_param_4 = 0x0; + pm->train_param_5 = 0x0; + pm->train_param_6 = 0x0; + + pm->data_byte_swap = 0x76543210; + pm->slice0_dq_swizzle = 0x3145726; + + pm->slice1_dq_swizzle = 0x54176230; + pm->slice2_dq_swizzle = 0x57604132; + + pm->slice3_dq_swizzle = 0x20631547; + pm->slice4_dq_swizzle = 0x16057423; + + pm->slice5_dq_swizzle = 0x16057423; + pm->slice6_dq_swizzle = 0x16057423; + + pm->slice7_dq_swizzle = 0x16057423; + + pm->ddr_spd_info.dimm_type = RDIMM_TYPE; + pm->ddr_spd_info.data_width = DIMM_X16; + pm->ddr_spd_info.mirror_type = NO_MIRROR; + pm->ddr_spd_info.ecc_type = NO_ECC_TYPE; + pm->ddr_spd_info.dram_type = LPDDR4_TYPE; + pm->ddr_spd_info.rank_num = 0x1; + pm->ddr_spd_info.row_num = 0x10; + pm->ddr_spd_info.col_num = 0xa; + pm->ddr_spd_info.bg_num = 0x0; + pm->ddr_spd_info.bank_num = 0x8; + pm->ddr_spd_info.taamin = 0x0; + pm->ddr_spd_info.trcdmin = 0x0; + + pm->ddr_spd_info.trpmin = 0x0; + pm->ddr_spd_info.trasmin = 0x0; + pm->ddr_spd_info.trcmin = 0x0; + pm->ddr_spd_info.tfawmin = 0x0; + + pm->ddr_spd_info.trrd_smin = 0x0; + pm->ddr_spd_info.trrd_lmin = 0x0; + pm->ddr_spd_info.tccd_lmin = 0x0; + pm->ddr_spd_info.twrmin = 0x0; + + pm->ddr_spd_info.twtr_smin = 0x0; + pm->ddr_spd_info.twtr_lmin = 0x0; + + return 0; +} + +void get_default_mcu_info(u8 *data) +{ + get_mcu_up_info_default((struct mcu_config *)data); +} + +void fix_mcu_info(u8 *data) +{ + struct mcu_config *mcu_info = (struct mcu_config *)data; + + init_dimm_param(mcu_info); +} + +void ddr_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + get_default_mcu_info(buffer); + fix_mcu_info(buffer); + + arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("DRAM init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pe2201/pcie.c b/board/phytium/pe2201/pcie.c new file mode 100644 index 0000000000..34c38d2aee --- /dev/null +++ b/board/phytium/pe2201/pcie.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pcu_ctr { + u32 base_config[4]; + u32 equalization[4]; + u8 rev[72]; +} __attribute((aligned(4))); + +struct pcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 independent_tree; + u32 base_cfg; + u8 rev2[16]; + struct pcu_ctr ctr_cfg[2]; +} __attribute((aligned(4))); + +struct pcu_config const peu_base_info = { + .magic = PARAMETER_PCIE_MAGIC, + .version = 0x4, + .size = 0x100, + .independent_tree = CFG_INDEPENDENT_TREE, + .base_cfg = ((PCI_PEU1 | (X1X1X1X1 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X1X1 << 1))), + .ctr_cfg[0].base_config[0] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[1] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[2] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[0] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[1] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[2] = (EP_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].equalization[0] = 0x7, + .ctr_cfg[0].equalization[1] = 0x7, + .ctr_cfg[0].equalization[2] = 0x7, + .ctr_cfg[1].equalization[0] = 0x7, + .ctr_cfg[1].equalization[1] = 0x7, + .ctr_cfg[1].equalization[2] = 0x7, +}; + +void pcie_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &peu_base_info, sizeof(peu_base_info)); + arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PCIE init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c new file mode 100644 index 0000000000..0e837b0f50 --- /dev/null +++ b/board/phytium/pe2201/pe2201.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include <asm/u-boot.h> +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int mach_cpu_init(void) +{ + check_reset(); + return 0; +} + +int board_early_init_f(void) +{ + pcie_init(); + return 0; +} + +int dram_init(void) +{ + debug("Phytium ddr init\n"); + ddr_init(); + + gd->mem_clk = 0; + gd->ram_size = PHYS_SDRAM_1_SIZE; + + sec_init(); + debug("PBF relocate done\n"); + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct arm_smccc_res res; + + debug("run in reset cpu\n"); + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("reset cpu error, %lx\n", res.a0); +} + +static struct mm_region pe2201_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x7b000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NS | PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = pe2201_mem_map; + +int last_stage_init(void) +{ + return 0; +} diff --git a/board/phytium/pe2201/pll.c b/board/phytium/pe2201/pll.c new file mode 100644 index 0000000000..f46435c74b --- /dev/null +++ b/board/phytium/pe2201/pll.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pll_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 clust0_pll; + u32 clust1_pll; + u32 clust2_pll; + u32 noc_pll; + u32 dmu_pll; +} __attribute((aligned(4))); + +struct pll_config const pll_base_info = { + .magic = PARAMETER_PLL_MAGIC, + .version = 0x2, + .size = 0x100, + .clust0_pll = 2000, + .clust1_pll = 2000, + .clust2_pll = 2000, + .noc_pll = 1800, + .dmu_pll = 600, +}; + +u32 get_reset_source(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res); + + return res.a0; +} + +void pll_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &pll_base_info, sizeof(pll_base_info)); + arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PLL init failed :0x%lx\n", res.a0); +} + +void check_reset(void) +{ + u32 rst; + + rst = get_reset_source(); + + switch (rst) { + case CPU_RESET_POWER_ON: + pll_init(); + break; + case CPU_RESET_PLL: + break; + case CPU_RESET_WATCH_DOG: + break; + default: + panic("other reset source\n"); + } +} diff --git a/board/phytium/pe2201/sec.c b/board/phytium/pe2201/sec.c new file mode 100644 index 0000000000..6a980d6ea6 --- /dev/null +++ b/board/phytium/pe2201/sec.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct common_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u64 core_bit_map; +} __attribute((aligned(4))); + +struct common_config const common_base_info = { + .magic = PARAMETER_COMMON_MAGIC, + .version = 0x1, + .core_bit_map = 0x3333, +}; + +void sec_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &common_base_info, sizeof(common_base_info)); + arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("SEC init failed :0x%lx\n", res.a0); +} diff --git a/configs/pe2201_defconfig b/configs/pe2201_defconfig new file mode 100644 index 0000000000..5a2f8f6f5e --- /dev/null +++ b/configs/pe2201_defconfig @@ -0,0 +1,40 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_PE2201=y +CONFIG_TEXT_BASE=0x38180000 +CONFIG_SYS_MALLOC_LEN=0x101000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30c1a000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="phytium-pe2201" +CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_PSCI_RESET is not set +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_LOAD_ADDR=0x90000000 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon=pl011,0x2800c000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pe2201#" +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_PCI=y +CONFIG_CMD_DM=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_BLK=y +# CONFIG_MMC is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_PHYTIUM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/pe2201.h b/include/configs/pe2201.h new file mode 100644 index 0000000000..3367053b3d --- /dev/null +++ b/include/configs/pe2201.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef __PE2201_CONFIG_H +#define __PE2201_CONFIG_H + +/* SDRAM Bank #1 start address */ +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x74000000 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* BOOT */ +#define BOOT_TARGET_DEVICES(func) \ + func(SCSI, scsi, 0) \ + +#include <config_distro_bootcmd.h> + +/* Initial environment variables */ +#define CFG_EXTRA_ENV_SETTINGS \ + "image=Image\0" \ + "scriptaddr=0x90100000\0" \ + "kernel_addr_r=0x90200000\0" \ + "fdt_addr_r=0x95000000\0" \ + "boot_fit=no\0" \ + "fdtfile=phytium-pe2201.dtb\0" \ + BOOTENV + +#endif -- 2.17.1

2 1

[PATCH] clk: fix clk_get_rate() always return ulong
by Julien Masson 15 Dec '23

15 Dec '23

When we call clk_get_rate(), we expect to get clock rate value as ulong. In that case we should not use log_ret() macro since it use internally an int. Otherwise we may return an invalid/truncated clock rate value. Signed-off-by: Julien Masson <jmasson(a)baylibre.com> --- drivers/clk/clk-uclass.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 3b5e3f9c86..41dcd14be5 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -488,11 +488,7 @@ ulong clk_get_rate(struct clk *clk) if (!ops->get_rate) return -ENOSYS; - ret = ops->get_rate(clk); - if (ret) - return log_ret(ret); - - return 0; + return ops->get_rate(clk); } struct clk *clk_get_parent(struct clk *clk) -- 2.41.0

2 4

[PATCH] arm: spl: Use separate fault handlers instead of a single common one
by Csókás Bence 15 Dec '23

15 Dec '23

It may be necessary to set breakpoints etc. on a specific fault handler in SPL. Add a Kconfig option to separate the different handlers into their own individual infinite loops. Signed-off-by: Csókás Bence <csokas.bence(a)prolan.hu> --- arch/arm/Kconfig | 10 ++++++++++ arch/arm/lib/vectors.S | 18 ++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 328e2ddc33..47494cb72b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -79,6 +79,16 @@ config SPL_SYS_NO_VECTOR_TABLE depends on SPL bool +config SPL_USE_SEPARATE_FAULT_HANDLERS + bool "Use separate fault handlers instead of a single common one" + depends on !SPL_SYS_NO_VECTOR_TABLE + default n + help + Instead of a common fault handler, generate a separate one for + undefined_instruction, software_interrupt, prefetch_abort etc. + This is for debugging purposes, when you want to set breakpoints + on them separately. + config LINUX_KERNEL_IMAGE_HEADER depends on ARM64 bool diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 7cf7d1636f..a14bca6fb8 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -138,11 +138,29 @@ _fiq: .word fiq #if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) .align 5 undefined_instruction: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b undefined_instruction +#endif software_interrupt: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b software_interrupt +#endif prefetch_abort: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b prefetch_abort +#endif data_abort: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b data_abort +#endif not_used: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b not_used +#endif irq: +#if CONFIG_IS_ENABLED(USE_SEPARATE_FAULT_HANDLERS) + b irq +#endif fiq: 1: b 1b /* hang and never return */ -- 2.25.1

2 3

[PATCH v2 00/21] Complete decoupling of bootm logic from commands
by Simon Glass 15 Dec '23

15 Dec '23

This series continues refactoring the bootm code to allow it to be used with CONFIG_COMMAND disabled. The OS-handling code is refactored and a new bootm_run() function is created to run through the bootm stages. This completes the work. A booti_go() function is created also, in case it proves useful, but at last for now standard boot does not use this. This is cmdd (part d of CMDLINE refactoring) It depends on dm/bootstda-working which depends on dm/cmdc-working Changes in v2: - Add new patch to enable more bootm OS methods in sandbox - Split addition of struct bootm_info to its own patch - Split changing of boot_os_fn parameters to a separate patch - Split out adding the rest of struct bootm_info fields to separate patch - Split out patch to move do_bootm_states() comment to header - Split out booti removal of #ifdef - Split out bootz removal of #ifdef - Adjust patch to focus just on dropping the do_bootm_states() arguments - Split do_bootm_states() rename to a separate patch - Rework series to allow OS access to cmdline arguments for bootm Simon Glass (21): mips: Add a reset_cpu() function m68k: Add a reset_cpu() function ppc: Add a reset_cpu() function nios2: Add a reset_cpu() function riscv: Add a reset_cpu() function bootm: Adjust how the board is reset sandbox: bootm: Enable more bootm OS methods bootm: Create a struct for argument information bootm: Adjust arguments of boot_os_fn bootm: Add more fields to bootm_info bootm: Move do_bootm_states() comment to header file booti: Avoid use of #ifdef bootz: Avoid use of #ifdef bootm: Drop arguments from do_bootm_states() bootm: Rename do_bootm_states() to bootm_run_states() bootm: Tidy up boot_selected_os() bootm: Create a function to run through the bootm states stm32: Use local vars in stm32prog for initrd and fdt bootm: Create a function to run through the bootz states stm32: Use bootm_run() and bootz_run() bootm: Create a function to run through the booti states arch/arc/lib/bootm.c | 5 +- arch/arm/lib/bootm.c | 6 +- .../cmd_stm32prog/cmd_stm32prog.c | 33 +++-- arch/m68k/lib/bootm.c | 5 +- arch/m68k/lib/traps.c | 7 + arch/microblaze/lib/bootm.c | 6 +- arch/mips/cpu/cpu.c | 8 +- arch/mips/lib/bootm.c | 8 +- arch/nios2/cpu/cpu.c | 8 +- arch/nios2/lib/bootm.c | 10 +- arch/powerpc/lib/bootm.c | 5 +- arch/powerpc/lib/traps.c | 10 ++ arch/riscv/cpu/cpu.c | 13 ++ arch/riscv/lib/bootm.c | 11 +- arch/riscv/lib/reset.c | 7 +- arch/sandbox/cpu/cpu.c | 8 ++ arch/sandbox/lib/bootm.c | 5 +- arch/sh/lib/bootm.c | 6 +- arch/x86/lib/bootm.c | 6 +- arch/xtensa/lib/bootm.c | 4 +- boot/bootm.c | 133 ++++++++++-------- boot/bootm_os.c | 78 +++++----- cmd/booti.c | 55 +++++--- cmd/bootm.c | 43 ++++-- cmd/bootz.c | 35 +++-- configs/sandbox_defconfig | 3 +- include/bootm.h | 124 ++++++++++++++-- 27 files changed, 440 insertions(+), 202 deletions(-) -- 2.43.0.472.g3155946c3a-goog

5 36

[PATCH v1 1/1] arm64: zynqmp: Fix k24 psu_init_gpl.c clocking
by Neal Frager 15 Dec '23

15 Dec '23

This patch corrects the k24 som clocking configuration such that the serdes clocks are correctly enabled and the usb0 is configured to use the psgtr refclk2 for usb3 mode. This patch also corrects the configuration of mio pins mio76 and mio77 which should be configured as gpio pins. Signed-off-by: Neal Frager <neal.frager(a)amd.com> --- .../zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c | 266 +++++++++++++----- 1 file changed, 200 insertions(+), 66 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c index 45102302dc..4c904c6c81 100644 --- a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c @@ -72,6 +72,18 @@ static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); } +static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, + u32 lane2_protocol, u32 lane2_rate, + u32 lane1_protocol, u32 lane1_rate, + u32 lane0_protocol, u32 lane0_rate) +{ + Xil_Out32(0xFD409914, 0xF3); + Xil_Out32(0xFD409940, 0xF3); + Xil_Out32(0xFD409990, 0x20); + Xil_Out32(0xFD409924, 0x37); + return 1; +} + static unsigned long psu_pll_init_data(void) { psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); @@ -490,20 +502,20 @@ static unsigned long psu_mio_init_data(void) psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U); psu_mask_write(0xFF180090, 0x000000FEU, 0x000000C0U); psu_mask_write(0xFF180094, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000080U); psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); @@ -528,8 +540,8 @@ static unsigned long psu_mio_init_data(void) psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U); psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U); psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02020U); psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); @@ -539,18 +551,18 @@ static unsigned long psu_mio_init_data(void) psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x00080814U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x00FC0814U); psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x03F7F7EBU); - psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x00FC000BU); + psu_mask_write(0xFF180160, 0x0387FFFFU, 0x0387FFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFF87FU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x0303F7EBU); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x0004400BU); psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF18017C, 0x0357FFFFU, 0x0357FFFFU); - psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x0357FFFFU); - psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x0303FFF4U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x03FBBFF4U); psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); return 1; @@ -569,21 +581,16 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U); psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); - psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); - psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); - psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000080U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000010U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000004U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); @@ -591,40 +598,26 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + psu_mask_write(0xFF0A0284, 0x03FFFFFFU, 0x01000000U); + psu_mask_write(0xFF0A0288, 0x03FFFFFFU, 0x01000000U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0100U); mask_delay(1); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0000U); mask_delay(5); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + psu_mask_write(0xFF0A0014, 0x03FF03FFU, 0x02FF0100U); return 1; } static unsigned long psu_serdes_init_data(void) { - psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U); - psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); - psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); - psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U); - psu_mask_write(0xFD402868, 0x00000082U, 0x00000002U); + psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U); - psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); - psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU); - psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U); - psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U); - psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U); - psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); - psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); - psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); - psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); @@ -678,18 +671,8 @@ static unsigned long psu_serdes_init_data(void) psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); - serdes_illcalib(0, 0, 3, 0, 4, 0, 4, 0); - psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U); + serdes_illcalib(0, 0, 3, 0, 0, 0, 0, 0); psu_mask_write(0xFD410014, 0x00000007U, 0x00000003U); - psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U); - psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); - psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); - psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U); - psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U); - return 1; } @@ -699,7 +682,7 @@ static unsigned long psu_resetout_init_data(void) psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U); psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); @@ -708,7 +691,6 @@ static unsigned long psu_resetout_init_data(void) psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); - mask_poll(0xFD4063E4, 0x00000010U); mask_poll(0xFD40A3E4, 0x00000010U); return 1; @@ -717,7 +699,7 @@ static unsigned long psu_resetout_init_data(void) static unsigned long psu_resetin_init_data(void) { psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000002U); psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); @@ -1034,6 +1016,157 @@ static unsigned long psu_ddr_phybringup_data(void) return 1; } +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int rdata = 0; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + + rdata = Xil_In32(0xFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0xFD40289C, rdata); + int count = 0; + do { + if (count == 1100000) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + } while ((rdata & 0x0000000E) != 0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + xil_printf("#SERDES initialization timed out\n\r"); + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if (p_code >= 0x26 && p_code <= 0x3C) + match_pmos_code[p_code - 0x26] += 1; + + if (n_code >= 0x26 && n_code <= 0x3C) + match_nmos_code[n_code - 0x26] += 1; + + if (i_code >= 0xC && i_code <= 0x12) + match_ical_code[i_code - 0xC] += 1; + + if (r_code >= 0x6 && r_code <= 0xC) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + static void init_peripheral(void) { psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); @@ -1050,6 +1183,7 @@ int psu_init(void) status &= psu_ddr_init_data(); status &= psu_ddr_phybringup_data(); status &= psu_peripherals_init_data(); + status &= init_serdes(); init_peripheral(); status &= psu_afi_config(); -- 2.25.1

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[PATCH 1/2] ARM: imx: Force DRAM regulators into FPWM mode on Data Modul i.MX8M Plus eDM SBC
by Marek Vasut 15 Dec '23

15 Dec '23

In case the Buck5 and Buck6 regulators which supply DRAM Vdd1 and Vdd2/Vddq respectively operate in automatic PWM/PFM mode, the DRAM EDAC detects more correctable errors than if the regulators operate in forced PWM only mode. Force DRAM regulators to forced PWM mode only to stop tempting the DRAM. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> --- board/data_modul/imx8mp_edm_sbc/spl.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index cfc4b65e0f9..a3600c8568a 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -68,6 +68,11 @@ int data_modul_imx_edm_sbc_board_power_init(void) /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c); + /* DRAM Vdd1 always FPWM */ + pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d); + /* DRAM Vdd2/Vddq always FPWM */ + pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d); + /* Set LDO4 and CONFIG2 to enable the I2C level translator. */ pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59); pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); -- 2.42.0

2 4

[PATCH] ARM: imx: Enable CAAM on DH i.MX8M Plus DHCOM
by Marek Vasut 15 Dec '23

15 Dec '23

Enable CAAM in U-Boot to make crypto available early in the boot process. This has a side-effect that in case an older kernel version contains a broken CAAM initialization timeout code, initialization in bootloader will help that old kernel version function correctly. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: u-boot(a)dh-electronics.com --- configs/imx8mp_dhcom_pdk2_defconfig | 1 + configs/imx8mp_dhcom_pdk3_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index 54c02dfd7ab..3f9b0e3733c 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -165,6 +165,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index 6799f0c8b73..50c21d51b8d 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -167,6 +167,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y -- 2.42.0

2 2

[PATCH] ARM: imx: Enable CAAM on Data Modul i.MX8M Mini/Plus eDM SBC
by Marek Vasut 15 Dec '23

15 Dec '23

Enable CAAM in U-Boot to make crypto available early in the boot process. This has a side-effect that in case an older kernel version contains a broken CAAM initialization timeout code, initialization in bootloader will help that old kernel version function correctly. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> --- configs/imx8mm_data_modul_edm_sbc_defconfig | 1 + configs/imx8mp_data_modul_edm_sbc_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index e724607c6ee..06e10869bc1 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -157,6 +157,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_FSL_CAAM=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig index ae1a48c6812..30f8636f4d5 100644 --- a/configs/imx8mp_data_modul_edm_sbc_defconfig +++ b/configs/imx8mp_data_modul_edm_sbc_defconfig @@ -164,6 +164,7 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y +CONFIG_FSL_CAAM=y CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y -- 2.42.0

2 2