November 2023 - U-Boot

[PATCH] mips: implement __udivdi3
by Sachsensolar GmbH 06 Nov '23

06 Nov '23

From: Linus Walleij <linus.walleij(a)linaro.org> Squashfs wasn't compiling because the lldiv() directives turn into __udivdi3 and we are using private libgcc. After this squashfs compiles for MIPS. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- Linus, this is the updated and optimized version of your initial patch. Sorry for the long delay ;) arch/mips/lib/Makefile | 2 +- arch/mips/lib/udivdi3.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 arch/mips/lib/udivdi3.c diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 9ee1fcb5c7..1621cc9a1f 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -14,4 +14,4 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o obj-$(CONFIG_SPL_BUILD) += spl.o -lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o udivdi3.o diff --git a/arch/mips/lib/udivdi3.c b/arch/mips/lib/udivdi3.c new file mode 100644 index 0000000000..4d780117cf --- /dev/null +++ b/arch/mips/lib/udivdi3.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#include "libgcc.h" + +#if BITS_PER_LONG == 32 + +#include <div64.h> + +long long __udivdi3(long long u, word_type b) +{ + long long ret = u; + + __div64_32(&ret, b); + return ret; +} + +#endif /* BITS_PER_LONG == 32 */ -- 2.41.0

1 0

[PATCH] mips: fix change_k0_cca()
by Sachsensolar GmbH 06 Nov '23

06 Nov '23

From: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> The intention of change_k0_cca() is to read the C0.Config register into register $t0, update $t0 with the new cache coherency mode passed in $a0 and write back $t0 to C0.Config. With MIPS32 R2 or later instruction sets, this can be achieved with a single instruction with INS. The source and destination register of the INS instruction is passed as first parameter. In case of change_k0_cca() it is register $t0. But for writing back the updated value to C0.Config, the incorrect $a0 register is used. This is only correct in the MIPS32 R1 code path. Fix the `mtc0` instruction to write back the value of the $t0 register. Fix the MIPS32 R1 code path to also store the updated value in $t0. Reported by user ddqxy138 on Github. https://github.com/u-boot/u-boot/commit/b838586086af3278bcaead3720c7a18813c… Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- arch/mips/lib/cache_init.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 602741c65d..d64209d76a 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -431,9 +431,9 @@ LEAF(change_k0_cca) #else xor a0, a0, t0 andi a0, a0, CONF_CM_CMASK - xor a0, a0, t0 + xor t0, a0, t0 #endif - mtc0 a0, CP0_CONFIG + mtc0 t0, CP0_CONFIG jr.hb ra END(change_k0_cca) -- 2.41.0

1 0

[GIT PULL] Please pull u-boot-amlogic-20231106
by Neil Armstrong 06 Nov '23

06 Nov '23

Hi Tom, A little set of fix for: - also enable DFU RAM boot for libretech-ac, since it uses a different config header - SM probe fix - A1 USB missing clocks The CI job is at https://source.denx.de/u-boot/custodians/u-boot-amlogic/pipelines/18452 Thanks, Neil The following changes since commit a4c83bda17196bf5d1ce640844595aaeced6465e: Merge branch '2023-11-03-assorted-tegra-improvements' (2023-11-04 09:55:39 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-amlogic.git tags/u-boot-amlogic-20231106 for you to fetch changes up to c550e81171940932664a85bda315a6a073aae23c: ARM: configs: libretech-ac: enable USB_DFU like in meson64.h (2023-11-06 09:46:05 +0100) ---------------------------------------------------------------- - fixup to also enabled DFU RAM boot for libretech-ac - sm fix to bind child sm devices in the device tree - add missing A1 clocks for USB stack ---------------------------------------------------------------- Alexey Romanov (1): clk: a1: add new clocks for USB stack Dmitry Rokosov (1): drivers: sm: bind child sm devices in the device tree Neil Armstrong (1): ARM: configs: libretech-ac: enable USB_DFU like in meson64.h drivers/clk/meson/a1.c | 6 ++++++ drivers/sm/meson-sm.c | 1 + include/configs/libretech-ac.h | 1 + 3 files changed, 8 insertions(+)

2 1

[PATCH] net: designware: add DMA offset awareness
by Baruch Siach 06 Nov '23

06 Nov '23

Older DesignWare Ethernet MAC versions that this driver supports can only work with 32-bit DMA source/destination addresses. Some platforms have no physical RAM at the lowest 4GB address space. For these platforms the driver must translate DMA addresses to/from physical memory addresses. Call translation routines so that properly configured platforms can use the DesignWare Ethernet MAC. For platforms using device-tree this usually means adding dma-ranges property to the bus the device node is in. Signed-off-by: Baruch Siach <baruch(a)tkos.co.il> --- drivers/net/designware.c | 31 ++++++++++++++++++++----------- drivers/net/designware.h | 1 + 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 20b86e74cecf..a174344b3ef5 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -19,6 +19,7 @@ #include <net.h> #include <pci.h> #include <reset.h> +#include <phys2bus.h> #include <asm/cache.h> #include <dm/device_compat.h> #include <dm/device-internal.h> @@ -232,8 +233,10 @@ static void tx_descs_init(struct dw_eth_dev *priv) for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; - desc_p->dmamac_addr = (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE]; - desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; + desc_p->dmamac_addr = dev_phys_to_bus(priv->dev, + (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE]); + desc_p->dmamac_next = dev_phys_to_bus(priv->dev, + (ulong)&desc_table_p[idx + 1]); #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | @@ -251,14 +254,15 @@ static void tx_descs_init(struct dw_eth_dev *priv) } /* Correcting the last pointer of the chain */ - desc_p->dmamac_next = (ulong)&desc_table_p[0]; + desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]); /* Flush all Tx buffer descriptors at once */ flush_dcache_range((ulong)priv->tx_mac_descrtable, (ulong)priv->tx_mac_descrtable + sizeof(priv->tx_mac_descrtable)); - writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); + writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]), + &dma_p->txdesclistaddr); priv->tx_currdescnum = 0; } @@ -280,8 +284,10 @@ static void rx_descs_init(struct dw_eth_dev *priv) for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; - desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE]; - desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; + desc_p->dmamac_addr = dev_phys_to_bus(priv->dev, + (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE]); + desc_p->dmamac_next = dev_phys_to_bus(priv->dev, + (ulong)&desc_table_p[idx + 1]); desc_p->dmamac_cntl = (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | @@ -291,14 +297,15 @@ static void rx_descs_init(struct dw_eth_dev *priv) } /* Correcting the last pointer of the chain */ - desc_p->dmamac_next = (ulong)&desc_table_p[0]; + desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]); /* Flush all Rx buffer descriptors at once */ flush_dcache_range((ulong)priv->rx_mac_descrtable, (ulong)priv->rx_mac_descrtable + sizeof(priv->rx_mac_descrtable)); - writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); + writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]), + &dma_p->rxdesclistaddr); priv->rx_currdescnum = 0; } @@ -448,7 +455,7 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) ulong desc_start = (ulong)desc_p; ulong desc_end = desc_start + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); - ulong data_start = desc_p->dmamac_addr; + ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr); ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); /* * Strictly we only need to invalidate the "txrx_status" field @@ -515,7 +522,7 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) ulong desc_start = (ulong)desc_p; ulong desc_end = desc_start + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); - ulong data_start = desc_p->dmamac_addr; + ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr); ulong data_end; /* Invalidate entire buffer descriptor */ @@ -532,7 +539,8 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) /* Invalidate received data */ data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); invalidate_dcache_range(data_start, data_end); - *packetp = (uchar *)(ulong)desc_p->dmamac_addr; + *packetp = (uchar *)(ulong)dev_bus_to_phys(priv->dev, + desc_p->dmamac_addr); } return length; @@ -757,6 +765,7 @@ int designware_eth_probe(struct udevice *dev) goto mdio_err; } priv->bus = miiphy_get_dev_by_name(dev->name); + priv->dev = dev; ret = dw_phy_init(priv, dev); debug("%s, ret=%d\n", __func__, ret); diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 9da4e902cb0d..918a38615ad6 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -241,6 +241,7 @@ struct dw_eth_dev { int clock_count; /* number of clock in clock list */ #endif + struct udevice *dev; struct phy_device *phydev; struct mii_dev *bus; }; -- 2.42.0

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[PATCH] net: e1000: Drop e1000_eth_ids[]
by Bin Meng 06 Nov '23

06 Nov '23

e1000_eth_ids holds compatible strings for e1000 devices, but it is meaningless as e1000 is a PCI device and there is no such compatible string assigned to e1000 by the DT bindings community. Drop it. Signed-off-by: Bin Meng <bmeng(a)tinylab.org> --- drivers/net/e1000.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 41e6ba760e..84a2a7cf90 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -5718,15 +5718,9 @@ static const struct eth_ops e1000_eth_ops = { .write_hwaddr = e1000_write_hwaddr, }; -static const struct udevice_id e1000_eth_ids[] = { - { .compatible = "intel,e1000" }, - { } -}; - U_BOOT_DRIVER(eth_e1000) = { .name = "eth_e1000", .id = UCLASS_ETH, - .of_match = e1000_eth_ids, .bind = e1000_eth_bind, .probe = e1000_eth_probe, .ops = &e1000_eth_ops, -- 2.34.1

3 2

[PATCH] net: Add option for tracing packets
by Sean Anderson 06 Nov '23

06 Nov '23

Add an option to trace all packets send/received. This can be helpful when debugging protocol issues, as the packets can then be imported into wireshark [1] and analyzed further. [1] https://www.wireshark.org/docs/wsug_html_chunked/ChIOImportSection.html Signed-off-by: Sean Anderson <seanga2(a)gmail.com> --- include/net.h | 4 ++++ net/net.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/include/net.h b/include/net.h index e254df7d7f4..e63a946002d 100644 --- a/include/net.h +++ b/include/net.h @@ -16,6 +16,7 @@ #include <asm/cache.h> #include <asm/byteorder.h> /* for nton* / ntoh* stuff */ #include <env.h> +#include <hexdump.h> #include <log.h> #include <time.h> #include <linux/if_ether.h> @@ -29,6 +30,7 @@ struct udevice; #define DEBUG_DEV_PKT 0 /* Packets or info directed to the device */ #define DEBUG_NET_PKT 0 /* Packets on info on the network at large */ #define DEBUG_INT_STATE 0 /* Internal network state changes */ +#define DEBUG_NET_PKT_TRACE 0 /* Trace all packet data */ /* * The number of receive packet buffers, and the required packet buffer @@ -640,6 +642,8 @@ uchar * net_get_async_tx_pkt_buf(void); /* Transmit a packet */ static inline void net_send_packet(uchar *pkt, int len) { + if (DEBUG_NET_PKT_TRACE) + print_hex_dump_bytes("tx: ", DUMP_PREFIX_OFFSET, pkt, len); /* Currently no way to return errors from eth_send() */ (void) eth_send(pkt, len); } diff --git a/net/net.c b/net/net.c index 43abbac7c32..53eb9ef1324 100644 --- a/net/net.c +++ b/net/net.c @@ -1201,6 +1201,9 @@ void net_process_received_packet(uchar *in_packet, int len) ushort cti = 0, vlanid = VLAN_NONE, myvlanid, mynvlanid; debug_cond(DEBUG_NET_PKT, "packet received\n"); + if (DEBUG_NET_PKT_TRACE) + print_hex_dump_bytes("rx: ", DUMP_PREFIX_OFFSET, in_packet, + len); #if defined(CONFIG_CMD_PCAP) pcap_post(in_packet, len, false); -- 2.37.1

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[PATCH] net: phy: TI DP83869 fix invalid clock delay configuration
by Frank de Brabander 06 Nov '23

06 Nov '23

Setting the clock delay from the device tree settings rx-internal-delay-ps and tx-internal-delay-ps was broken: - The expected value in the device tree is suppose to be a delay in picoseconds, but the driver only allowed an array index. - Driver converted this array index to the actual delay in picoseconds and tried to apply this in the device register. This however is not a valid register value. The actual logic here was reversed, it converted an register representation of the delay to the device tree delay in picoseconds. Only when the internal delays were NOT configured in the device tree and they default value of 7 (=2000ps) was used, a valid value was loaded in the register. Signed-off-by: Frank de Brabander <debrabander(a)gmail.com> --- drivers/net/phy/dp83869.c | 53 +++++++++++++++++++++++---------------- 1 file changed, 32 insertions(+), 21 deletions(-) diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index 8d32d73b07..f9d4782580 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -81,7 +81,10 @@ /* RGMIIDCTL bits */ #define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 -#define DP83869_CLK_DELAY_DEF 7 +#define DP83869_CLK_DELAY_STEP 250 +#define DP83869_CLK_DELAY_MIN 250 +#define DP83869_CLK_DELAY_MAX 4000 +#define DP83869_CLK_DELAY_DEFAULT 2000 /* CFG2 bits */ #define MII_DP83869_CFG2_SPEEDOPT_10EN 0x0040 @@ -157,10 +160,6 @@ static int dp83869_config_port_mirroring(struct phy_device *phydev) return 0; } -static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, - 1750, 2000, 2250, 2500, 2750, 3000, - 3250, 3500, 3750, 4000}; - static int dp83869_set_strapped_mode(struct phy_device *phydev) { struct dp83869_private *dp83869 = phydev->priv; @@ -183,7 +182,6 @@ static int dp83869_set_strapped_mode(struct phy_device *phydev) static int dp83869_of_init(struct phy_device *phydev) { struct dp83869_private * const dp83869 = phydev->priv; - const int delay_entries = ARRAY_SIZE(dp83869_internal_delay); int ret; ofnode node; @@ -238,32 +236,45 @@ static int dp83869_of_init(struct phy_device *phydev) dp83869->tx_fifo_depth = ofnode_read_s32_default(node, "tx-fifo-depth", DP83869_PHYCR_FIFO_DEPTH_4_B_NIB); + /* Internal clock delay values can be configured in steps of + * 250ps (0.25ns). The register field for clock delay is 4-bits wide, + * the values range from 0b0000 for 0.25ns to 0b1111 for 4ns. + */ + /* RX delay *must* be specified if internal delay of RX is used. */ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { - dp83869->rx_int_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", - DP83869_CLK_DELAY_DEF); - if (dp83869->rx_int_delay > delay_entries) { - dp83869->rx_int_delay = DP83869_CLK_DELAY_DEF; - pr_debug("rx-internal-delay-ps not set/invalid, default to %ups\n", - dp83869_internal_delay[dp83869->rx_int_delay]); + dp83869->rx_int_delay = ofnode_read_u32_default(node, + "rx-internal-delay-ps", DP83869_CLK_DELAY_DEFAULT); + if (dp83869->rx_int_delay > DP83869_CLK_DELAY_MAX || + dp83869->rx_int_delay < DP83869_CLK_DELAY_MIN || + dp83869->rx_int_delay % DP83869_CLK_DELAY_STEP) { + dp83869->rx_int_delay = DP83869_CLK_DELAY_DEFAULT; + pr_warn("rx-internal-delay-ps not set/invalid, default" + " to %ups\n", DP83869_CLK_DELAY_DEFAULT); } - dp83869->rx_int_delay = dp83869_internal_delay[dp83869->rx_int_delay]; + dp83869->rx_int_delay = + (dp83869->rx_int_delay - DP83869_CLK_DELAY_STEP) + / DP83869_CLK_DELAY_STEP; } - /* TX delay *must* be specified if internal delay of RX is used. */ + /* TX delay *must* be specified if internal delay of TX is used. */ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { - dp83869->tx_int_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", - DP83869_CLK_DELAY_DEF); - if (dp83869->tx_int_delay > delay_entries) { - dp83869->tx_int_delay = DP83869_CLK_DELAY_DEF; - pr_debug("tx-internal-delay-ps not set/invalid, default to %ups\n", - dp83869_internal_delay[dp83869->tx_int_delay]); + dp83869->tx_int_delay = ofnode_read_u32_default(node, + "tx-internal-delay-ps", DP83869_CLK_DELAY_DEFAULT); + if (dp83869->tx_int_delay > DP83869_CLK_DELAY_MAX || + dp83869->tx_int_delay < DP83869_CLK_DELAY_MIN || + dp83869->tx_int_delay % DP83869_CLK_DELAY_STEP) { + dp83869->tx_int_delay = DP83869_CLK_DELAY_DEFAULT; + pr_warn("tx-internal-delay-ps not set/invalid, default" + " to %ups\n", DP83869_CLK_DELAY_DEFAULT); } - dp83869->tx_int_delay = dp83869_internal_delay[dp83869->tx_int_delay]; + dp83869->tx_int_delay = + (dp83869->tx_int_delay - DP83869_CLK_DELAY_STEP) + / DP83869_CLK_DELAY_STEP; } return 0; -- 2.30.2

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[PATCH v2] net: eth-uclass: Setup ROM source only when ROM reading passes
by Michal Simek 06 Nov '23

06 Nov '23

There is no reason to setup ROM source if read_rom_hwaddr hook doesn't exist or reading mac address fails. It is ending up with confusion about mac address source. It is nicely visible if you put mac address to DT as local-mac-address = [ff ff ff ff ff ff]; but also save ethaddr to variables setenv -f ethaddr 02:18:31:7e:3e:01 Before this patch U-Boot prints that source is ROM Address in ROM is ff:ff:ff:ff:ff:ff Address in environment is 02:18:31:7e:3e:01 After that source is DT: Address in DT is ff:ff:ff:ff:ff:ff Address in environment is 02:18:31:7e:3e:01 Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- Changes in v2: - Fix commit message net/eth-uclass.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/net/eth-uclass.c b/net/eth-uclass.c index c393600fabcd..e40b869e1c31 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -588,10 +588,14 @@ static int eth_post_probe(struct udevice *dev) /* Check if the device has a valid MAC address in device tree */ if (!eth_dev_get_mac_address(dev, pdata->enetaddr) || !is_valid_ethaddr(pdata->enetaddr)) { - source = "ROM"; /* Check if the device has a MAC address in ROM */ - if (eth_get_ops(dev)->read_rom_hwaddr) - eth_get_ops(dev)->read_rom_hwaddr(dev); + if (eth_get_ops(dev)->read_rom_hwaddr) { + int ret; + + ret = eth_get_ops(dev)->read_rom_hwaddr(dev); + if (!ret) + source = "ROM"; + } } eth_env_get_enetaddr_by_index("eth", dev_seq(dev), env_enetaddr); -- 2.36.1

2 1

[PATCH RESEND v2 0/2] net: add support for HiSilicon Fast Ethernet Controller driver
by Yang Xiwen via B4 Relay 06 Nov '23

06 Nov '23

This core is found on many HiSilicon chips. This patchset adds support for it and the integrated MDIO bus. The driver code comes from linux kernel driver, downstream u-boot driver and the datasheet. It's already tested on a Hi3798MV200 based STB. Note that currently this driver can't be used for Hi3798MV200 since the clock driver is missing. I will implement and submit the clock driver and the framework in a later patchset. Signed-off-by: Yang Xiwen <forbidden405(a)outlook.com> --- Changes in v2: - hisi_femac: clear previous irq before sending - Link to v1: https://lore.kernel.org/r/20230725-wip-hisi_femac-trunk-v1-0-88469a170310@o… --- Yang Xiwen (2): net: add hifemac Ethernet driver for HiSilicon platform net: add hifemac_mdio MDIO bus driver for HiSilicon platform drivers/net/Kconfig | 17 ++ drivers/net/Makefile | 2 + drivers/net/hifemac.c | 481 +++++++++++++++++++++++++++++++++++++++++++++ drivers/net/hifemac_mdio.c | 116 +++++++++++ 4 files changed, 616 insertions(+) --- base-commit: 580eb31199be8a822e62f20965854a242f895d03 change-id: 20230724-wip-hisi_femac-trunk-1f57f0986f0c Best regards, -- Yang Xiwen <forbidden405(a)outlook.com>

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[PATCH 1/2] net: mv88e6xxx: use generic bitfield macros for MDIO
by Robert Marko 06 Nov '23

06 Nov '23

Driver is currently defining the mask and bit shifting itself, there is no need for that as U-Boot has generic bitfield macros that help us achieve the same result but in a cleaner way. Signed-off-by: Robert Marko <robert.marko(a)sartura.hr> --- drivers/net/mv88e6xxx.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/net/mv88e6xxx.c b/drivers/net/mv88e6xxx.c index 64e860e324d..deb72772d19 100644 --- a/drivers/net/mv88e6xxx.c +++ b/drivers/net/mv88e6xxx.c @@ -29,6 +29,7 @@ #include <dm/device-internal.h> #include <dm/lists.h> #include <dm/of_extra.h> +#include <linux/bitfield.h> #include <linux/delay.h> #include <miiphy.h> #include <net/dsa.h> @@ -110,20 +111,20 @@ */ #define SMI_BUSY BIT(15) #define SMI_CMD_CLAUSE_22 BIT(12) -#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10) -#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10) -#define SMI_CMD_ADDR_SHIFT 5 -#define SMI_CMD_ADDR_MASK 0x1f -#define SMI_CMD_REG_SHIFT 0 -#define SMI_CMD_REG_MASK 0x1f +#define SMI_CMD_OP_MASK GENMASK(11, 10) +#define SMI_CMD_CLAUSE_22_OP_WRITE 0x1 +#define SMI_CMD_CLAUSE_22_OP_READ 0x2 + +#define SMI_CMD_ADDR_MASK GENMASK(9, 5) +#define SMI_CMD_REG_MASK GENMASK(4, 0) #define SMI_CMD_READ(addr, reg) \ - (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_READ) | \ - (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \ - (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT) + (SMI_BUSY | SMI_CMD_CLAUSE_22 | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_22_OP_READ)) | \ + (FIELD_PREP(SMI_CMD_ADDR_MASK, addr)) | \ + (FIELD_PREP(SMI_CMD_REG_MASK, reg)) #define SMI_CMD_WRITE(addr, reg) \ - (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_WRITE) | \ - (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \ - (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT) + (SMI_BUSY | SMI_CMD_CLAUSE_22 | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_22_OP_WRITE)) | \ + (FIELD_PREP(SMI_CMD_ADDR_MASK, addr)) | \ + (FIELD_PREP(SMI_CMD_REG_MASK, reg)) /* ID register values for different switch models */ #define PORT_SWITCH_ID_6020 0x0200 -- 2.41.0

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