November 2023 - U-Boot

[PATCH 0/3] exynos: Include missing CPU headers
by Sam Protsenko 14 Nov '23

14 Nov '23

During porting a new Exynos-based board to U-Boot I faced a couple of similar build errors due to missing <asm/arch/cpu.h> inclusion. This series make sure it's fixed in all places I found. Sam Protsenko (3): arm: exynos: Include missing CPU header in soc.c arm: exynos: Include missing CPU header in gpio.h watchdog: s5p_wdt: Include missing CPU header arch/arm/mach-exynos/include/mach/gpio.h | 3 +++ arch/arm/mach-exynos/soc.c | 1 + drivers/watchdog/s5p_wdt.c | 1 + 3 files changed, 5 insertions(+) -- 2.39.2

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[PATCH] clk: meson: add Hardware Clock measure driver
by Neil Armstrong 14 Nov '23

14 Nov '23

Amlogic SoCs embeds an hardware clock measure block, port it from Linux and implement it as a UCLK_CLK with only the dump op and fail-only xlate. Signed-off-by: Neil Armstrong <neil.armstrong(a)linaro.org> --- drivers/clk/meson/Kconfig | 9 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-measure.c | 634 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 644 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index cdc9d6f76c..da097ae7b8 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -29,3 +29,12 @@ config CLK_MESON_A1 help Enable clock support for the Amlogic A1 SoC family, such as the A113L + +config CLK_MESON_MSR + bool "Enable clock measure driver for Amlogic SoCs" + depends on CLK && ARCH_MESON + depends on CMD_CLK + default ARCH_MESON + help + Enable clock support for the Hardware Clock Measure for various + Amlogic SoCs. diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index d975f07aab..c7a446e86c 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK_MESON_AXG) += axg-ao.o obj-$(CONFIG_CLK_MESON_G12A) += g12a.o obj-$(CONFIG_CLK_MESON_G12A) += g12a-ao.o obj-$(CONFIG_CLK_MESON_A1) += a1.o +obj-$(CONFIG_CLK_MESON_MSR) += clk-measure.o diff --git a/drivers/clk/meson/clk-measure.c b/drivers/clk/meson/clk-measure.c new file mode 100644 index 0000000000..abb038647a --- /dev/null +++ b/drivers/clk/meson/clk-measure.c @@ -0,0 +1,634 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Based on Linux driver from: + * (C) Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong <narmstrong(a)baylibre.com> + * (C) Copyright 2023 - Neil Armstrong <neil.armstrong(a)linaro.org> + */ + +#include <common.h> +#include <log.h> +#include <clk-uclass.h> +#include <div64.h> +#include <dm.h> +#include <regmap.h> +#include <syscon.h> +#include <linux/bitops.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/kernel.h> + +#define MSR_CLK_DUTY 0x0 +#define MSR_CLK_REG0 0x4 +#define MSR_CLK_REG1 0x8 +#define MSR_CLK_REG2 0xc + +#define MSR_DURATION GENMASK(15, 0) +#define MSR_ENABLE BIT(16) +#define MSR_CONT BIT(17) /* continuous measurement */ +#define MSR_INTR BIT(18) /* interrupts */ +#define MSR_RUN BIT(19) +#define MSR_CLK_SRC GENMASK(26, 20) +#define MSR_BUSY BIT(31) + +#define MSR_VAL_MASK GENMASK(15, 0) + +#define DIV_MIN 32 +#define DIV_STEP 32 +#define DIV_MAX 640 + +#define CLK_MSR_MAX 128 + +struct meson_msr_id { + unsigned int id; + const char *name; +}; + +struct meson_msr { + struct regmap *regmap; + struct meson_msr_id *msr_table; +}; + +#define CLK_MSR_ID(__id, __name) \ + [__id] = {.id = __id, .name = __name,} + +static struct meson_msr_id clk_msr_m8[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee0"), + CLK_MSR_ID(1, "ring_osc_out_ee1"), + CLK_MSR_ID(2, "ring_osc_out_ee2"), + CLK_MSR_ID(3, "a9_ring_osck"), + CLK_MSR_ID(6, "vid_pll"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(11, "eth_rmii"), + CLK_MSR_ID(13, "amclk"), + CLK_MSR_ID(14, "fec_clk_0"), + CLK_MSR_ID(15, "fec_clk_1"), + CLK_MSR_ID(16, "fec_clk_2"), + CLK_MSR_ID(18, "a9_clk_div16"), + CLK_MSR_ID(19, "hdmi_sys"), + CLK_MSR_ID(20, "rtc_osc_clk_out"), + CLK_MSR_ID(21, "i2s_clk_in_src0"), + CLK_MSR_ID(22, "clk_rmii_from_pad"), + CLK_MSR_ID(23, "hdmi_ch0_tmds"), + CLK_MSR_ID(24, "lvds_fifo"), + CLK_MSR_ID(26, "sc_clk_int"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(30, "mpll_clk_test_out"), + CLK_MSR_ID(31, "audac_clkpi"), + CLK_MSR_ID(32, "vdac"), + CLK_MSR_ID(33, "sdhc_rx"), + CLK_MSR_ID(34, "sdhc_sd"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "pcm_sclk"), + CLK_MSR_ID(40, "pcm_mclk"), + CLK_MSR_ID(41, "eth_rx_tx"), + CLK_MSR_ID(42, "pwm_d"), + CLK_MSR_ID(43, "pwm_c"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "pcm2_sclk"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "pwm_f"), + CLK_MSR_ID(49, "pwm_e"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(60, "usb_32k_alt"), + CLK_MSR_ID(61, "gpio"), + CLK_MSR_ID(62, "vid2_pll"), + CLK_MSR_ID(63, "mipi_csi_cfg"), +}; + +static struct meson_msr_id clk_msr_gx[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "a53_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(6, "enci"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(10, "vdac"), + CLK_MSR_ID(11, "rgmii_tx"), + CLK_MSR_ID(12, "pdm"), + CLK_MSR_ID(13, "amclk"), + CLK_MSR_ID(14, "fec_0"), + CLK_MSR_ID(15, "fec_1"), + CLK_MSR_ID(16, "fec_2"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(19, "hdmitx_sys"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(21, "i2s_in_src0"), + CLK_MSR_ID(22, "eth_phy_ref"), + CLK_MSR_ID(23, "hdmi_todig"), + CLK_MSR_ID(26, "sc_int"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(32, "vdec"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(37, "i958"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "pcm_sclk"), + CLK_MSR_ID(40, "pcm_mclk"), + CLK_MSR_ID(41, "eth_rx_or_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "nand_core"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(53, "sd_emmc_a"), + CLK_MSR_ID(55, "vid_pll_div_out"), + CLK_MSR_ID(56, "cci"), + CLK_MSR_ID(57, "wave420l_c"), + CLK_MSR_ID(58, "wave420l_b"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(60, "alt_32k"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(62, "hevc"), + CLK_MSR_ID(66, "vid_lock"), + CLK_MSR_ID(70, "pwm_f"), + CLK_MSR_ID(71, "pwm_e"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(75, "aoclkx2_int"), + CLK_MSR_ID(76, "aoclk_int"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), +}; + +static struct meson_msr_id clk_msr_axg[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "a53_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(5, "gp1_pll"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(23, "mmc_clk"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(40, "mod_eth_tx_clk"), + CLK_MSR_ID(41, "mod_eth_rx_clk_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmm_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(66, "audio_slv_lrclk_c"), + CLK_MSR_ID(67, "audio_slv_lrclk_b"), + CLK_MSR_ID(68, "audio_slv_lrclk_a"), + CLK_MSR_ID(69, "audio_slv_sclk_c"), + CLK_MSR_ID(70, "audio_slv_sclk_b"), + CLK_MSR_ID(71, "audio_slv_sclk_a"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(74, "wifi_beacon"), + CLK_MSR_ID(75, "tdmin_lb_lrcl"), + CLK_MSR_ID(76, "tdmin_lb_sclk"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(84, "audio_resample"), + CLK_MSR_ID(85, "audio_pdm_sys"), + CLK_MSR_ID(86, "audio_spdifout"), + CLK_MSR_ID(87, "audio_spdifin"), + CLK_MSR_ID(88, "audio_lrclk_f"), + CLK_MSR_ID(89, "audio_lrclk_e"), + CLK_MSR_ID(90, "audio_lrclk_d"), + CLK_MSR_ID(91, "audio_lrclk_c"), + CLK_MSR_ID(92, "audio_lrclk_b"), + CLK_MSR_ID(93, "audio_lrclk_a"), + CLK_MSR_ID(94, "audio_sclk_f"), + CLK_MSR_ID(95, "audio_sclk_e"), + CLK_MSR_ID(96, "audio_sclk_d"), + CLK_MSR_ID(97, "audio_sclk_c"), + CLK_MSR_ID(98, "audio_sclk_b"), + CLK_MSR_ID(99, "audio_sclk_a"), + CLK_MSR_ID(100, "audio_mclk_f"), + CLK_MSR_ID(101, "audio_mclk_e"), + CLK_MSR_ID(102, "audio_mclk_d"), + CLK_MSR_ID(103, "audio_mclk_c"), + CLK_MSR_ID(104, "audio_mclk_b"), + CLK_MSR_ID(105, "audio_mclk_a"), + CLK_MSR_ID(106, "pcie_refclk_n"), + CLK_MSR_ID(107, "pcie_refclk_p"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), +}; + +static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "sys_cpu_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(6, "enci"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(10, "vdac"), + CLK_MSR_ID(11, "eth_tx"), + CLK_MSR_ID(12, "hifi_pll"), + CLK_MSR_ID(13, "mod_tcon"), + CLK_MSR_ID(14, "fec_0"), + CLK_MSR_ID(15, "fec_1"), + CLK_MSR_ID(16, "fec_2"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(19, "lcd_an_ph2"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(21, "lcd_an_ph3"), + CLK_MSR_ID(22, "eth_phy_ref"), + CLK_MSR_ID(23, "mpll_50m"), + CLK_MSR_ID(24, "eth_125m"), + CLK_MSR_ID(25, "eth_rmii"), + CLK_MSR_ID(26, "sc_int"), + CLK_MSR_ID(27, "in_mac"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(29, "pcie_inp"), + CLK_MSR_ID(30, "pcie_inn"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(32, "vdec"), + CLK_MSR_ID(33, "sys_cpu_ring_osc_1"), + CLK_MSR_ID(34, "eth_mpll_50m"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(37, "cdac"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "bt656"), + CLK_MSR_ID(41, "eth_rx_or_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmc_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(53, "sd_emmc_a"), + CLK_MSR_ID(54, "vpu_clkc"), + CLK_MSR_ID(55, "vid_pll_div_out"), + CLK_MSR_ID(56, "wave420l_a"), + CLK_MSR_ID(57, "wave420l_c"), + CLK_MSR_ID(58, "wave420l_b"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(62, "hevcb"), + CLK_MSR_ID(63, "dsi_meas"), + CLK_MSR_ID(64, "spicc_1"), + CLK_MSR_ID(65, "spicc_0"), + CLK_MSR_ID(66, "vid_lock"), + CLK_MSR_ID(67, "dsi_phy"), + CLK_MSR_ID(68, "hdcp22_esm"), + CLK_MSR_ID(69, "hdcp22_skp"), + CLK_MSR_ID(70, "pwm_f"), + CLK_MSR_ID(71, "pwm_e"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(75, "hevcf"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(83, "co_rx"), + CLK_MSR_ID(84, "co_tx"), + CLK_MSR_ID(89, "hdmi_todig"), + CLK_MSR_ID(90, "hdmitx_sys"), + CLK_MSR_ID(91, "sys_cpub_div16"), + CLK_MSR_ID(92, "sys_pll_cpub_div16"), + CLK_MSR_ID(94, "eth_phy_rx"), + CLK_MSR_ID(95, "eth_phy_pll"), + CLK_MSR_ID(96, "vpu_b"), + CLK_MSR_ID(97, "cpu_b_tmp"), + CLK_MSR_ID(98, "ts"), + CLK_MSR_ID(99, "ring_osc_out_ee_3"), + CLK_MSR_ID(100, "ring_osc_out_ee_4"), + CLK_MSR_ID(101, "ring_osc_out_ee_5"), + CLK_MSR_ID(102, "ring_osc_out_ee_6"), + CLK_MSR_ID(103, "ring_osc_out_ee_7"), + CLK_MSR_ID(104, "ring_osc_out_ee_8"), + CLK_MSR_ID(105, "ring_osc_out_ee_9"), + CLK_MSR_ID(106, "ephy_test"), + CLK_MSR_ID(107, "au_dac_g128x"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), + CLK_MSR_ID(110, "audio_tdmout_c_sclk"), + CLK_MSR_ID(111, "audio_tdmout_b_sclk"), + CLK_MSR_ID(112, "audio_tdmout_a_sclk"), + CLK_MSR_ID(113, "audio_tdmin_lb_sclk"), + CLK_MSR_ID(114, "audio_tdmin_c_sclk"), + CLK_MSR_ID(115, "audio_tdmin_b_sclk"), + CLK_MSR_ID(116, "audio_tdmin_a_sclk"), + CLK_MSR_ID(117, "audio_resample"), + CLK_MSR_ID(118, "audio_pdm_sys"), + CLK_MSR_ID(119, "audio_spdifout_b"), + CLK_MSR_ID(120, "audio_spdifout"), + CLK_MSR_ID(121, "audio_spdifin"), + CLK_MSR_ID(122, "audio_pdm_dclk"), +}; + +static struct meson_msr_id clk_msr_sm1[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "ring_osc_out_ee_3"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(5, "gp1_pll"), + CLK_MSR_ID(6, "enci"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(10, "vdac"), + CLK_MSR_ID(11, "eth_tx"), + CLK_MSR_ID(12, "hifi_pll"), + CLK_MSR_ID(13, "mod_tcon"), + CLK_MSR_ID(14, "fec_0"), + CLK_MSR_ID(15, "fec_1"), + CLK_MSR_ID(16, "fec_2"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(19, "lcd_an_ph2"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(21, "lcd_an_ph3"), + CLK_MSR_ID(22, "eth_phy_ref"), + CLK_MSR_ID(23, "mpll_50m"), + CLK_MSR_ID(24, "eth_125m"), + CLK_MSR_ID(25, "eth_rmii"), + CLK_MSR_ID(26, "sc_int"), + CLK_MSR_ID(27, "in_mac"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(29, "pcie_inp"), + CLK_MSR_ID(30, "pcie_inn"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(32, "vdec"), + CLK_MSR_ID(34, "eth_mpll_50m"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(37, "cdac"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "bt656"), + CLK_MSR_ID(40, "arm_ring_osc_out_4"), + CLK_MSR_ID(41, "eth_rx_or_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmc_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(53, "sd_emmc_a"), + CLK_MSR_ID(54, "vpu_clkc"), + CLK_MSR_ID(55, "vid_pll_div_out"), + CLK_MSR_ID(56, "wave420l_a"), + CLK_MSR_ID(57, "wave420l_c"), + CLK_MSR_ID(58, "wave420l_b"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(60, "arm_ring_osc_out_5"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(62, "hevcb"), + CLK_MSR_ID(63, "dsi_meas"), + CLK_MSR_ID(64, "spicc_1"), + CLK_MSR_ID(65, "spicc_0"), + CLK_MSR_ID(66, "vid_lock"), + CLK_MSR_ID(67, "dsi_phy"), + CLK_MSR_ID(68, "hdcp22_esm"), + CLK_MSR_ID(69, "hdcp22_skp"), + CLK_MSR_ID(70, "pwm_f"), + CLK_MSR_ID(71, "pwm_e"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(74, "arm_ring_osc_out_6"), + CLK_MSR_ID(75, "hevcf"), + CLK_MSR_ID(76, "arm_ring_osc_out_7"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(83, "co_rx"), + CLK_MSR_ID(84, "co_tx"), + CLK_MSR_ID(85, "arm_ring_osc_out_8"), + CLK_MSR_ID(86, "arm_ring_osc_out_9"), + CLK_MSR_ID(87, "mipi_dsi_phy"), + CLK_MSR_ID(88, "cis2_adapt"), + CLK_MSR_ID(89, "hdmi_todig"), + CLK_MSR_ID(90, "hdmitx_sys"), + CLK_MSR_ID(91, "nna_core"), + CLK_MSR_ID(92, "nna_axi"), + CLK_MSR_ID(93, "vad"), + CLK_MSR_ID(94, "eth_phy_rx"), + CLK_MSR_ID(95, "eth_phy_pll"), + CLK_MSR_ID(96, "vpu_b"), + CLK_MSR_ID(97, "cpu_b_tmp"), + CLK_MSR_ID(98, "ts"), + CLK_MSR_ID(99, "arm_ring_osc_out_10"), + CLK_MSR_ID(100, "arm_ring_osc_out_11"), + CLK_MSR_ID(101, "arm_ring_osc_out_12"), + CLK_MSR_ID(102, "arm_ring_osc_out_13"), + CLK_MSR_ID(103, "arm_ring_osc_out_14"), + CLK_MSR_ID(104, "arm_ring_osc_out_15"), + CLK_MSR_ID(105, "arm_ring_osc_out_16"), + CLK_MSR_ID(106, "ephy_test"), + CLK_MSR_ID(107, "au_dac_g128x"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), + CLK_MSR_ID(110, "audio_tdmout_c_sclk"), + CLK_MSR_ID(111, "audio_tdmout_b_sclk"), + CLK_MSR_ID(112, "audio_tdmout_a_sclk"), + CLK_MSR_ID(113, "audio_tdmin_lb_sclk"), + CLK_MSR_ID(114, "audio_tdmin_c_sclk"), + CLK_MSR_ID(115, "audio_tdmin_b_sclk"), + CLK_MSR_ID(116, "audio_tdmin_a_sclk"), + CLK_MSR_ID(117, "audio_resample"), + CLK_MSR_ID(118, "audio_pdm_sys"), + CLK_MSR_ID(119, "audio_spdifout_b"), + CLK_MSR_ID(120, "audio_spdifout"), + CLK_MSR_ID(121, "audio_spdifin"), + CLK_MSR_ID(122, "audio_pdm_dclk"), + CLK_MSR_ID(123, "audio_resampled"), + CLK_MSR_ID(124, "earcrx_pll"), + CLK_MSR_ID(125, "earcrx_pll_test"), + CLK_MSR_ID(126, "csi_phy0"), + CLK_MSR_ID(127, "csi2_data"), +}; + +static int meson_clk_msr_measure_id(struct meson_msr *priv, unsigned int id, + unsigned int duration) +{ + unsigned int val; + int ret; + + regmap_write(priv->regmap, MSR_CLK_REG0, 0); + + /* Set measurement duration */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_DURATION, + FIELD_PREP(MSR_DURATION, duration - 1)); + + /* Set ID */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_CLK_SRC, + FIELD_PREP(MSR_CLK_SRC, id)); + + /* Enable & Start */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, + MSR_RUN | MSR_ENABLE, + MSR_RUN | MSR_ENABLE); + + ret = regmap_read_poll_timeout(priv->regmap, MSR_CLK_REG0, + val, !(val & MSR_BUSY), 10, 10000); + if (ret) + return ret; + + /* Disable */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_ENABLE, 0); + + /* Get the value in multiple of gate time counts */ + regmap_read(priv->regmap, MSR_CLK_REG2, &val); + + if (val >= MSR_VAL_MASK) + return -EINVAL; + + return DIV_ROUND_CLOSEST_ULL((val & MSR_VAL_MASK) * 1000000ULL, + duration); +} + +static int meson_clk_msr_best_id(struct meson_msr *priv, unsigned int id, + unsigned int *precision) +{ + unsigned int duration = DIV_MAX; + int ret; + + /* Start from max duration and down to min duration */ + do { + ret = meson_clk_msr_measure_id(priv, id, duration); + if (ret >= 0) + *precision = (2 * 1000000) / duration; + else + duration -= DIV_STEP; + } while (duration >= DIV_MIN && ret == -EINVAL); + + return ret; +} + +static void meson_clk_msr_dump(struct udevice *dev) +{ + struct meson_msr *priv = dev_get_priv(dev); + unsigned int precision = 0; + int val, i; + + printf(" clock rate precision\n"); + printf("---------------------------------------------\n"); + + for (i = 0 ; i < CLK_MSR_MAX ; ++i) { + if (!priv->msr_table[i].name) + continue; + + val = meson_clk_msr_best_id(priv, i, &precision); + if (val < 0) + return; + + printf(" %-20s %10d +/-%dHz\n", + priv->msr_table[i].name, val, precision); + } +} + +static int meson_clk_msr_xlate(struct clk *clk, struct ofnode_phandle_args *args) +{ + /* This driver doesn't expose any clocks */ + return -EINVAL; +} + +static int meson_clk_msr_probe(struct udevice *dev) +{ + struct meson_msr *priv = dev_get_priv(dev); + int ret; + + priv->msr_table = (struct meson_msr_id *)dev_get_driver_data(dev); + + ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap); + if (ret) + return ret; + + return 0; +} + +static struct clk_ops meson_clk_msr_ops = { + .of_xlate = meson_clk_msr_xlate, + .dump = meson_clk_msr_dump, +}; + +static const struct udevice_id meson_clk_msr_ids[] = { + { + .compatible = "amlogic,meson-gx-clk-measure", + .data = (ulong)clk_msr_gx, + }, + { + .compatible = "amlogic,meson8-clk-measure", + .data = (ulong)clk_msr_m8, + }, + { + .compatible = "amlogic,meson8b-clk-measure", + .data = (ulong)clk_msr_m8, + }, + { + .compatible = "amlogic,meson-axg-clk-measure", + .data = (ulong)clk_msr_axg, + }, + { + .compatible = "amlogic,meson-g12a-clk-measure", + .data = (ulong)clk_msr_g12a, + }, + { + .compatible = "amlogic,meson-sm1-clk-measure", + .data = (ulong)clk_msr_sm1, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(meson_clk_msr) = { + .name = "meson_clk_msr", + .id = UCLASS_CLK, + .of_match = meson_clk_msr_ids, + .priv_auto = sizeof(struct meson_msr), + .ops = &meson_clk_msr_ops, + .probe = meson_clk_msr_probe, +}; --- base-commit: 3221d10770b4c288ddb7d83350e1cd86c3b6ef55 change-id: 20231113-uboot-meson-clk-msr-21cf9101278b Best regards, -- Neil Armstrong <neil.armstrong(a)linaro.org>

2 2

[PATCH] mtd: rawnand: omap_gpmc: remove unneeded variable
by Heiko Schocher 14 Nov '23

14 Nov '23

remove unneeded variable ecc_flag in omap_correct_data_bch Signed-off-by: Heiko Schocher <hs(a)denx.de> --- azure build is fine with this patch: https://dev.azure.com/hs0298/hs/_build/results?buildId=110&view=results drivers/mtd/nand/raw/omap_gpmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 1a5ed0de31..1fe8b1671e 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -637,13 +637,13 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, uint32_t error_count = 0, error_max; uint32_t error_loc[ELM_MAX_ERROR_COUNT]; enum bch_level bch_type; - uint32_t i, ecc_flag = 0; + uint32_t i; uint8_t count; uint32_t byte_pos, bit_pos; int err = 0; /* check calculated ecc */ - for (i = 0; i < ecc->bytes && !ecc_flag; i++) { + for (i = 0; i < ecc->bytes; i++) { if (calc_ecc[i] != 0x00) goto not_ecc_match; } -- 2.37.3

2 1

[PATCH v2 0/5] cmd: add scmi command
by AKASHI Takahiro 14 Nov '23

14 Nov '23

"Scmi" command will be re-introduced per Michal's request. The functionality is the same as I put it in my patch set of adding SCMI base protocol support, but made some tweak to make UT, "ut dm scmi_cmd," more flexible and tolerable when enabling/disabling a specific SCMI protocol for test purpose. Each commit may have some change history inherited from the preceding patch series. Test ==== The patch series was tested on the following platforms: * sandbox Prerequisite: ============= * This patch series is based on the latest master. Changes: ======== v2(Nov 13, 2023) * localize global variables to avoid pytest errors. AKASHI Takahiro (5): test: dm: skip scmi tests against disabled protocols firmware: scmi: support protocols on sandbox only if enabled cmd: add scmi command for SCMI firmware doc: cmd: add documentation for scmi test: dm: add scmi command test cmd/Kconfig | 9 + cmd/Makefile | 1 + cmd/scmi.c | 384 +++++++++++++++++++ configs/sandbox_defconfig | 1 + doc/usage/cmd/scmi.rst | 126 ++++++ doc/usage/index.rst | 1 + drivers/firmware/scmi/sandbox-scmi_agent.c | 27 +- drivers/firmware/scmi/sandbox-scmi_devices.c | 78 ++-- test/dm/scmi.c | 93 +++++ 9 files changed, 687 insertions(+), 33 deletions(-) create mode 100644 cmd/scmi.c create mode 100644 doc/usage/cmd/scmi.rst -- 2.34.1

2 9

[PATCH v1 0/3] bootflow: bootmeth_efi: Fix network efi boot
by Shantur Rathore 14 Nov '23

14 Nov '23

Currently bootmeth_efi crashes while doing a network (dhcp) boot. This patch series fixes issues and both network and disk boot works. Shantur Rathore (3): bootflow: bootmeth_efi: Set bootp_arch as hex bootflow: bootmeth_efi: Don't set bootdev again bootflow: bootmeth_efi: Handle fdt not available. boot/bootmeth_efi.c | 15 ++++++++++----- include/bootflow.h | 1 + 2 files changed, 11 insertions(+), 5 deletions(-) -- 2.40.1

1 3

[PATCH v4 0/7] arm: mach-snapdragon: Qualcomm clock driver cleanup
by Caleb Connolly 14 Nov '23

14 Nov '23

This series begins making some headway towards cleaning up Qualcomm platform support in u-boot. The following is a rough overview of the changes: * Move the Qualcomm clock drivers out of mach-snapdragon and into clk/qcom * Introduce per-platform clock driver configs to decouple Qualcomm platform support from mach-snapdragon targets. * Add the IPQ4019 clock driver, removing it from mach-ipq40xx and introducing the reset map. * Merge the qcom reset driver is into clk/qcom and rework it to be compatible with upstream devicetrees. * A callback model is added so that multiple clock drivers can be compiled in at once. * SDM845 gains support for enabling/disabling all gate clocks (CBC's) by way of a new "gate_clk" abstraction. * Preperatory cleanup work is done to simplify the bringup process for new platforms. Further details are included in each commit. The primary goal of this series is to prepare for enabling several new Qualcomm platforms in u-boot as well as additional peripherals, while minimising the amount of copy/pasted board-specific code. This series conflicts with a previous series introducing support for the Qualcomm RB2 board [1], I plan to resend this initial support pending acceptance of this series and several other cleanups. [1]: https://lore.kernel.org/u-boot/20230324080418.3856409-1-bhupesh.sharma@lina… --- Changes in v4: * Fixed mnd_width for UART clock on apq8016, apq8096, and qcs404 * Link to v3: https://lore.kernel.org/r/20231103-b4-qcom-clk-v3-0-8d2d460ece84@linaro.org Changes in v3: * Rebased on qcom-next [1] * Dropped erroneous LOG_DEBUG define * Add drivers/clk/qcom to MAINTAINERS * Link to v2: https://lore.kernel.org/r/20231024-b4-qcom-clk-v2-0-6572bc2be690@linaro.org Changes in v2: * Added missing headers in clock-qcom.c for "fix rcg divider value" patch * Use writel() instead of setbits_le32() in "fix rcg divider value" patch to ensure that writes are propagated to hardware. * Adjust RCG configuration to be more similar to Linux * Remove sysmap headers and define macros directly in platform clock code. * avoid renaming msm_* to qcom_* for now * only add relevant gate_clks for sdm845 * Link to v1: https://lore.kernel.org/r/20231024-b4-qcom-clk-v1-0-9d96359b9a82@linaro.org [1]: https://source.denx.de/u-boot/custodians/u-boot-snapdragon --- Caleb Connolly (6): clk/qcom: move from mach-snapdragon clk/qcom: move ipq4019 driver from mach-ipq40xx clk/qcom: sdm845: add register map for simple gate clocks clk/qcom: use function pointers for enable and set_rate clk/qcom: add mnd_width to clk_rcg_set_rate_mnd() clk/qcom: fix rcg divider value Konrad Dybcio (1): clk/qcom: handle resets and clocks in one device MAINTAINERS | 1 + arch/arm/Kconfig | 2 + arch/arm/dts/qcom-ipq4019.dtsi | 14 +- arch/arm/dts/qcs404-evb.dts | 19 +- arch/arm/mach-ipq40xx/Makefile | 1 - arch/arm/mach-ipq40xx/clock-ipq4019.c | 88 ------ arch/arm/mach-snapdragon/Kconfig | 4 + arch/arm/mach-snapdragon/Makefile | 5 - arch/arm/mach-snapdragon/clock-sdm845.c | 98 ------- arch/arm/mach-snapdragon/clock-snapdragon.c | 181 ------------ arch/arm/mach-snapdragon/clock-snapdragon.h | 48 ---- .../mach-snapdragon/include/mach/sysmap-apq8016.h | 39 --- .../mach-snapdragon/include/mach/sysmap-apq8096.h | 37 --- .../mach-snapdragon/include/mach/sysmap-qcs404.h | 88 ------ .../mach-snapdragon/include/mach/sysmap-sdm845.h | 42 --- board/qualcomm/dragonboard820c/dragonboard820c.c | 6 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/qcom/Kconfig | 52 ++++ drivers/clk/qcom/Makefile | 10 + .../clk/qcom}/clock-apq8016.c | 60 +++- .../clk/qcom}/clock-apq8096.c | 56 +++- .../reset-qcom.c => clk/qcom/clock-ipq4019.c} | 160 ++++------- drivers/clk/qcom/clock-qcom.c | 307 +++++++++++++++++++++ drivers/clk/qcom/clock-qcom.h | 100 +++++++ .../clk/qcom}/clock-qcs404.c | 167 +++++++++-- drivers/clk/qcom/clock-sdm845.c | 187 +++++++++++++ drivers/reset/Kconfig | 7 - drivers/reset/Makefile | 1 - include/configs/dragonboard410c.h | 1 - include/configs/dragonboard820c.h | 1 - include/configs/dragonboard845c.h | 1 - include/configs/qcs404-evb.h | 1 - .../{qcom,ipq4019-gcc.h => qcom,gcc-ipq4019.h} | 73 +++++ include/dt-bindings/reset/qcom,ipq4019-reset.h | 92 ------ 35 files changed, 1053 insertions(+), 898 deletions(-) --- base-commit: b9221f7d86f9511ad2a816f589d41bc02dbcd6f8 // Caleb (they/them)

1 9

[PATCH] efi_loader: Fix UEFI variable error handling
by Weizhao Ouyang 13 Nov '23

13 Nov '23

Correct some UEFI variable error handing code paths. Signed-off-by: Weizhao Ouyang <o451686892(a)gmail.com> --- lib/efi_loader/efi_var_file.c | 1 + lib/efi_loader/efi_variable.c | 8 ++++---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c index 62e071bd83..dbb9b1f3fc 100644 --- a/lib/efi_loader/efi_var_file.c +++ b/lib/efi_loader/efi_var_file.c @@ -236,6 +236,7 @@ efi_status_t efi_var_from_file(void) log_err("Invalid EFI variables file\n"); error: free(buf); + return ret; #endif return EFI_SUCCESS; } diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index be95ed44e6..13966297c6 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -350,17 +350,17 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, if (var_type == EFI_AUTH_VAR_PK) ret = efi_init_secure_state(); - else - ret = EFI_SUCCESS; + if (ret != EFI_SUCCESS) + return ret; /* * Write non-volatile EFI variables to file * TODO: check if a value change has occured to avoid superfluous writes */ if (attributes & EFI_VARIABLE_NON_VOLATILE) - efi_var_to_file(); + ret = efi_var_to_file(); - return EFI_SUCCESS; + return ret; } efi_status_t efi_query_variable_info_int(u32 attributes, -- 2.39.2

3 6

[PATCH] efi_loader: Clean up efi_dp_append and efi_dp_concat
by Ilias Apalodimas 13 Nov '23

13 Nov '23

Looking back at the initrd storing functionality, we introduced three functions, efi_dp_append_or_concatenate(), efi_dp_append/concat(). In hindsight we could have simplified that by a lot. First of all none of the functions append anything. They all allocate a new device path and concatenate the contents of two device paths in one. A boolean parameter controls the final device path -- if that's true an end node is injected between the two device paths. So let's rewrite this and make it a bit easier to read. Get rid of efi_dp_append(), efi_dp_concat() and rename efi_dp_append_or_concatenate() to efi_dp_concat(). This is far more intuitive and the only adjustment that is needed is an extra boolean argument on all callsites. Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- Kojima-san, I think this might affect your EFI HTTP boot series. I don't mind waiting for this and merging it after your series goes in (and adjust it). The changes should be trivial anyway cmd/bootefi.c | 4 +- cmd/eficonfig.c | 7 ++- cmd/efidebug.c | 6 +- include/efi_loader.h | 5 +- lib/efi_loader/efi_bootmgr.c | 2 +- lib/efi_loader/efi_boottime.c | 2 +- lib/efi_loader/efi_device_path.c | 66 ++++++---------------- lib/efi_loader/efi_device_path_utilities.c | 2 +- 8 files changed, 32 insertions(+), 62 deletions(-) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 20e5c94a33a4..eb839136bf7e 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -513,8 +513,8 @@ efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size) goto out; msg_path = file_path; } else { - file_path = efi_dp_append(bootefi_device_path, - bootefi_image_path); + file_path = efi_dp_concat(bootefi_device_path, + bootefi_image_path, false); msg_path = bootefi_image_path; log_debug("Loaded from disk\n"); } diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c index e6e8a0a488e7..470adb7eddbf 100644 --- a/cmd/eficonfig.c +++ b/cmd/eficonfig.c @@ -528,7 +528,7 @@ struct efi_device_path *eficonfig_create_device_path(struct efi_device_path *dp_ p += fp_size; *((struct efi_device_path *)p) = END; - dp = efi_dp_append(dp_volume, (struct efi_device_path *)buf); + dp = efi_dp_concat(dp_volume, (struct efi_device_path *)buf, false); free(buf); return dp; @@ -1481,7 +1481,8 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo ret = EFI_OUT_OF_RESOURCES; goto out; } - initrd_dp = efi_dp_append((const struct efi_device_path *)&id_dp, dp); + initrd_dp = efi_dp_concat((const struct efi_device_path *)&id_dp, + dp, false); efi_free_pool(dp); } @@ -1492,7 +1493,7 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo } final_dp_size = efi_dp_size(dp) + sizeof(END); if (initrd_dp) { - final_dp = efi_dp_concat(dp, initrd_dp); + final_dp = efi_dp_concat(dp, initrd_dp, true); final_dp_size += efi_dp_size(initrd_dp) + sizeof(END); } else { final_dp = efi_dp_dup(dp); diff --git a/cmd/efidebug.c b/cmd/efidebug.c index 201531ac19fc..a62298bf5987 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -698,8 +698,8 @@ struct efi_device_path *create_initrd_dp(const char *dev, const char *part, if (!short_fp) short_fp = tmp_fp; - initrd_dp = efi_dp_append((const struct efi_device_path *)&id_dp, - short_fp); + initrd_dp = efi_dp_concat((const struct efi_device_path *)&id_dp, + short_fp, false); out: efi_free_pool(tmp_dp); @@ -841,7 +841,7 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, goto out; } - final_fp = efi_dp_concat(file_path, initrd_dp); + final_fp = efi_dp_concat(file_path, initrd_dp, true); if (!final_fp) { printf("Cannot create final device path\n"); r = CMD_RET_FAILURE; diff --git a/include/efi_loader.h b/include/efi_loader.h index e24410505f40..398cd20c7ae6 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -808,8 +808,6 @@ efi_uintn_t efi_dp_instance_size(const struct efi_device_path *dp); /* size of multi-instance device path excluding end node */ efi_uintn_t efi_dp_size(const struct efi_device_path *dp); struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp); -struct efi_device_path *efi_dp_append(const struct efi_device_path *dp1, - const struct efi_device_path *dp2); struct efi_device_path *efi_dp_append_node(const struct efi_device_path *dp, const struct efi_device_path *node); /* Create a device path node of given type, sub-type, length */ @@ -928,7 +926,8 @@ struct efi_load_option { struct efi_device_path *efi_dp_from_lo(struct efi_load_option *lo, const efi_guid_t *guid); struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1, - const struct efi_device_path *dp2); + const struct efi_device_path *dp2, + bool split_end_node); struct efi_device_path *search_gpt_dp_node(struct efi_device_path *device_path); efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8 *data, efi_uintn_t *size); diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index a40762c74c83..646c7c7faaad 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -110,7 +110,7 @@ static efi_status_t try_load_from_file_path(efi_handle_t *fs_handles, if (!dp) continue; - dp = efi_dp_append(dp, fp); + dp = efi_dp_concat(dp, fp, false); if (!dp) continue; diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 0b7579cb5af1..709ea07655c2 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -1821,7 +1821,7 @@ efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path, if (device_path) { info->device_handle = efi_dp_find_obj(device_path, NULL, NULL); - dp = efi_dp_append(device_path, file_path); + dp = efi_dp_concat(device_path, file_path, false); if (!dp) { ret = EFI_OUT_OF_RESOURCES; goto failure; diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index ed7214f3a347..ad79b65843e9 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -272,30 +272,27 @@ struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp) } /** - * efi_dp_append_or_concatenate() - Append or concatenate two device paths. - * Concatenated device path will be separated - * by a sub-type 0xff end node + * efi_dp_concat() - Concatenate two device paths and add and terminate them + * with an end node. * - * @dp1: First device path - * @dp2: Second device path - * @concat: If true the two device paths will be concatenated and separated - * by an end of entrire device path sub-type 0xff end node. - * If true the second device path will be appended to the first and - * terminated by an end node + * @dp1: First device path + * @dp2: Second device path + * @split_end_node: If true the two device paths will be concatenated and + * separated by an end node. + * If false the second device path will be concatenated to the + * first one as-is. * * Return: * concatenated device path or NULL. Caller must free the returned value */ -static struct -efi_device_path *efi_dp_append_or_concatenate(const struct efi_device_path *dp1, - const struct efi_device_path *dp2, - bool concat) +struct +efi_device_path *efi_dp_concat(const struct efi_device_path *dp1, + const struct efi_device_path *dp2, + bool split_end_node) { struct efi_device_path *ret; size_t end_size = sizeof(END); - if (concat) - end_size = 2 * sizeof(END); if (!dp1 && !dp2) { /* return an end node */ ret = efi_dp_dup(&END); @@ -307,14 +304,18 @@ efi_device_path *efi_dp_append_or_concatenate(const struct efi_device_path *dp1, /* both dp1 and dp2 are non-null */ unsigned sz1 = efi_dp_size(dp1); unsigned sz2 = efi_dp_size(dp2); - void *p = efi_alloc(sz1 + sz2 + end_size); + void *p; + + if (split_end_node) + end_size = 2 * sizeof(END); + p = efi_alloc(sz1 + sz2 + end_size); if (!p) return NULL; ret = p; memcpy(p, dp1, sz1); p += sz1; - if (concat) { + if (split_end_node) { memcpy(p, &END, sizeof(END)); p += sizeof(END); } @@ -328,37 +329,6 @@ efi_device_path *efi_dp_append_or_concatenate(const struct efi_device_path *dp1, return ret; } -/** - * efi_dp_append() - Append a device to an existing device path. - * - * @dp1: First device path - * @dp2: Second device path - * - * Return: - * concatenated device path or NULL. Caller must free the returned value - */ -struct efi_device_path *efi_dp_append(const struct efi_device_path *dp1, - const struct efi_device_path *dp2) -{ - return efi_dp_append_or_concatenate(dp1, dp2, false); -} - -/** - * efi_dp_concat() - Concatenate 2 device paths. The final device path will - * contain two device paths separated by and end node (0xff). - * - * @dp1: First device path - * @dp2: Second device path - * - * Return: - * concatenated device path or NULL. Caller must free the returned value - */ -struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1, - const struct efi_device_path *dp2) -{ - return efi_dp_append_or_concatenate(dp1, dp2, true); -} - struct efi_device_path *efi_dp_append_node(const struct efi_device_path *dp, const struct efi_device_path *node) { diff --git a/lib/efi_loader/efi_device_path_utilities.c b/lib/efi_loader/efi_device_path_utilities.c index a07d9bab3a3c..fa211aee495e 100644 --- a/lib/efi_loader/efi_device_path_utilities.c +++ b/lib/efi_loader/efi_device_path_utilities.c @@ -77,7 +77,7 @@ static struct efi_device_path * EFIAPI append_device_path( const struct efi_device_path *src2) { EFI_ENTRY("%pD, %pD", src1, src2); - return EFI_EXIT(efi_dp_append(src1, src2)); + return EFI_EXIT(efi_dp_concat(src1, src2, false)); } /* -- 2.40.1

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[PULL] Pull request for u-boot next / v2024.04 = u-boot-stm32-20231113
by Patrice CHOTARD 13 Nov '23

13 Nov '23

Hi Tom Please pull the STM32 related patches for u-boot/next, v2024.04: u-boot-stm32-20231113 CI status: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/18567 The following changes since commit 3b6db6901ff5babbb9d21f0fca750996e29d85e0: Merge branch '2023-11-10-improve-semihosting-armv6' into next (2023-11-10 12:52:33 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-stm.git tags/u-boot-stm32-20231113 for you to fetch changes up to 01a701994b0590b6452516a7c67353359d053c94: stm32mp2: initial support (2023-11-13 10:55:38 +0100) ---------------------------------------------------------------- Introduce STM32MP2 SoCs family support Add STM32MP257F-EV1 board ---------------------------------------------------------------- Patrice Chotard (8): arm: caches: Make DCACHE_DEFAULT_OPTION accessible for ARM64 arch stm32mp: dram_init: Get RAM size from DT if no RAM driver found stm32mp: dram_init: Limit DDR usage under 4GB boundary for STM32MP stm32mp: bsec: Fix AARCH64 compilation warnings serial: stm32: Fix AARCH64 compilation warnings pinctrl: pinctrl_stm32: Add stm32mp2 support ARM: dts: stm32: Add STM32MP257F Evaluation board support stm32mp2: initial support Patrick Delaunay (1): stm32mp: dram_init: Fix AARCH64 compilation warnings arch/arm/Kconfig | 2 +- arch/arm/dts/Makefile | 3 +++ arch/arm/dts/stm32mp25-pinctrl.dtsi | 38 +++++++++++++++++++++++++++++++++++ arch/arm/dts/stm32mp25-u-boot.dtsi | 102 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/stm32mp251.dtsi | 285 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/stm32mp253.dtsi | 23 ++++++++++++++++++++++ arch/arm/dts/stm32mp255.dtsi | 9 +++++++++ arch/arm/dts/stm32mp257.dtsi | 9 +++++++++ arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi | 20 +++++++++++++++++++ arch/arm/dts/stm32mp257f-ev1.dts | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/stm32mp25xc.dtsi | 8 ++++++++ arch/arm/dts/stm32mp25xf.dtsi | 8 ++++++++ arch/arm/dts/stm32mp25xxai-pinctrl.dtsi | 83 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/stm32mp25xxak-pinctrl.dtsi | 71 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/stm32mp25xxal-pinctrl.dtsi | 71 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/system.h | 16 +++++++-------- arch/arm/mach-stm32mp/Kconfig | 26 +++++++++++++++++++++++- arch/arm/mach-stm32mp/Kconfig.25x | 43 ++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-stm32mp/Makefile | 15 ++++---------- arch/arm/mach-stm32mp/bsec.c | 29 ++++++++++++++------------- arch/arm/mach-stm32mp/dram_init.c | 17 ++++++++++++---- arch/arm/mach-stm32mp/include/mach/stm32.h | 141 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------------------------------------------- arch/arm/mach-stm32mp/include/mach/sys_proto.h | 26 ++++++++++++++++++++++++ arch/arm/mach-stm32mp/stm32mp1/Makefile | 20 +++++++++++++++++++ arch/arm/mach-stm32mp/{ => stm32mp1}/cpu.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/fdt.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/psci.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/pwr_regulator.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/spl.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/stm32mp13x.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/stm32mp15x.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/tzc400.c | 0 arch/arm/mach-stm32mp/stm32mp2/Makefile | 9 +++++++++ arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-stm32mp/stm32mp2/cpu.c | 108 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-stm32mp/stm32mp2/fdt.c | 16 +++++++++++++++ arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c | 194 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-stm32mp/syscon.c | 4 ++-- board/st/stm32mp2/Kconfig | 13 ++++++++++++ board/st/stm32mp2/MAINTAINERS | 9 +++++++++ board/st/stm32mp2/Makefile | 6 ++++++ board/st/stm32mp2/stm32mp2.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++ configs/stm32mp25_defconfig | 52 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/pinctrl/pinctrl_stm32.c | 2 ++ drivers/serial/serial_stm32.c | 23 ++++++++++++---------- drivers/serial/serial_stm32.h | 2 +- include/configs/stm32mp25_common.h | 24 +++++++++++++++++++++++ include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 +++ 48 files changed, 1597 insertions(+), 108 deletions(-) create mode 100644 arch/arm/dts/stm32mp25-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp251.dtsi create mode 100644 arch/arm/dts/stm32mp253.dtsi create mode 100644 arch/arm/dts/stm32mp255.dtsi create mode 100644 arch/arm/dts/stm32mp257.dtsi create mode 100644 arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp257f-ev1.dts create mode 100644 arch/arm/dts/stm32mp25xc.dtsi create mode 100644 arch/arm/dts/stm32mp25xf.dtsi create mode 100644 arch/arm/dts/stm32mp25xxai-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25xxak-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25xxal-pinctrl.dtsi create mode 100644 arch/arm/mach-stm32mp/Kconfig.25x create mode 100644 arch/arm/mach-stm32mp/stm32mp1/Makefile rename arch/arm/mach-stm32mp/{ => stm32mp1}/cpu.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/fdt.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/psci.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/pwr_regulator.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/spl.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/stm32mp13x.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/stm32mp15x.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/tzc400.c (100%) create mode 100644 arch/arm/mach-stm32mp/stm32mp2/Makefile create mode 100644 arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/cpu.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/fdt.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c create mode 100644 board/st/stm32mp2/Kconfig create mode 100644 board/st/stm32mp2/MAINTAINERS create mode 100644 board/st/stm32mp2/Makefile create mode 100644 board/st/stm32mp2/stm32mp2.c create mode 100644 configs/stm32mp25_defconfig create mode 100644 include/configs/stm32mp25_common.h

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[PATCH v2] clk: nuvoton: add read only feature for clk driver
by Jim Liu 13 Nov '23

13 Nov '23

Add a flag to set ahb/apb/fiu clock divider as read-only It just protects the clock source and can't modify it in uboot. Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- Changes for v2: - add commit message --- drivers/clk/nuvoton/clk_npcm.c | 15 ++++++++++++--- drivers/clk/nuvoton/clk_npcm.h | 1 + drivers/clk/nuvoton/clk_npcm8xx.c | 12 ++++++------ 3 files changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/clk/nuvoton/clk_npcm.c b/drivers/clk/nuvoton/clk_npcm.c index 8d71f2a24b..18cb9cddbf 100644 --- a/drivers/clk/nuvoton/clk_npcm.c +++ b/drivers/clk/nuvoton/clk_npcm.c @@ -135,7 +135,7 @@ static u32 npcm_clk_get_div(struct clk *clk) return div; } -static u32 npcm_clk_set_div(struct clk *clk, u32 div) +static int npcm_clk_set_div(struct clk *clk, u32 div) { struct npcm_clk_priv *priv = dev_get_priv(clk->dev); struct npcm_clk_div *divider; @@ -145,6 +145,9 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div) if (!divider) return -EINVAL; + if (divider->flags & DIV_RO) + return 0; + if (divider->flags & PRE_DIV2) div = div >> 1; @@ -153,6 +156,12 @@ static u32 npcm_clk_set_div(struct clk *clk, u32 div) else clkdiv = ilog2(div); + if (clkdiv > (divider->mask >> (ffs(divider->mask) - 1))) { + printf("clkdiv(%d) for clk(%ld) is over limit\n", + clkdiv, clk->id); + return -EINVAL; + } + val = readl(priv->base + divider->reg); val &= ~divider->mask; val |= (clkdiv << (ffs(divider->mask) - 1)) & divider->mask; @@ -253,8 +262,8 @@ static ulong npcm_clk_set_rate(struct clk *clk, ulong rate) if (ret) return ret; - debug("%s: rate %lu, new rate (%lu / %u)\n", __func__, rate, parent_rate, div); - return (parent_rate / div); + debug("%s: rate %lu, new rate %lu\n", __func__, rate, npcm_clk_get_rate(clk)); + return npcm_clk_get_rate(clk); } static int npcm_clk_set_parent(struct clk *clk, struct clk *parent) diff --git a/drivers/clk/nuvoton/clk_npcm.h b/drivers/clk/nuvoton/clk_npcm.h index 06b60dc8b8..b4726d8381 100644 --- a/drivers/clk/nuvoton/clk_npcm.h +++ b/drivers/clk/nuvoton/clk_npcm.h @@ -50,6 +50,7 @@ #define PRE_DIV2 BIT(2) /* Pre divisor = 2 */ #define POST_DIV2 BIT(3) /* Post divisor = 2 */ #define FIXED_PARENT BIT(4) /* clock source is fixed */ +#define DIV_RO BIT(5) /* divider is read-only */ /* Parameters of PLL configuration */ struct npcm_clk_pll { diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c b/drivers/clk/nuvoton/clk_npcm8xx.c index 27e3cfcf55..d1b32e3237 100644 --- a/drivers/clk/nuvoton/clk_npcm8xx.c +++ b/drivers/clk/nuvoton/clk_npcm8xx.c @@ -45,12 +45,12 @@ static struct npcm_clk_select npcm8xx_clk_selectors[] = { }; static struct npcm_clk_div npcm8xx_clk_dividers[] = { - {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2}, - {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2}, - {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2}, - {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1}, - {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1}, - {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1}, + {NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2 | DIV_RO}, + {NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2 | DIV_RO}, + {NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2 | DIV_RO}, + {NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1 | DIV_RO}, + {NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1 | DIV_RO}, + {NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1 | DIV_RO}, {NPCM8XX_CLK_SPIX, CLKDIV3, SPIXCKDIV, DIV_TYPE1}, {NPCM8XX_CLK_UART, CLKDIV1, UARTDIV1, DIV_TYPE1}, {NPCM8XX_CLK_UART2, CLKDIV3, UARTDIV2, DIV_TYPE1}, -- 2.25.1

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