November 2023 - U-Boot

[PATCH v2] net: axi_emac: Use reg property for DMA registers
by Mayuresh Chitale 21 Nov '23

21 Nov '23

As per the xlnx,axi-ethernet-1.00.a DT documentation in linux, the AXI DMA registers can be obtained via the reg property or via a separate node for the axistream DMA controller. Currently only the latter is supported, so add support to fetch the DMA controller registers from the "reg" property. Signed-off-by: Mayuresh Chitale <mchitale(a)ventanamicro.com> Reviewed-by: Michal Simek <michal.simek(a)amd.com> --- Changes in v2: ==== Add Reviewed-by Tag. drivers/net/xilinx_axi_emac.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 54f2232768..ef151ee51b 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -903,12 +903,11 @@ static int axi_emac_of_to_plat(struct udevice *dev) ret = dev_read_phandle_with_args(dev, "axistream-connected", NULL, 0, 0, &axistream_node); - if (ret) { - printf("%s: axistream is not found\n", __func__); - return -EINVAL; - } + if (!ret) + plat->dmatx = (struct axidma_reg *)ofnode_get_addr(axistream_node.node); + else + plat->dmatx = (struct axidma_reg *)dev_read_addr_index(dev, 1); - plat->dmatx = (struct axidma_reg *)ofnode_get_addr(axistream_node.node); if (!plat->dmatx) { printf("%s: axi_dma register space not found\n", __func__); return -EINVAL; -- 2.34.1

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[PATCH v3 0/2] Xilinx PCI driver fixes
by Mayuresh Chitale 21 Nov '23

21 Nov '23

This series fixes couple issues with the Xilinx PCIe host controller driver. Changes in v3: - Add error checking and improve commit title of patch 1 - Rebase patch 2 on modified patch 1 Mayuresh Chitale (2): pci: xilinx: Fix "reg" not found error pci: xilinx: Enable MMIO region drivers/pci/pcie_xilinx.c | 37 ++++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-) -- 2.34.1

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[PATCH 1/2] xilinx: zynq: Generate dfu for SPI only when enabled
by Michal Simek 21 Nov '23

21 Nov '23

Bitmain S9 board is not enabling SPI that's why CONFIG_SYS_SPI_U_BOOT_OFFS symbol is not present which ends in build failure when EFI/DFU infrastructure is enabled. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- board/xilinx/zynq/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 3b6581e30462..6c365910011d 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -184,6 +184,7 @@ void set_dfu_alt_info(char *interface, char *devstr) "mmc 0=boot.bin fat 0 1;" "%s fat 0 1", CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); break; +#if defined(CONFIG_SPL_SPI_LOAD) case ZYNQ_BM_QSPI: snprintf(buf, DFU_ALT_BUF_LEN, "sf 0:0=boot.bin raw 0 0x1500000;" @@ -191,6 +192,7 @@ void set_dfu_alt_info(char *interface, char *devstr) CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, CONFIG_SYS_SPI_U_BOOT_OFFS); break; +#endif default: return; } -- 2.36.1

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[PATCH v4 0/6] spi-nor: Add parallel and stacked memories support
by Venkatesh Yadav Abbarapu 21 Nov '23

21 Nov '23

This series adds support for Xilinx qspi parallel and stacked memeories. In parallel mode, the current implementation assumes that a maximum of two flashes are connected. The QSPI controller splits the data evenly between both the flashes so, both the flashes that are connected in parallel mode should be identical. During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in nor->flags. In stacked mode the current implementation assumes that a maximum of two flashes are connected and both the flashes are of same make but can differ in sizes. So, except the sizes all other flash parameters of both the flashes are identical. Spi-nor will pass on the appropriate flash select flag to low level driver, and it will select pass all the data to that particular flash. Write operation in parallel mode are performed in page size * 2 chunks as each write operation results in writing both the flashes. For doubling the address space each operation is performed at addr/2 flash offset, where addr is the address specified by the user. Similarly for read and erase operations it will read from both flashes, so size and offset are divided by 2 and send to flash. Changes in v2: - Fixed the compilation issues. Changes in v3: - Fixed the CI issues. Changes in v4: - Removed the dio,dummy_bytes variables from zynq_qspi driver. - Fix the compilation issue by including the DM_SERIAL config. Ashok Reddy Soma (4): mtd: spi-nor: Add parallel and stacked memories support mtd: spi-nor: Add parallel memories support for read_sr and read_fsr mtd: spi-nor: Add parallel and stacked memories support in read_bar and write_bar spi: spi-uclass: Read chipselect and restrict capabilities Venkatesh Yadav Abbarapu (2): spi: zynqmp_gqspi: Add parallel memories support in GQSPI driver spi: zynq_qspi: Add parallel memories support in QSPI driver drivers/mtd/spi/sandbox.c | 2 +- drivers/mtd/spi/spi-nor-core.c | 389 ++++++++++++++++++++++++++++----- drivers/spi/altera_spi.c | 4 +- drivers/spi/atcspi200_spi.c | 2 +- drivers/spi/ath79_spi.c | 2 +- drivers/spi/atmel_spi.c | 6 +- drivers/spi/bcm63xx_hsspi.c | 42 ++-- drivers/spi/bcm63xx_spi.c | 6 +- drivers/spi/bcmbca_hsspi.c | 34 +-- drivers/spi/cf_spi.c | 6 +- drivers/spi/davinci_spi.c | 6 +- drivers/spi/fsl_dspi.c | 18 +- drivers/spi/fsl_espi.c | 4 +- drivers/spi/fsl_qspi.c | 4 +- drivers/spi/gxp_spi.c | 2 +- drivers/spi/mpc8xx_spi.c | 4 +- drivers/spi/mpc8xxx_spi.c | 10 +- drivers/spi/mscc_bb_spi.c | 4 +- drivers/spi/mxc_spi.c | 6 +- drivers/spi/npcm_fiu_spi.c | 14 +- drivers/spi/nxp_fspi.c | 2 +- drivers/spi/octeon_spi.c | 2 +- drivers/spi/omap3_spi.c | 4 +- drivers/spi/pic32_spi.c | 2 +- drivers/spi/rk_spi.c | 4 +- drivers/spi/rockchip_sfc.c | 2 +- drivers/spi/spi-aspeed-smc.c | 28 +-- drivers/spi/spi-mxic.c | 6 +- drivers/spi/spi-qup.c | 4 +- drivers/spi/spi-sifive.c | 6 +- drivers/spi/spi-sn-f-ospi.c | 2 +- drivers/spi/spi-sunxi.c | 6 +- drivers/spi/spi-synquacer.c | 4 +- drivers/spi/spi-uclass.c | 23 +- drivers/spi/stm32_qspi.c | 2 +- drivers/spi/stm32_spi.c | 4 +- drivers/spi/ti_qspi.c | 14 +- drivers/spi/xilinx_spi.c | 4 +- drivers/spi/zynq_qspi.c | 120 ++++++++-- drivers/spi/zynq_spi.c | 6 +- drivers/spi/zynqmp_gqspi.c | 140 ++++++++++-- include/linux/mtd/spi-nor.h | 13 ++ include/spi.h | 26 ++- lib/acpi/acpi_device.c | 2 +- 44 files changed, 765 insertions(+), 226 deletions(-) -- 2.17.1

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[PATCH 0/9] Update clang support for ARM
by Tom Rini 21 Nov '23

21 Nov '23

Hey all, I decided to take a look again at what's needed to build and boot ARM platforms when building with clang. The good news is that this generally works now. Some size-constrained platforms don't build right now but I was able to test a reasonable part of my lab. This series also depends on: https://patchwork.ozlabs.org/project/uboot/patch/20200604203515.12971-1-tri… to fix the warning there. At this point LTO + clang requires a bit more work, and to use llvm-ld. As the platform I was trying was still too large to link even with this, I've set that investigation aside for now. I've boot tested clang-16 on Pi 3 (32bit, 64bit, arm64) and libretech-cc, and I'll be testing pine64_plus soon along with maybe mx6cuboxi and seeing what the failures are on am65x_evm / j721e_evm (these platforms require a bit more scripting on my part to make build and test clean). -- Tom

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[PATCH] arm: mach-k3: J721e: Add xSPI boot mode
by Reid Tonking 21 Nov '23

21 Nov '23

From: Vignesh Raghavendra <vigneshr(a)ti.com> J7200 ROM supports booting from xSPI compliant flash. Detect if ROM booted from xSPI bootmode and map that to BOOT_DEVICE_SPI Signed-off-by: Vignesh Raghavendra <vigneshr(a)ti.com> Signed-off-by: Pratyush Yadav <p.yadav(a)ti.com> --- arch/arm/mach-k3/include/mach/j721e_spl.h | 3 ++- arch/arm/mach-k3/j721e_init.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h index ed3d7333bd..c51bc5ab8e 100644 --- a/arch/arm/mach-k3/include/mach/j721e_spl.h +++ b/arch/arm/mach-k3/include/mach/j721e_spl.h @@ -24,8 +24,9 @@ #define BOOT_DEVICE_UFS 0x13 #define BOOT_DEVIE_GPMC 0x14 #define BOOT_DEVICE_PCIE 0x15 -#define BOOT_DEVICE_MMC2_2 0x16 +#define BOOT_DEVICE_XSPI 0x16 #define BOOT_DEVICE_RAM 0x17 +#define BOOT_DEVICE_MMC2_2 0xFF /* Invalid value */ /* Backup boot modes with MCU Only = 0 */ #define BACKUP_BOOT_DEVICE_RAM 0x0 diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 18814c39ec..7bd64107b2 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -340,7 +340,8 @@ static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat) bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << BOOT_MODE_B_SHIFT; - if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI) + if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI || + bootmode == BOOT_DEVICE_XSPI) bootmode = BOOT_DEVICE_SPI; if (bootmode == BOOT_DEVICE_MMC2) { -- 2.34.1

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[UBOOT PATCH v3] test/py: net: Add dhcp abort test
by Love Kumar 21 Nov '23

21 Nov '23

Abort the dhcp request in the middle by pressing ctrl + c on u-boot prompt and validate the abort status. Signed-off-by: Love Kumar <love.kumar(a)amd.com> --- Changes in v2: - Mark CMD_MII command dependency Changes in v3: - Skip the test if PHY device not present --- test/py/tests/test_net.py | 47 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py index b2241ae6a482..76647f274006 100644 --- a/test/py/tests/test_net.py +++ b/test/py/tests/test_net.py @@ -7,6 +7,7 @@ import pytest import u_boot_utils import uuid +import re """ Note: This test relies on boardenv_* containing configuration values to define @@ -115,6 +116,52 @@ def test_net_dhcp(u_boot_console): global net_set_up net_set_up = True +(a)pytest.mark.buildconfigspec("cmd_dhcp") +(a)pytest.mark.buildconfigspec("cmd_mii") +def test_net_dhcp_abort(u_boot_console): + """Test the dhcp command by pressing ctrl+c in the middle of dhcp request + + The boardenv_* file may be used to enable/disable this test; see the + comment at the beginning of this file. + """ + + test_dhcp = u_boot_console.config.env.get("env__net_dhcp_server", False) + if not test_dhcp: + pytest.skip("No DHCP server available") + + u_boot_console.run_command("setenv autoload no") + + # Phy reset before running dhcp command + output = u_boot_console.run_command("mii device") + if not re.search(r"Current device: '(.+?)'", output): + pytest.skip("PHY device does not exist!") + eth_num = re.search(r"Current device: '(.+?)'", output).groups()[0] + u_boot_console.run_command(f"mii device {eth_num}") + output = u_boot_console.run_command("mii info") + eth_addr = hex(int(re.search(r"PHY (.+?):", output).groups()[0], 16)) + u_boot_console.run_command(f"mii modify {eth_addr} 0 0x8000 0x8000") + + u_boot_console.run_command("dhcp", wait_for_prompt=False) + try: + u_boot_console.wait_for("Waiting for PHY auto negotiation to complete") + except: + pytest.skip("Timeout waiting for PHY auto negotiation to complete") + + u_boot_console.wait_for("done") + + # Sending Ctrl-C + output = u_boot_console.run_command( + chr(3), wait_for_echo=False, send_nl=False + ) + + assert "TIMEOUT" not in output + assert "DHCP client bound to address " not in output + assert "Abort" in output + + # Provide a time to recover from Abort - if it is not performed + # There is message like: ethernet@ff0e0000: No link. + u_boot_console.run_command("sleep 1") + @pytest.mark.buildconfigspec('cmd_dhcp6') def test_net_dhcp6(u_boot_console): """Test the dhcp6 command. -- 2.25.1

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[PATCH] arm64: zynqmp: Add multiboot support for SPL/SPI offset calculation
by Michal Simek 21 Nov '23

21 Nov '23

In case of A/B update systems there should be an option to load the same binary/binaries to different location and they should work. Before this patch boot.bin with U-Boot SPL can be added to whatever 32k offset in SPI and SPL finds u-boot.itb at CONFIG_SYS_SPI_U_BOOT_OFFS offset. In case of A/B update systems that means that SPL is at different locations but it still points to the same u-boot.itb which is not correct. That's why include multiboot value to offset calculation to be able to point to image from the same base. It doesn't affect any current system which starts from 0 offset. This patch also change Kria defconfig which uses A/B setup. Partition A starts at multiboot 64, partition B at multiboot 496. And also print message about used SPI offset which is useful for all cases. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- board/xilinx/zynqmp/zynqmp.c | 15 +++++++++++++++ configs/xilinx_zynqmp_kria_defconfig | 2 +- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index f16280308483..59feaaf6f32f 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -681,3 +681,18 @@ void set_dfu_alt_info(char *interface, char *devstr) puts("DFU alt info setting: done\n"); } #endif + +#if defined(CONFIG_SPL_SPI_LOAD) +unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash) +{ + u32 offset; + int multiboot = multi_boot(); + + offset = multiboot * SZ_32K; + offset += CONFIG_SYS_SPI_U_BOOT_OFFS; + + log_info("SPI offset:\t0x%x\n", offset); + + return offset; +} +#endif diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index daedf1de01ea..a20df1a4072f 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -48,7 +48,7 @@ CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x8000000 CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_SYS_MAXARGS=64 -- 2.36.1

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RGMII handling in Marvell PHY driver wrong?
by David Müller (ELSOFT AG) 21 Nov '23

21 Nov '23

Hello Since commit 68e6ecadc551 ("net: phy: marvell 88e151x: Fix handling of RGMII interface types") it is possible to set the Rx/Tx delays settings of Marvell PHYs from the DTS. The code handled all 4 possible cases ("PHY_INTERFACE_MODE_RGMII", "PHY_INTERFACE_MODE_RGMII_ID", "PHY_INTERFACE_MODE_RGMII_RXID", "PHY_INTERFACE_MODE_RGMII_TXID") of the Rx/Tx delay bits in the MSCR register. Later, commit 431be621c6cb ("net: phy: marvell 88e151x: Fix handling of bare RGMII interface type") merged the "PHY_INTERFACE_MODE_RGMII" and "PHY_INTERFACE_MODE_RGMII_ID" cases, effectively loosing the possibility to specify Rx/Tx delay bits both cleared. This looks wrong for at least two reasons: - How does one describe a system with a Rx/Tx delay bits clear requirement in the DTS properly? - The Linux Marvell PHY driver does not merge the "PHY_INTERFACE_MODE_RGMII" and "PHY_INTERFACE_MODE_RGMII_ID" cases either. Therefore I think commit 431be621c6cb should be reverted. Or am I missing something here?

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[PATCH v2 1/2] usb: ci: Fix gadget reinit
by Simon Holesch 21 Nov '23

21 Nov '23

The ChipIdea device controller wasn't properly cleaned up when disabled. So enabling it again left it in a broken state. The problem occurred for example when the host unbinds the driver and binds it again. During the first setup, when the out request is queued, the endpoint is primed (`epprime`). If the endpoint is then disabled, it stayed primed with the initial buffer. So after the endpoint is re-enabled, the device controller and device driver were out of sync: the new out request was in the driver queue head, yet not submitted, but the "complete" function was still called, since the endpoint was primed with the old buffer. With the fastboot function this error led to the (rather confusing) error message "buffer overflow". Fixed by clearing the primed buffers with the `epflush` (`ENDPTFLUSH`) register. Signed-off-by: Simon Holesch <simon(a)holesch.de> Reviewed-by: Marek Vasut <marex(a)denx.de> --- Changes in v2: - use wait_for_bit_le32(), clrbits_le32 I didn't use setbits_le32(), because the epflush register ignores 0 bits. Thanks for the review! drivers/usb/gadget/ci_udc.c | 38 +++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 2bfacfe59f..750d471487 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -13,6 +13,7 @@ #include <cpu_func.h> #include <net.h> #include <malloc.h> +#include <wait_bit.h> #include <asm/byteorder.h> #include <asm/cache.h> #include <linux/delay.h> @@ -354,12 +355,49 @@ static int ci_ep_enable(struct usb_ep *ep, return 0; } +static int ep_disable(int num, int in) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + unsigned int ep_bit, enable_bit; + int err; + + if (in) { + ep_bit = EPT_TX(num); + enable_bit = CTRL_TXE; + } else { + ep_bit = EPT_RX(num); + enable_bit = CTRL_RXE; + } + + /* clear primed buffers */ + do { + writel(ep_bit, &udc->epflush); + err = wait_for_bit_le32(&udc->epflush, ep_bit, false, 1000, false); + if (err) + return err; + } while (readl(&udc->epstat) & ep_bit); + + /* clear enable bit */ + clrbits_le32(&udc->epctrl[num], enable_bit); + + return 0; +} + static int ci_ep_disable(struct usb_ep *ep) { struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + int num, in, err; + + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + + err = ep_disable(num, in); + if (err) + return err; ci_ep->desc = NULL; ep->desc = NULL; + ci_ep->req_primed = false; return 0; } -- 2.42.1

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