October 2023 - U-Boot

[PATCH v4 00/44] spl: Preparation for Universal Payload
by Simon Glass 07 Oct '23

07 Oct '23

This series tidies up SPL a little and adds some core ofnode functions needed to support Universal Payload. It also includes a few minor fix-ups for sandbox. For SPL the changes include CONFIG naming, removing various #ifdefs and tidying up the FIT code. One notable piece of the ofnode improvements is support for flattening a livetree. This should be useful in future as we move FDT fixups to use the ofnode API. With v4 an attempt is made to reduce code-size impact, resulting in this for lion-rk3368 : 45: pci: serial: Support reading PCI-register size with base aarch64: (for 1/1 boards) all +318.0 rodata +46.0 spl/u-boot-spl:all -136.0 spl/u-boot-spl:rodata +16.0 spl/u-boot-spl:text -152.0 text +272.0 tpl/u-boot-tpl:all -109.0 tpl/u-boot-tpl:rodata +19.0 tpl/u-boot-tpl:text -128.0 The U-Boot proper growth is due to using dev_read_addr_size() instead of dev_read_addr() in ns16550. Changes in v4: - Add new patch to drop mention of SPL/TPL_SYS_MALLOC_F - Take account of CONFIG_BOOTSTAGE_STASH for stashing, to avoid size inc - Split all new bloblist names into a separate patch - Use an #ifdef to avoid adding a string - Add new patch with C-based runtime detection of SPL - Add new patch to drop ns16550 serial_getinfo() in SPL - Add new patch to tweak device_is_on_pci_bus() for code size - Avoid reading size except in SPL Changes in v3: - Mention testing on qemu-ppce500 - Add new patch to create a proper symbol for enabling the malloc() pool - Add new patch to enable CONFIG_SPL_SYS_MALLOC_F where needed - Add new patch to nable CONFIG_TPL_SYS_MALLOC_F where needed - Add new patch to use SYS_MALLOC_F instead of SYS_MALLOC_F_LEN - Add new patch to tidy up uses of CONFIG_SYS_MALLOC_F_LEN - Add new patch to clean up SYS_MALLOC_SIMPLE documentation - Add new patch to correct help in TPL_DM and VPL_DM - Rebase on the new patch Changes in v2: - Rename based on Tom's feedback - Improve readability by moving the size part to the header file - Explicitly copy two maintainers as it seems only Mario was auto-cc'd - Change the approach to use the header file - Use the same condition for both pieces to avoid possible problems - No changes as it still seems unclear what should be done Simon Glass (44): configs: Resync with savedefconfig spl: Use CONFIG_SPL... instead of CONFIG_..._SPL_... spl: Rename SYS_SPL_ARGS_ADDR to SPL_PAYLOAD_ARGS_ADDR spl: Avoid #ifdef with CONFIG_SPL_SYS_MALLOC spl: mx6: powerpc: Drop the condition on timer_init() spl: Drop #ifdefs for BOARD_INIT and watchdog spl: Avoid #ifdef with CONFIG_SPL_PAYLOAD_ARGS_ADDR spl: Drop the switch() statement for OS selection serial: Drop mention of SPL/TPL_SYS_MALLOC_F spl: Create proper symbols for enabling the malloc() pool spl: Enable CONFIG_SPL_SYS_MALLOC_F where needed tpl: Enable CONFIG_TPL_SYS_MALLOC_F where needed spl: Use SYS_MALLOC_F instead of SYS_MALLOC_F_LEN Tidy up uses of CONFIG_SYS_MALLOC_F_LEN doc: Clean up SYS_MALLOC_SIMPLE dm: core: Correct help in TPL_DM and VPL_DM spl: Avoid an #ifdef when printing gd->malloc_ptr spl: Remove #ifdefs with BOOTSTAGE spl: Rename spl_load_fit_image() to load_simple_fit() spl: Move the full FIT code to spl_fit.c spl: Use the correct FIT_..._PROP constants spl: Move bloblist writing until the image is known dm: core: Reverse the argument order in ofnode_copy_props() dm: core: Ensure we run flattree tests on ofnode dm: core: Tidy up comments in the ofnode tests dm: core: Add a function to create an empty tree dm: core: Add a way to copy a node dm: core: Add a way to delete a node dm: core: Add a way to convert a devicetree to a dtb dm: core: Support writing a boolean dm: core: Support writing a 64-bit value dm: core: Add tests for oftree_path() sandbox: Move reading the RAM buffer into a better place sandbox: Init the EC properly even if no state file is available sandbox: Only read the state if we have a state file sandbox: Move the bloblist down a little in memory bloblist: Support initing from multiple places bloblist: Add missing name fdt: Allow the devicetree to come from a bloblist command: Include a required header in command.h spl: Add C-based runtime detection of SPL serial: Drop ns16550 serial_getinfo() in SPL dm: core: Tweak device_is_on_pci_bus() for code size pci: serial: Support reading PCI-register size with base Kconfig | 69 +++-- Makefile | 2 +- README | 18 -- arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- .../armv8/fsl-layerscape/doc/README.falcon | 2 +- arch/arm/lib/bdinfo.c | 2 +- arch/arm/mach-rockchip/rv1126/Kconfig | 3 + arch/arm/mach-snapdragon/Kconfig | 3 + arch/arm/mach-socfpga/Kconfig | 3 + arch/mips/cpu/start.S | 4 +- arch/mips/mach-mtmips/mt7621/spl/start.S | 4 +- arch/powerpc/cpu/mpc83xx/start.S | 2 +- arch/powerpc/cpu/mpc85xx/start.S | 4 +- arch/sandbox/cpu/start.c | 29 +- arch/sandbox/cpu/state.c | 2 + arch/sandbox/dts/test.dts | 6 +- arch/sh/lib/start.S | 4 +- boot/vbe_request.c | 2 +- boot/vbe_simple_os.c | 2 +- common/Kconfig | 2 +- common/Makefile | 6 +- common/bloblist.c | 15 +- common/board_f.c | 6 +- common/board_r.c | 2 +- common/bootstage.c | 14 + common/dlmalloc.c | 12 +- common/init/board_init.c | 4 +- common/spl/Kconfig | 16 +- common/spl/Kconfig.nxp | 2 +- common/spl/spl.c | 226 ++++----------- common/spl/spl_ext.c | 4 +- common/spl/spl_fat.c | 4 +- common/spl/spl_fit.c | 127 +++++++-- common/spl/spl_mmc.c | 2 +- common/spl/spl_nand.c | 10 +- common/spl/spl_nor.c | 8 +- common/spl/spl_spi.c | 2 +- common/spl/spl_ubi.c | 2 +- common/spl/spl_xip.c | 2 +- configs/10m50_defconfig | 2 +- configs/3c120_defconfig | 2 +- configs/CMPC885_defconfig | 2 +- configs/CMPCPRO_defconfig | 4 +- configs/MCR3000_defconfig | 4 +- configs/MPC837XERDB_defconfig | 2 +- configs/MPC8548CDS_36BIT_defconfig | 4 +- configs/MPC8548CDS_defconfig | 4 +- configs/MPC8548CDS_legacy_defconfig | 4 +- configs/P1010RDB-PA_36BIT_NAND_defconfig | 4 +- configs/P1010RDB-PA_36BIT_NOR_defconfig | 4 +- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 4 +- configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 4 +- configs/P1010RDB-PA_NAND_defconfig | 4 +- configs/P1010RDB-PA_NOR_defconfig | 4 +- configs/P1010RDB-PA_SDCARD_defconfig | 4 +- configs/P1010RDB-PA_SPIFLASH_defconfig | 4 +- configs/P1010RDB-PB_36BIT_NAND_defconfig | 4 +- configs/P1010RDB-PB_36BIT_NOR_defconfig | 4 +- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 4 +- configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 4 +- configs/P1010RDB-PB_NAND_defconfig | 4 +- configs/P1010RDB-PB_NOR_defconfig | 4 +- configs/P1010RDB-PB_SDCARD_defconfig | 4 +- configs/P1010RDB-PB_SPIFLASH_defconfig | 4 +- configs/P1020RDB-PC_36BIT_NAND_defconfig | 4 +- configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 6 +- configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 6 +- configs/P1020RDB-PC_36BIT_defconfig | 4 +- configs/P1020RDB-PC_NAND_defconfig | 4 +- configs/P1020RDB-PC_SDCARD_defconfig | 6 +- configs/P1020RDB-PC_SPIFLASH_defconfig | 6 +- configs/P1020RDB-PC_defconfig | 4 +- configs/P1020RDB-PD_NAND_defconfig | 4 +- configs/P1020RDB-PD_SDCARD_defconfig | 6 +- configs/P1020RDB-PD_SPIFLASH_defconfig | 6 +- configs/P1020RDB-PD_defconfig | 4 +- configs/P2020RDB-PC_36BIT_NAND_defconfig | 4 +- configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 6 +- configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 6 +- configs/P2020RDB-PC_36BIT_defconfig | 4 +- configs/P2020RDB-PC_NAND_defconfig | 4 +- configs/P2020RDB-PC_SDCARD_defconfig | 6 +- configs/P2020RDB-PC_SPIFLASH_defconfig | 6 +- configs/P2020RDB-PC_defconfig | 4 +- configs/P2041RDB_NAND_defconfig | 6 +- configs/P2041RDB_SDCARD_defconfig | 6 +- configs/P2041RDB_SPIFLASH_defconfig | 6 +- configs/P2041RDB_defconfig | 4 +- configs/T1024RDB_NAND_defconfig | 4 +- configs/T1024RDB_SDCARD_defconfig | 4 +- configs/T1024RDB_SPIFLASH_defconfig | 4 +- configs/T1024RDB_defconfig | 2 +- configs/T1042D4RDB_NAND_defconfig | 4 +- configs/T1042D4RDB_SDCARD_defconfig | 4 +- configs/T1042D4RDB_SPIFLASH_defconfig | 4 +- configs/T1042D4RDB_defconfig | 2 +- configs/T2080QDS_NAND_defconfig | 6 +- configs/T2080QDS_SDCARD_defconfig | 6 +- configs/T2080QDS_SECURE_BOOT_defconfig | 4 +- configs/T2080QDS_SPIFLASH_defconfig | 6 +- configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 4 +- configs/T2080QDS_defconfig | 4 +- configs/T2080RDB_NAND_defconfig | 4 +- configs/T2080RDB_SDCARD_defconfig | 4 +- configs/T2080RDB_SPIFLASH_defconfig | 4 +- configs/T2080RDB_defconfig | 2 +- configs/T2080RDB_revD_NAND_defconfig | 4 +- configs/T2080RDB_revD_SDCARD_defconfig | 4 +- configs/T2080RDB_revD_SPIFLASH_defconfig | 4 +- configs/T2080RDB_revD_defconfig | 2 +- configs/T4240RDB_SDCARD_defconfig | 4 +- configs/T4240RDB_defconfig | 2 +- configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv32_spl_defconfig | 2 +- configs/ae350_rv32_spl_xip_defconfig | 2 +- configs/ae350_rv32_xip_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_spl_defconfig | 2 +- configs/ae350_rv64_spl_xip_defconfig | 2 +- configs/ae350_rv64_xip_defconfig | 2 +- configs/am335x_baltos_defconfig | 6 +- configs/am335x_boneblack_vboot_defconfig | 4 +- configs/am335x_evm_defconfig | 6 +- configs/am335x_evm_spiboot_defconfig | 6 +- configs/am335x_guardian_defconfig | 4 +- configs/am335x_hs_evm_defconfig | 6 +- configs/am335x_hs_evm_uart_defconfig | 6 +- configs/am335x_igep003x_defconfig | 8 +- configs/am335x_pdu001_defconfig | 4 +- configs/am335x_shc_defconfig | 4 +- configs/am335x_shc_ict_defconfig | 4 +- configs/am335x_shc_netboot_defconfig | 4 +- configs/am335x_shc_sdboot_defconfig | 4 +- configs/am335x_sl50_defconfig | 4 +- configs/am3517_evm_defconfig | 6 +- configs/am43xx_evm_defconfig | 4 +- configs/am43xx_evm_rtconly_defconfig | 4 +- configs/am43xx_evm_usbhost_boot_defconfig | 4 +- configs/am43xx_hs_evm_defconfig | 6 +- configs/am57xx_evm_defconfig | 6 +- configs/am57xx_hs_evm_defconfig | 6 +- configs/am57xx_hs_evm_usb_defconfig | 7 +- configs/am62ax_evm_r5_defconfig | 6 +- configs/am62x_evm_r5_defconfig | 8 +- configs/am64x_evm_a53_defconfig | 4 +- configs/am64x_evm_r5_defconfig | 8 +- configs/am65x_evm_a53_defconfig | 6 +- configs/am65x_evm_r5_defconfig | 8 +- configs/am65x_evm_r5_usbdfu_defconfig | 8 +- configs/am65x_evm_r5_usbmsc_defconfig | 8 +- configs/am65x_hs_evm_a53_defconfig | 6 +- configs/am65x_hs_evm_r5_defconfig | 8 +- configs/apalis-imx8_defconfig | 2 +- configs/apalis-tk1_defconfig | 10 +- configs/apalis_imx6_defconfig | 2 +- configs/apalis_t30_defconfig | 8 +- configs/axm_defconfig | 8 +- configs/bayleybay_defconfig | 1 - configs/bcmns_defconfig | 4 +- configs/beaver_defconfig | 8 +- configs/bitmain_antminer_s9_defconfig | 4 +- configs/boston32r2_defconfig | 2 +- configs/boston32r2el_defconfig | 2 +- configs/boston32r6_defconfig | 2 +- configs/boston32r6el_defconfig | 2 +- configs/boston64r2_defconfig | 2 +- configs/boston64r2el_defconfig | 2 +- configs/boston64r6_defconfig | 2 +- configs/boston64r6el_defconfig | 2 +- configs/brppt1_mmc_defconfig | 6 +- configs/brppt2_defconfig | 4 +- configs/brsmarc1_defconfig | 6 +- configs/brxre1_defconfig | 6 +- configs/cardhu_defconfig | 8 +- configs/cei-tk1-som_defconfig | 8 +- configs/cgtqmx8_defconfig | 10 +- configs/cherryhill_defconfig | 1 - configs/chiliboard_defconfig | 4 +- configs/chromebook_coral_defconfig | 3 +- configs/chromebook_link_defconfig | 1 - configs/chromebook_samus_defconfig | 1 - configs/chromebook_samus_tpl_defconfig | 6 +- configs/chromebox_panther_defconfig | 1 - configs/cl-som-imx7_defconfig | 2 +- configs/cm_fx6_defconfig | 6 +- configs/cm_t43_defconfig | 4 +- configs/colibri-imx8x_defconfig | 2 +- configs/colibri_imx6_defconfig | 2 +- configs/colibri_t20_defconfig | 8 +- configs/colibri_t30_defconfig | 8 +- configs/colibri_vf_defconfig | 2 +- ...-qeval20-qa3-e3845-internal-uart_defconfig | 1 - configs/conga-qeval20-qa3-e3845_defconfig | 1 - configs/coreboot64_defconfig | 2 +- configs/coreboot_defconfig | 2 +- configs/cortina_presidio-asic-emmc_defconfig | 1 - configs/cougarcanyon2_defconfig | 1 - configs/crownbay_defconfig | 1 - configs/da850evm_defconfig | 8 +- configs/da850evm_nand_defconfig | 8 +- configs/dalmore_defconfig | 8 +- configs/deneb_defconfig | 12 +- configs/devkit8000_defconfig | 8 +- configs/dfi-bt700-q7x-151_defconfig | 1 - configs/dh_imx6_defconfig | 2 +- configs/display5_defconfig | 4 +- configs/display5_factory_defconfig | 6 +- configs/dra7xx_evm_defconfig | 6 +- configs/dra7xx_hs_evm_defconfig | 6 +- configs/dra7xx_hs_evm_usb_defconfig | 6 +- configs/draco_defconfig | 6 +- configs/dragonboard410c_defconfig | 2 +- configs/durian_defconfig | 1 - configs/ea-lpc3250devkitv2_defconfig | 2 +- configs/efi-x86_payload32_defconfig | 1 - configs/efi-x86_payload64_defconfig | 2 - configs/endeavoru_defconfig | 14 +- configs/etamin_defconfig | 6 +- configs/galileo_defconfig | 1 - .../gardena-smart-gateway-at91sam_defconfig | 4 +- .../gardena-smart-gateway-mt7688_defconfig | 2 +- configs/gazerbeam_defconfig | 4 +- configs/ge_b1x5v2_defconfig | 4 +- configs/ge_bx50v3_defconfig | 2 +- configs/giedi_defconfig | 12 +- configs/grouper_common_defconfig | 14 +- configs/gwventana_emmc_defconfig | 8 +- configs/gwventana_nand_defconfig | 8 +- configs/harmony_defconfig | 8 +- configs/highbank_defconfig | 2 +- configs/igep00x0_defconfig | 10 +- configs/imx28_xea_defconfig | 4 +- configs/imx6dl_icore_nand_defconfig | 2 +- configs/imx6dl_mamoj_defconfig | 4 +- configs/imx6q_bosch_acc_defconfig | 2 +- configs/imx6q_icore_nand_defconfig | 2 +- configs/imx6q_logic_defconfig | 4 +- configs/imx6qdl_icore_mipi_defconfig | 4 +- configs/imx6qdl_icore_mmc_defconfig | 4 +- configs/imx6qdl_icore_nand_defconfig | 2 +- configs/imx6qdl_icore_rqs_defconfig | 4 +- configs/imx6ul_geam_mmc_defconfig | 2 +- configs/imx6ul_geam_nand_defconfig | 2 +- configs/imx6ul_isiot_emmc_defconfig | 2 +- configs/imx6ul_isiot_nand_defconfig | 2 +- configs/imx6ulz_smm_m2_defconfig | 2 +- configs/imx7_cm_defconfig | 2 +- configs/imx8mm-cl-iot-gate-optee_defconfig | 10 +- configs/imx8mm-cl-iot-gate_defconfig | 10 +- configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 10 +- configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 10 +- configs/imx8mm-mx8menlo_defconfig | 10 +- configs/imx8mm_beacon_defconfig | 8 +- configs/imx8mm_beacon_fspi_defconfig | 8 +- configs/imx8mm_data_modul_edm_sbc_defconfig | 8 +- configs/imx8mm_evk_defconfig | 10 +- configs/imx8mm_evk_fspi_defconfig | 10 +- configs/imx8mm_phg_defconfig | 10 +- configs/imx8mm_venice_defconfig | 8 +- configs/imx8mn_beacon_2g_defconfig | 8 +- configs/imx8mn_beacon_defconfig | 8 +- configs/imx8mn_beacon_fspi_defconfig | 8 +- configs/imx8mn_bsh_smm_s2_defconfig | 10 +- configs/imx8mn_bsh_smm_s2pro_defconfig | 10 +- configs/imx8mn_ddr4_evk_defconfig | 10 +- configs/imx8mn_evk_defconfig | 10 +- configs/imx8mn_var_som_defconfig | 10 +- configs/imx8mn_venice_defconfig | 10 +- configs/imx8mp-icore-mx8mp-edimm2.2_defconfig | 10 +- configs/imx8mp_beacon_defconfig | 10 +- configs/imx8mp_data_modul_edm_sbc_defconfig | 8 +- configs/imx8mp_dhcom_pdk2_defconfig | 8 +- configs/imx8mp_dhcom_pdk3_defconfig | 8 +- configs/imx8mp_evk_defconfig | 10 +- configs/imx8mp_rsb3720a1_4G_defconfig | 10 +- configs/imx8mp_rsb3720a1_6G_defconfig | 10 +- configs/imx8mp_venice_defconfig | 10 +- configs/imx8mq_cm_defconfig | 10 +- configs/imx8mq_evk_defconfig | 10 +- configs/imx8mq_phanbell_defconfig | 10 +- configs/imx8mq_reform2_defconfig | 10 +- configs/imx8qm_dmsse20a1_defconfig | 2 +- configs/imx8qm_mek_defconfig | 10 +- configs/imx8qxp_mek_defconfig | 10 +- configs/imx8ulp_evk_defconfig | 8 +- configs/imx93_11x11_evk_defconfig | 8 +- configs/imx93_11x11_evk_ld_defconfig | 8 +- configs/iot2050_defconfig | 8 +- configs/j7200_evm_a72_defconfig | 6 +- configs/j7200_evm_r5_defconfig | 8 +- configs/j721e_evm_a72_defconfig | 6 +- configs/j721e_evm_r5_defconfig | 8 +- configs/j721s2_evm_a72_defconfig | 6 +- configs/j721s2_evm_r5_defconfig | 8 +- configs/jetson-tk1_defconfig | 8 +- configs/k2e_evm_defconfig | 6 +- configs/k2e_hs_evm_defconfig | 2 +- configs/k2g_evm_defconfig | 6 +- configs/k2g_hs_evm_defconfig | 2 +- configs/k2hk_evm_defconfig | 6 +- configs/k2hk_hs_evm_defconfig | 2 +- configs/k2l_evm_defconfig | 6 +- configs/kmcent2_defconfig | 2 +- configs/kmcoge5ne_defconfig | 4 +- configs/kmeter1_defconfig | 4 +- configs/kmopti2_defconfig | 4 +- configs/kmsupx5_defconfig | 4 +- configs/kmtepr2_defconfig | 4 +- configs/kontron-sl-mx6ul_defconfig | 6 +- configs/kontron-sl-mx8mm_defconfig | 10 +- configs/kontron_pitx_imx8m_defconfig | 10 +- configs/kontron_sl28_defconfig | 6 +- configs/kp_imx6q_tpc_defconfig | 2 +- configs/librem5_defconfig | 10 +- configs/liteboard_defconfig | 2 +- configs/ls1012a2g5rdb_qspi_defconfig | 4 +- configs/ls1012a2g5rdb_tfa_defconfig | 4 +- configs/ls1012afrdm_qspi_defconfig | 4 +- configs/ls1012afrdm_tfa_defconfig | 4 +- .../ls1012afrwy_qspi_SECURE_BOOT_defconfig | 4 +- configs/ls1012afrwy_qspi_defconfig | 4 +- configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 4 +- configs/ls1012afrwy_tfa_defconfig | 4 +- configs/ls1012aqds_qspi_defconfig | 4 +- configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 4 +- configs/ls1012aqds_tfa_defconfig | 4 +- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 4 +- configs/ls1012ardb_qspi_defconfig | 4 +- configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 4 +- configs/ls1012ardb_tfa_defconfig | 4 +- configs/ls1021aiot_qspi_defconfig | 2 +- configs/ls1021aiot_sdcard_defconfig | 10 +- configs/ls1021aqds_ddr4_nor_defconfig | 4 +- configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 4 +- configs/ls1021aqds_nand_defconfig | 12 +- configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 4 +- configs/ls1021aqds_nor_defconfig | 4 +- configs/ls1021aqds_nor_lpuart_defconfig | 4 +- configs/ls1021aqds_qspi_defconfig | 4 +- configs/ls1021aqds_sdcard_ifc_defconfig | 8 +- configs/ls1021aqds_sdcard_qspi_defconfig | 6 +- configs/ls1021atsn_qspi_defconfig | 4 +- configs/ls1021atsn_sdcard_defconfig | 10 +- configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 4 +- configs/ls1021atwr_nor_defconfig | 4 +- configs/ls1021atwr_nor_lpuart_defconfig | 4 +- configs/ls1021atwr_qspi_defconfig | 4 +- ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 10 +- configs/ls1021atwr_sdcard_ifc_defconfig | 10 +- configs/ls1021atwr_sdcard_qspi_defconfig | 10 +- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 4 +- configs/ls1028aqds_tfa_defconfig | 4 +- configs/ls1028aqds_tfa_lpuart_defconfig | 4 +- configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 4 +- configs/ls1028ardb_tfa_defconfig | 4 +- configs/ls1043aqds_defconfig | 4 +- configs/ls1043aqds_lpuart_defconfig | 4 +- configs/ls1043aqds_nand_defconfig | 10 +- configs/ls1043aqds_nor_ddr3_defconfig | 4 +- configs/ls1043aqds_qspi_defconfig | 4 +- configs/ls1043aqds_sdcard_ifc_defconfig | 6 +- configs/ls1043aqds_sdcard_qspi_defconfig | 6 +- configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 4 +- configs/ls1043aqds_tfa_defconfig | 4 +- configs/ls1043ardb_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_defconfig | 2 +- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 8 +- configs/ls1043ardb_nand_defconfig | 8 +- .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 4 +- configs/ls1043ardb_sdcard_defconfig | 4 +- configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_tfa_defconfig | 2 +- configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046afrwy_tfa_defconfig | 2 +- configs/ls1046aqds_SECURE_BOOT_defconfig | 4 +- configs/ls1046aqds_defconfig | 4 +- configs/ls1046aqds_lpuart_defconfig | 4 +- configs/ls1046aqds_nand_defconfig | 6 +- configs/ls1046aqds_qspi_defconfig | 4 +- configs/ls1046aqds_sdcard_ifc_defconfig | 6 +- configs/ls1046aqds_sdcard_qspi_defconfig | 6 +- configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 4 +- configs/ls1046aqds_tfa_defconfig | 4 +- configs/ls1046ardb_emmc_defconfig | 4 +- configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_qspi_defconfig | 2 +- configs/ls1046ardb_qspi_spl_defconfig | 6 +- .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 4 +- configs/ls1046ardb_sdcard_defconfig | 4 +- configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_tfa_defconfig | 2 +- configs/ls1088aqds_defconfig | 2 +- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 4 +- configs/ls1088aqds_qspi_defconfig | 4 +- configs/ls1088aqds_sdcard_ifc_defconfig | 4 +- configs/ls1088aqds_sdcard_qspi_defconfig | 4 +- configs/ls1088aqds_tfa_defconfig | 4 +- configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 4 +- configs/ls1088ardb_qspi_defconfig | 4 +- ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 4 +- configs/ls1088ardb_sdcard_qspi_defconfig | 4 +- configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_tfa_defconfig | 2 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 4 +- configs/ls2080aqds_defconfig | 4 +- configs/ls2080aqds_nand_defconfig | 8 +- configs/ls2080aqds_qspi_defconfig | 6 +- configs/ls2080aqds_sdcard_defconfig | 8 +- configs/ls2080ardb_SECURE_BOOT_defconfig | 4 +- configs/ls2080ardb_defconfig | 4 +- configs/ls2080ardb_nand_defconfig | 8 +- configs/ls2081ardb_defconfig | 6 +- configs/ls2088aqds_tfa_defconfig | 4 +- configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 6 +- configs/ls2088ardb_qspi_defconfig | 6 +- configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 4 +- configs/ls2088ardb_tfa_defconfig | 4 +- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/lx2160aqds_tfa_defconfig | 4 +- configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/lx2160ardb_tfa_defconfig | 4 +- configs/lx2160ardb_tfa_stmm_defconfig | 4 +- configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/lx2162aqds_tfa_defconfig | 4 +- .../lx2162aqds_tfa_verified_boot_defconfig | 4 +- configs/m53menlo_defconfig | 2 +- configs/mccmon6_nor_defconfig | 4 +- configs/mccmon6_sd_defconfig | 2 +- configs/medcom-wide_defconfig | 8 +- configs/minnowmax_defconfig | 1 - configs/msc_sm2s_imx8mp_defconfig | 10 +- configs/mvebu_espressobin-88f3720_defconfig | 3 +- configs/mx53ppd_defconfig | 2 +- configs/mx6cuboxi_defconfig | 4 +- configs/mx6memcal_defconfig | 2 +- configs/mx6sabreauto_defconfig | 2 +- configs/mx6sabresd_defconfig | 2 +- configs/mx6slevk_spl_defconfig | 2 +- configs/mx6ul_14x14_evk_defconfig | 2 +- configs/mx6ul_9x9_evk_defconfig | 2 +- configs/myir_mys_6ulx_defconfig | 2 +- configs/novena_defconfig | 2 +- configs/nyan-big_defconfig | 10 +- configs/octeontx2_95xx_defconfig | 3 +- configs/octeontx2_96xx_defconfig | 3 +- configs/octeontx_81xx_defconfig | 2 +- configs/octeontx_83xx_defconfig | 2 +- configs/odroid-xu3_defconfig | 1 - configs/odroid_defconfig | 1 - configs/omap35_logic_defconfig | 6 +- configs/omap35_logic_somlv_defconfig | 8 +- configs/omap3_beagle_defconfig | 4 +- configs/omap3_evm_defconfig | 4 +- configs/omap3_logic_defconfig | 6 +- configs/omap3_logic_somlv_defconfig | 8 +- configs/omap4_panda_defconfig | 4 +- configs/omap4_sdp4430_defconfig | 4 +- configs/omapl138_lcdk_defconfig | 8 +- configs/openpiton_riscv64_spl_defconfig | 2 +- configs/opos6uldev_defconfig | 2 +- configs/origen_defconfig | 1 - configs/paz00_defconfig | 8 +- configs/pcm051_rev3_defconfig | 2 +- configs/pcm058_defconfig | 2 +- configs/pg_wcom_expu1_defconfig | 4 +- configs/pg_wcom_expu1_update_defconfig | 4 +- configs/pg_wcom_seli8_defconfig | 4 +- configs/pg_wcom_seli8_update_defconfig | 4 +- configs/phycore-am335x-r2-regor_defconfig | 6 +- configs/phycore-am335x-r2-wega_defconfig | 6 +- configs/phycore-imx8mm_defconfig | 8 +- configs/phycore-imx8mp_defconfig | 8 +- configs/phycore_pcl063_defconfig | 2 +- configs/phycore_pcl063_ull_defconfig | 2 +- configs/pico-dwarf-imx6ul_defconfig | 2 +- configs/pico-dwarf-imx7d_defconfig | 2 +- configs/pico-hobbit-imx6ul_defconfig | 2 +- configs/pico-hobbit-imx7d_defconfig | 2 +- configs/pico-imx6_defconfig | 2 +- configs/pico-imx6ul_defconfig | 2 +- configs/pico-imx7d_bl33_defconfig | 2 +- configs/pico-imx7d_defconfig | 2 +- configs/pico-imx8mq_defconfig | 8 +- configs/pico-nymph-imx7d_defconfig | 2 +- configs/pico-pi-imx6ul_defconfig | 2 +- configs/pico-pi-imx7d_defconfig | 2 +- configs/plutux_defconfig | 8 +- configs/pomelo_defconfig | 1 - configs/pxm2_defconfig | 6 +- configs/qemu-ppce500_defconfig | 4 +- configs/qemu-riscv32_spl_defconfig | 2 +- configs/qemu-riscv64_spl_defconfig | 2 +- configs/qemu-x86_64_defconfig | 2 +- configs/r8a77990_ebisu_defconfig | 2 +- configs/r8a77995_draak_defconfig | 2 +- configs/rastaban_defconfig | 6 +- configs/rcar3_salvator-x_defconfig | 2 +- configs/rcar3_ulcb_defconfig | 2 +- configs/ringneck-px30_defconfig | 2 +- configs/riotboard_defconfig | 4 +- configs/rock64-rk3328_defconfig | 4 +- configs/rpi_0_w_defconfig | 2 +- configs/rpi_2_defconfig | 2 +- configs/rpi_3_32b_defconfig | 2 +- configs/rpi_3_b_plus_defconfig | 2 +- configs/rpi_3_defconfig | 2 +- configs/rpi_4_32b_defconfig | 4 +- configs/rpi_4_defconfig | 4 +- configs/rpi_arm64_defconfig | 4 +- configs/rpi_defconfig | 2 +- configs/rut_defconfig | 6 +- configs/s5p4418_nanopi2_defconfig | 2 +- configs/s5p_goni_defconfig | 1 - configs/s5pc210_universal_defconfig | 1 - configs/sama5d27_giantboard_defconfig | 4 +- configs/sama5d27_som1_ek_mmc1_defconfig | 4 +- configs/sama5d27_som1_ek_mmc_defconfig | 4 +- configs/sama5d27_som1_ek_qspiflash_defconfig | 4 +- configs/sama5d27_wlsom1_ek_mmc_defconfig | 4 +- .../sama5d27_wlsom1_ek_qspiflash_defconfig | 4 +- configs/sama5d29_curiosity_mmc1_defconfig | 1 - configs/sama5d29_curiosity_mmc_defconfig | 1 - configs/sama5d2_icp_mmc_defconfig | 4 +- configs/sama5d2_xplained_emmc_defconfig | 4 +- configs/sama5d2_xplained_mmc_defconfig | 4 +- configs/sama5d2_xplained_qspiflash_defconfig | 4 +- configs/sama5d2_xplained_spiflash_defconfig | 4 +- configs/sama5d3_xplained_mmc_defconfig | 4 +- configs/sama5d3_xplained_nandflash_defconfig | 4 +- configs/sama5d3xek_mmc_defconfig | 4 +- configs/sama5d3xek_nandflash_defconfig | 4 +- configs/sama5d3xek_spiflash_defconfig | 4 +- configs/sama5d4_xplained_mmc_defconfig | 4 +- configs/sama5d4_xplained_nandflash_defconfig | 4 +- configs/sama5d4_xplained_spiflash_defconfig | 4 +- configs/sama5d4ek_mmc_defconfig | 4 +- configs/sama5d4ek_nandflash_defconfig | 4 +- configs/sama5d4ek_spiflash_defconfig | 4 +- configs/sandbox64_defconfig | 3 +- configs/sandbox_defconfig | 5 +- configs/seaboard_defconfig | 8 +- configs/seeed_npi_imx6ull_defconfig | 2 +- configs/sifive_unleashed_defconfig | 2 +- configs/sifive_unmatched_defconfig | 2 +- configs/slimbootloader_defconfig | 2 - configs/smartweb_defconfig | 4 +- configs/sniper_defconfig | 6 +- configs/socfpga_agilex_atf_defconfig | 8 +- configs/socfpga_agilex_defconfig | 8 +- configs/socfpga_agilex_vab_defconfig | 8 +- configs/socfpga_arria10_defconfig | 10 +- configs/socfpga_arria5_defconfig | 2 +- configs/socfpga_chameleonv3_defconfig | 8 +- configs/socfpga_cyclone5_defconfig | 2 +- configs/socfpga_dbm_soc1_defconfig | 2 +- configs/socfpga_de0_nano_soc_defconfig | 2 +- configs/socfpga_de10_nano_defconfig | 2 +- configs/socfpga_de10_standard_defconfig | 2 +- configs/socfpga_de1_soc_defconfig | 2 +- configs/socfpga_is1_defconfig | 2 +- configs/socfpga_mcvevk_defconfig | 2 +- configs/socfpga_n5x_atf_defconfig | 8 +- configs/socfpga_n5x_defconfig | 8 +- configs/socfpga_n5x_vab_defconfig | 8 +- configs/socfpga_sockit_defconfig | 2 +- configs/socfpga_sr1500_defconfig | 2 +- configs/socfpga_stratix10_atf_defconfig | 8 +- configs/socfpga_stratix10_defconfig | 8 +- configs/socfpga_vining_fpga_defconfig | 2 +- configs/socrates_defconfig | 2 +- configs/som-db5800-som-6867_defconfig | 1 - configs/starfive_visionfive2_defconfig | 19 +- configs/stm32746g-eval_spl_defconfig | 2 +- configs/stm32f746-disco_spl_defconfig | 2 +- configs/stm32f769-disco_spl_defconfig | 2 +- ...stm32mp15-icore-stm32mp1-ctouch2_defconfig | 8 +- ...tm32mp15-icore-stm32mp1-edimm2.2_defconfig | 8 +- ...-microgea-stm32mp1-microdev2-of7_defconfig | 8 +- ...mp15-microgea-stm32mp1-microdev2_defconfig | 8 +- configs/stm32mp15_basic_defconfig | 10 +- configs/stm32mp15_defconfig | 2 +- configs/stm32mp15_dhcom_basic_defconfig | 8 +- configs/stm32mp15_dhcor_basic_defconfig | 8 +- configs/stm32mp15_trusted_defconfig | 2 +- configs/stmark2_defconfig | 2 +- configs/syzygy_hub_defconfig | 6 +- configs/taurus_defconfig | 8 +- configs/tec-ng_defconfig | 8 +- configs/tec_defconfig | 8 +- configs/ten64_tfa_defconfig | 2 +- ...able-x86-conga-qa3-e3845-pcie-x4_defconfig | 1 - .../theadorable-x86-conga-qa3-e3845_defconfig | 1 - configs/theadorable-x86-dfi-bt700_defconfig | 1 - configs/thuban_defconfig | 6 +- configs/tools-only_defconfig | 2 +- configs/topic_miami_defconfig | 5 +- configs/topic_miamilite_defconfig | 5 +- configs/topic_miamiplus_defconfig | 5 +- configs/tqma6dl_mba6_mmc_defconfig | 2 +- configs/tqma6dl_mba6_spi_defconfig | 2 +- configs/tqma6q_mba6_mmc_defconfig | 2 +- configs/tqma6q_mba6_spi_defconfig | 2 +- configs/tqma6s_mba6_mmc_defconfig | 2 +- configs/tqma6s_mba6_spi_defconfig | 2 +- configs/transformer_t30_defconfig | 14 +- configs/trats2_defconfig | 1 - configs/trats_defconfig | 1 - configs/trimslice_defconfig | 8 +- configs/tuge1_defconfig | 4 +- configs/turris_mox_defconfig | 3 +- configs/turris_omnia_defconfig | 2 +- configs/tuxx1_defconfig | 4 +- configs/udoo_defconfig | 2 +- configs/udoo_neo_defconfig | 2 +- configs/uniphier_ld4_sld8_defconfig | 2 +- configs/uniphier_v7_defconfig | 2 +- configs/uniphier_v8_defconfig | 2 +- configs/variscite_dart6ul_defconfig | 2 +- configs/venice2_defconfig | 8 +- configs/ventana_defconfig | 8 +- configs/verdin-am62_a53_defconfig | 2 +- configs/verdin-am62_r5_defconfig | 8 +- configs/verdin-imx8mm_defconfig | 10 +- configs/verdin-imx8mp_defconfig | 10 +- configs/vining_2000_defconfig | 2 +- configs/vyasa-rk3288_defconfig | 2 +- configs/wandboard_defconfig | 2 +- configs/warp7_defconfig | 2 +- configs/x3_t30_defconfig | 14 +- configs/xenguest_arm64_defconfig | 2 +- configs/xilinx_versal_mini_qspi_defconfig | 2 +- configs/xilinx_versal_net_mini_defconfig | 2 +- configs/xilinx_versal_net_mini_qspi_defconfig | 2 +- configs/xilinx_versal_net_virt_defconfig | 2 +- configs/xilinx_versal_virt_defconfig | 2 +- configs/xilinx_zynq_virt_defconfig | 9 +- configs/xilinx_zynqmp_mini_emmc0_defconfig | 8 +- configs/xilinx_zynqmp_mini_emmc1_defconfig | 8 +- configs/xilinx_zynqmp_mini_qspi_defconfig | 10 +- configs/xilinx_zynqmp_virt_defconfig | 13 +- configs/zynq_cse_nand_defconfig | 8 +- configs/zynq_cse_nor_defconfig | 8 +- configs/zynq_cse_qspi_defconfig | 10 +- doc/arch/sandbox/sandbox.rst | 4 +- doc/develop/devicetree/control.rst | 3 + doc/develop/falcon.rst | 2 +- doc/usage/cmd/bdinfo.rst | 2 +- drivers/core/Kconfig | 14 +- drivers/core/fdtaddr.c | 6 +- drivers/core/of_access.c | 65 +++++ drivers/core/ofnode.c | 183 ++++++++++++- drivers/core/read.c | 6 +- drivers/core/util.c | 2 +- drivers/misc/cros_ec_sandbox.c | 9 +- drivers/pci/pci-uclass.c | 2 +- drivers/pci/pci_mvebu.c | 3 +- drivers/pci/pci_tegra.c | 2 +- drivers/pci/pcie_mediatek.c | 4 +- drivers/serial/Kconfig | 2 - drivers/serial/ns16550.c | 21 +- dts/Kconfig | 8 + include/asm-generic/global_data.h | 12 +- include/bloblist.h | 23 ++ include/bootstage.h | 22 ++ include/command.h | 3 + include/configs/socfpga_common.h | 2 +- include/configs/socfpga_soc64_common.h | 2 +- include/dm/device.h | 3 +- include/dm/fdtaddr.h | 3 +- include/dm/of_access.h | 18 ++ include/dm/ofnode.h | 102 ++++++- include/dm/read.h | 8 +- include/fdtdec.h | 3 +- include/ns16550.h | 4 +- include/of_live.h | 18 ++ include/serial.h | 2 + include/spl.h | 38 ++- include/system-constants.h | 20 +- lib/asm-offsets.c | 2 +- lib/fdtdec.c | 46 +++- lib/of_live.c | 141 ++++++++++ test/dm/ofnode.c | 258 ++++++++++++++++-- test/dm/pci.c | 14 +- test/lib/kconfig.c | 4 +- 684 files changed, 2689 insertions(+), 1851 deletions(-) -- 2.42.0.515.g380fc7ccd1-goog

4 47

[PATCH v5 39/43] command: Include a required header in command.h
by Simon Glass 07 Oct '23

07 Oct '23

This uses ARRAY_SIZE() but does not include the header file which declares it. Fix this, so that command.h can be included without common.h Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v5: - Adjust so this builds on azure boot/bootm.c | 2 +- include/command.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/boot/bootm.c b/boot/bootm.c index b1c3afe0a3a..8f96a80d425 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -8,6 +8,7 @@ #include <common.h> #include <bootstage.h> #include <cli.h> +#include <command.h> #include <cpu_func.h> #include <env.h> #include <errno.h> @@ -29,7 +30,6 @@ #include "mkimage.h" #endif -#include <command.h> #include <bootm.h> #include <image.h> diff --git a/include/command.h b/include/command.h index ae7bb4a30b0..34ea989b39b 100644 --- a/include/command.h +++ b/include/command.h @@ -25,6 +25,10 @@ #endif #ifndef __ASSEMBLY__ + +/* For ARRAY_SIZE() */ +#include <linux/kernel.h> + /* * Monitor Command Table */ -- 2.42.0.515.g380fc7ccd1-goog

3 2

[PATCH v2 0/6] PHYTEC SoM detection for phyCORE-i.MX8MP
by Teresa Remmet 07 Oct '23

07 Oct '23

second version of the series to add support for EEPROM SoM detection used by different PHYTEC SoMs. The EEPROM data consist of 32 bytes containing information like PCB revision, RAM size and other SoM specific configuration. For SoMs of the i.MX8M family the data is written to two areas of the used i2c EEPROM. We initally add the detection support for phyCORE-i.MX8MP. Due to layout constraints phyCORE-i.MX8MP SoMs with PCB revision 2 and older can only make use of a lower RAM frequency. This changes with the use of newer PCB revisions. We make use of the factory flashed EEPROM data to detect the PCB revision and select the fitting RAM settings. Changes in v2: - fix wrong RAM Timing values as pointed out by Yannic - removed superfluous goto - removed blank line at EOF - fix string conversion to integer - fix typo s/revsions/revisions Teresa Teresa Remmet (6): board: phytec: Add common PHYTEC SoM detection board: phytec: common: Add imx8m specific EEPROM detection support board: phytec: phycore-imx8mp: Add EEPROM detection initialisation board: phytec: phycore_imx8mp: Update 2GB RAM Timings board: phytec: common: phytec_som_detection: Add helper for PCB revision board: phytec: phycore_imx8mp: Add 4000MTS RAM timings based on PCB rev board/phytec/common/Kconfig | 13 + board/phytec/common/Makefile | 11 + board/phytec/common/imx8m_som_detection.c | 168 ++++++++++++ board/phytec/common/imx8m_som_detection.h | 54 ++++ board/phytec/common/phytec_som_detection.c | 203 ++++++++++++++ board/phytec/common/phytec_som_detection.h | 109 ++++++++ board/phytec/phycore_imx8mp/Kconfig | 1 + board/phytec/phycore_imx8mp/lpddr4_timing.c | 278 ++++++++++---------- board/phytec/phycore_imx8mp/spl.c | 78 ++++++ configs/phycore-imx8mp_defconfig | 1 + 10 files changed, 773 insertions(+), 143 deletions(-) create mode 100644 board/phytec/common/Kconfig create mode 100644 board/phytec/common/Makefile create mode 100644 board/phytec/common/imx8m_som_detection.c create mode 100644 board/phytec/common/imx8m_som_detection.h create mode 100644 board/phytec/common/phytec_som_detection.c create mode 100644 board/phytec/common/phytec_som_detection.h -- 2.34.1

3 15

[PATCH] usbarmory: Add DM_I2C and DM_SERIAL support
by Andrej Rosano 07 Oct '23

07 Oct '23

From: Andrej Rosano <andrej.rosano(a)withsecure.com> Use DM_I2C and DM_SERIAL as it is now mandatory. Signed-off-by: Andrej Rosano <andrej.rosano(a)withsecure.com> --- configs/usbarmory_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index 66c969f95e..277f055aef 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -29,7 +29,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="usbarmory" -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_IIM=y CONFIG_FSL_ESDHC_IMX=y @@ -39,6 +39,7 @@ CONFIG_PINCTRL_IMX5=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_USB_EHCI_MX5=y -- 2.42.0

2 1

[PATCH 0/2] Fixes i.MX93 11x11 EVK boot failures
by Sébastien Szymanski 07 Oct '23

07 Oct '23

This series fixes i.MX93 11x11 EVK boot failures. Sébastien Szymanski (2): arm: dts: imx93-11x11-evk: add bootph-some-ram property dm: adc: imx93-adc depends on ADC (fix boot) arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 20 ++++++++++++++++++++ configs/imx93_11x11_evk_defconfig | 1 + drivers/adc/Kconfig | 1 + 3 files changed, 22 insertions(+) -- 2.41.0

2 4

[PATCH 1/1] [u-boot][master][PATCH v5] pico-imx7d: add baseboard SD card boot detect
by egyszeregy＠freemail.hu 07 Oct '23

07 Oct '23

From: Benjamin Szőke <egyszeregy(a)freemail.hu> Take over codes from Techenxion to support mmc autodetect boot for pico-imx7d. Signed-off-by: Benjamin Szőke <egyszeregy(a)freemail.hu> --- board/technexion/pico-imx7d/pico-imx7d.c | 57 +++++++++++++++ board/technexion/pico-imx7d/spl.c | 91 ++++++++++++++++++++++-- include/configs/pico-imx7d.h | 4 +- 3 files changed, 144 insertions(+), 8 deletions(-) diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 6e98b85b28..a3fa915b49 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -5,6 +5,7 @@ #include <init.h> #include <net.h> +#include <command.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> #include <asm/arch/imx-regs.h> @@ -13,6 +14,7 @@ #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/boot_mode.h> #include <asm/io.h> #include <common.h> #include <miiphy.h> @@ -129,6 +131,49 @@ int board_phy_config(struct phy_device *phydev) } #endif +#if CONFIG_IS_ENABLED(FSL_ESDHC_IMX) +int check_mmc_autodetect(void) +{ + char *autodetect_str = env_get("mmcautodetect"); + + if ((autodetect_str) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_init(void) +{ + int dev_no = 0; + char cmd[32]; + + if (!check_mmc_autodetect()) + return; + + switch (get_boot_device()) { + case SD3_BOOT: + case MMC3_BOOT: + env_set("bootdev", "MMC3"); + dev_no = 2; + break; + case SD1_BOOT: + env_set("bootdev", "SD1"); + dev_no = 0; + break; + default: + printf("Wrong boot device!"); + } + + /* Set mmcdev env */ + env_set_ulong("mmcdev", dev_no); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); @@ -176,6 +221,12 @@ int board_late_init(void) set_wdog_reset(wdog); +#if CONFIG_IS_ENABLED(FSL_ESDHC_IMX) +#if defined(CONFIG_ENV_IS_IN_MMC) || defined(CONFIG_ENV_IS_NOWHERE) + board_late_mmc_init(); +#endif /* CONFIG_ENV_IS_IN_MMC or CONFIG_ENV_IS_NOWHERE */ +#endif + /* * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), * since we use PMIC_PWRON to reset the board. @@ -210,3 +261,9 @@ int board_ehci_hcd_init(int port) } return 0; } + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index c6b21aaa42..2fe76145be 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -15,6 +15,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch-mx7/mx7-ddr.h> #include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/boot_mode.h> #include <asm/gpio.h> #include <asm/sections.h> #include <fsl_esdhc_imx.h> @@ -159,7 +160,20 @@ void reset_cpu(void) #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) -static iomux_v3_cfg_t const usdhc3_pads[] = { +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) +/* EMMC/SD */ +static const iomux_v3_cfg_t usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14) +static const iomux_v3_cfg_t usdhc3_emmc_pads[] = { MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -173,20 +187,83 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; -static struct fsl_esdhc_cfg usdhc_cfg[1] = { +static struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR}, + {USDHC1_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { - /* Assume uSDHC3 emmc is always present */ - return 1; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); /* Assume uSDHC1 sd is always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); /* Assume uSDHC3 emmc is always present */ + break; + } + + return ret; } int board_mmc_init(struct bd_info *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + int ret; + u32 index = 0; + + /* + * Following map is done: + * (USDHC) (Physical Port) + * usdhc3 SOM MicroSD/MMC + * usdhc1 Carrier board MicroSD + * Always set boot USDHC as mmc0 + */ + + imx_iomux_v3_setup_multiple_pads(usdhc3_emmc_pads, + ARRAY_SIZE(usdhc3_emmc_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + + switch (get_boot_device()) { + case SD1_BOOT: + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + case MMC3_BOOT: + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 8; + usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + case SD3_BOOT: + default: + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + } + + for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) { + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; + } + + return 0; } #endif diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 096e5bbe66..f797bd51af 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -13,7 +13,7 @@ #define CFG_MXC_UART_BASE UART5_IPS_BASE_ADDR /* MMC Config */ -#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR #define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ @@ -79,9 +79,11 @@ "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \ "fastboot_partition_alias_system=rootfs\0" \ "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \ + "mmcautodetect=yes\0" \ PICO_BOOT_ENV #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 2) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(PXE, pxe, na) \ -- 2.42.0.windows.2

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Pull request: u-boot-rockchip-20231007
by Kever Yang 07 Oct '23

07 Oct '23

Hi Tom, Please pull the updates for rockchip platform: - Add Board: rk3568 Bananapi R2Pro; - Update pcie bifurcation support; - dwc_eth_qos controller support for rk3568 and rk3588; - Compressed binary support for U-Boot on rockchip platform; - dts and config updates for different board and soc; CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/18045 Thanks, - Kever The following changes since commit be2abe73df58a35da9e8d5afb13fccdf1b0faa8e: Merge https://source.denx.de/u-boot/custodians/u-boot-riscv (2023-10-05 13:26:44 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20231007 for you to fetch changes up to a7c86c57fb404df0a807c2ad9717c510150b8ebb: configs: rockchip: rk3308: enable CONFIG_OF_LIBFDT_OVERLAY (2023-10-07 10:48:16 +0800) ---------------------------------------------------------------- FUKAUMI Naoki (5): configs: rockchip: rock-pi-s: use default bootdelay (2s) arm: dts: rockchip: sync DT for RK3588 series with Linux arm: dts: rockchip: rock-5b: add support for PCIe3 and NVMe configs: rockchip: rk3308: use CONFIG_DEFAULT_FDT_FILE configs: rockchip: rk3308: enable CONFIG_OF_LIBFDT_OVERLAY Frank Wunderlich (1): board: rockchip: Add Bananapi R2Pro Board Jonas Karlman (19): pci: pcie_dw_rockchip: Configure number of lanes and link width speed phy: rockchip: snps-pcie3: Refactor to use clk_bulk API phy: rockchip: snps-pcie3: Refactor to use a phy_init ops phy: rockchip: snps-pcie3: Add bifurcation support for RK3568 phy: rockchip: snps-pcie3: Add support for RK3588 phy: rockchip: naneng-combphy: Use signal from comb PHY on RK3588 rockchip: rk3568-nanopi-r5: Update defconfig for NanoPi R5C and R5S rockchip: rk3568-nanopi-r5: Enable PCIe on NanoPi R5C and R5S rockchip: rk356x: Enable poweroff command power: regulator: Only run autoset once for each regulator rockchip: Port IO-domain driver for RK3568 from linux rockchip: board: Add minimal generic RK3566/RK3568 board net: dwc_eth_qos: Drop unused rx_pkt from eqos_priv net: dwc_eth_qos: Return error code when start fails net: dwc_eth_qos: Stop spam of RX packet not available message net: dwc_eth_qos: Add glue driver for GMAC on Rockchip RK3568 net: dwc_eth_qos_rockchip: Add support for RK3588 configs: rockchip: Enable ethernet driver on RK356x boards configs: rockchip: Enable ethernet driver on RK3588 boards Joseph Chen (1): regulator: rk8xx: Return correct voltage for buck converters Manoj Sai (4): spl: fit: support for booting a GZIP-compressed U-boot binary spl: fit: support for booting a LZMA-compressed U-boot binary rockchip: Add support to generate GZIP compressed U-boot binary rockchip: Add support to generate LZMA compressed U-boot binary Massimo Pegorer (3): rockchip: Kconfig: Enable external TPL binary for rk3308 doc: rockchip: Update and improve info on rk3308, TPL and TF-A configs: rockchip: add DOS_PARTITION to RK3308 boards defconfig shengfei Xu (1): regulator: rk8xx: Return correct voltage for switchout converters arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi | 19 + arch/arm/dts/rk3568-bpi-r2-pro.dts | 852 +++++++++++++++++++++ arch/arm/dts/rk3568-generic-u-boot.dtsi | 14 + arch/arm/dts/rk3568-generic.dts | 38 + arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi | 4 + arch/arm/dts/rk3568-nanopi-r5c.dts | 2 +- arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 10 +- arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 1 - arch/arm/dts/rk3588-edgeble-neu6a.dtsi | 1 - arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi | 6 - arch/arm/dts/rk3588-edgeble-neu6b-io.dts | 66 ++ arch/arm/dts/rk3588-edgeble-neu6b.dtsi | 359 ++++++++- arch/arm/dts/rk3588-evb1-v10.dts | 720 ++++++++++++++++- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 142 ++-- arch/arm/dts/rk3588-rock-5b.dts | 448 ++++++++++- arch/arm/dts/rk3588.dtsi | 215 ++++++ arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi | 12 - arch/arm/dts/rk3588s-rock-5a.dts | 665 +++++++++++++++- arch/arm/dts/rk3588s-u-boot.dtsi | 162 ---- arch/arm/dts/rk3588s.dtsi | 367 +++++++++ arch/arm/dts/rockchip-u-boot.dtsi | 11 + arch/arm/mach-rockchip/Kconfig | 3 +- board/rockchip/evb_rk3568/MAINTAINERS | 14 + common/spl/spl_fit.c | 20 +- configs/bpi-r2-pro-rk3568_defconfig | 93 +++ configs/evb-rk3308_defconfig | 3 +- configs/evb-rk3568_defconfig | 6 +- configs/evb-rk3588_defconfig | 5 +- configs/generic-rk3568_defconfig | 64 ++ configs/lubancat-2-rk3568_defconfig | 3 + configs/nanopi-r5c-rk3568_defconfig | 18 +- configs/nanopi-r5s-rk3568_defconfig | 22 +- configs/neu6a-io-rk3588_defconfig | 2 - configs/neu6b-io-rk3588_defconfig | 2 - configs/odroid-m1-rk3568_defconfig | 3 + configs/quartz64-a-rk3566_defconfig | 4 + configs/quartz64-b-rk3566_defconfig | 4 + configs/radxa-cm3-io-rk3566_defconfig | 6 +- configs/roc-cc-rk3308_defconfig | 3 +- configs/rock-3a-rk3568_defconfig | 6 +- configs/rock-pi-s-rk3308_defconfig | 5 +- configs/rock5a-rk3588s_defconfig | 5 +- configs/rock5b-rk3588_defconfig | 4 +- configs/soquartz-blade-rk3566_defconfig | 3 + configs/soquartz-cm4-rk3566_defconfig | 3 + configs/soquartz-model-a-rk3566_defconfig | 4 + doc/README.rockchip | 10 +- doc/board/rockchip/rockchip.rst | 45 +- drivers/misc/Kconfig | 9 + drivers/misc/Makefile | 1 + drivers/misc/rockchip-io-domain.c | 167 ++++ drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 33 +- drivers/net/dwc_eth_qos.h | 3 +- drivers/net/dwc_eth_qos_rockchip.c | 531 +++++++++++++ drivers/pci/pcie_dw_rockchip.c | 58 +- drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 6 + drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 230 ++++-- drivers/power/pmic/Kconfig | 1 + drivers/power/regulator/regulator-uclass.c | 18 +- drivers/power/regulator/rk8xx.c | 95 ++- include/configs/rk3308_common.h | 4 +- include/dt-bindings/ata/ahci.h | 20 + include/power/regulator.h | 1 + include/spl.h | 10 + 67 files changed, 5206 insertions(+), 465 deletions(-) create mode 100644 arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-bpi-r2-pro.dts create mode 100644 arch/arm/dts/rk3568-generic-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-generic.dts create mode 100644 configs/bpi-r2-pro-rk3568_defconfig create mode 100644 configs/generic-rk3568_defconfig create mode 100644 drivers/misc/rockchip-io-domain.c create mode 100644 drivers/net/dwc_eth_qos_rockchip.c create mode 100644 include/dt-bindings/ata/ahci.h

1 1

[PATCH 1/2] configs: rockchip: rk3308: use CONFIG_DEFAULT_FDT_FILE
by FUKAUMI Naoki 07 Oct '23

07 Oct '23

all rk3308 boards should use their own dtb file. also, change fdt_addr_r to avoid following error: "ERROR: Did not find a cmdline Flattened Device Tree" it happens on Radxa ROCK Pi S (256MB/512MB) with kernel built from Radxa BSP. Signed-off-by: FUKAUMI Naoki <naoki(a)radxa.com> --- configs/evb-rk3308_defconfig | 1 + configs/roc-cc-rk3308_defconfig | 1 + configs/rock-pi-s-rk3308_defconfig | 1 + include/configs/rk3308_common.h | 3 ++- 4 files changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index a13a809c1e..2c7ac88ed9 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -24,6 +24,7 @@ CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=0 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-evb.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x20000 diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 9a789b212f..9cb90f6ee6 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -24,6 +24,7 @@ CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=0 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-roc-cc.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x20000 diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index cc3274a98b..e2abe4b4f7 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -25,6 +25,7 @@ CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=0 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-pi-s.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x20000 diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 7d55fcd975..a413af1bd4 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -16,11 +16,12 @@ #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ - "fdt_addr_r=0x02800000\0" \ + "fdt_addr_r=0x03e00000\0" \ "kernel_addr_r=0x00680000\0" \ "ramdisk_addr_r=0x04000000\0" #define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ ENV_MEM_LAYOUT_SETTINGS \ "partitions=" PARTS_DEFAULT \ ROCKCHIP_DEVICE_SETTINGS \ -- 2.39.2

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[PATCH RESEND 1/2] arm: dts: rockchip: rk3588, rk3588s: sync with Linux
by FUKAUMI Naoki 07 Oct '23

07 Oct '23

Sync the devicetree with linux-next tag: next-20230831 Signed-off-by: FUKAUMI Naoki <naoki(a)radxa.com> --- arch/arm/dts/rk3588.dtsi | 215 +++++++++++++++++++ arch/arm/dts/rk3588s.dtsi | 367 +++++++++++++++++++++++++++++++++ include/dt-bindings/ata/ahci.h | 20 ++ 3 files changed, 602 insertions(+) create mode 100644 include/dt-bindings/ata/ahci.h diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi index 8be75556af..5519c1430c 100644 --- a/arch/arm/dts/rk3588.dtsi +++ b/arch/arm/dts/rk3588.dtsi @@ -7,6 +7,16 @@ #include "rk3588-pinctrl.dtsi" / { + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + }; + + pipe_phy1_grf: syscon@fd5c0000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -75,6 +85,159 @@ status = "disabled"; }; + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x0f>; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <3>; + msi-map = <0x0000 &its1 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; + reg = <0xa 0x40000000 0x0 0x00400000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x0 0xf0000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie3x2: pcie@fe160000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <1>; + max-link-speed = <3>; + msi-map = <0x1000 &its1 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; + reg = <0xa 0x40400000 0x0 0x00400000>, + <0x0 0xfe160000 0x0 0x00010000>, + <0x0 0xf1000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l0: pcie@fe170000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, + <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, + <0 0 0 2 &pcie2x1l0_intc 1>, + <0 0 0 3 &pcie2x1l0_intc 2>, + <0 0 0 4 &pcie2x1l0_intc 3>; + linux,pci-domain = <2>; + max-link-speed = <2>; + msi-map = <0x2000 &its0 0x2000 0x1000>; + num-lanes = <1>; + phys = <&combphy1_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; + reg = <0xa 0x40800000 0x0 0x00400000>, + <0x0 0xfe170000 0x0 0x00010000>, + <0x0 0xf2000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + gmac0: ethernet@fe1b0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1b0000 0x0 0x10000>; @@ -123,4 +286,56 @@ queue1 {}; }; }; + + sata1: sata@fe220000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe220000 0 0x1000>; + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, + <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy1_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + status = "disabled"; + }; + + pcie30phy: phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x0 0xfee80000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; + clock-names = "pclk"; + resets = <&cru SRST_PCIE30_PHY>; + reset-names = "phy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi index 7dbac9ae2e..5544f66c6f 100644 --- a/arch/arm/dts/rk3588s.dtsi +++ b/arch/arm/dts/rk3588s.dtsi @@ -8,6 +8,8 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/rk3588-power.h> #include <dt-bindings/reset/rockchip,rk3588-cru.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/ata/ahci.h> / { compatible = "rockchip,rk3588"; @@ -397,6 +399,50 @@ }; }; + usb_host0_ehci: usb@fc800000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + sys_grf: syscon@fd58c000 { compatible = "rockchip,rk3588-sys-grf", "syscon"; reg = <0x0 0xfd58c000 0x0 0x1000>; @@ -407,6 +453,66 @@ reg = <0x0 0xfd5b0000 0x0 0x1000>; }; + pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + #clock-cells = <0>; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + #clock-cells = <0>; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + ioc: syscon@fd5f0000 { compatible = "rockchip,rk3588-ioc", "syscon"; reg = <0x0 0xfd5f0000 0x0 0x10000>; @@ -830,6 +936,57 @@ }; }; + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 0>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S4_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 2>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S5_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddfc000 0x0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 23>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S9_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + qos_gpu_m0: qos@fdf35000 { compatible = "rockchip,rk3588-qos", "syscon"; reg = <0x0 0xfdf35000 0x0 0x20>; @@ -1070,6 +1227,108 @@ reg = <0x0 0xfdf82200 0x0 0x20>; }; + pcie2x1l1: pcie@fe180000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x30 0x3f>; + clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, + <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, + <0 0 0 2 &pcie2x1l1_intc 1>, + <0 0 0 3 &pcie2x1l1_intc 2>, + <0 0 0 4 &pcie2x1l1_intc 3>; + linux,pci-domain = <3>; + max-link-speed = <2>; + msi-map = <0x3000 &its0 0x3000 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, + <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; + reg = <0xa 0x40c00000 0x0 0x00400000>, + <0x0 0xfe180000 0x0 0x00010000>, + <0x0 0xf3000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x40 0x4f>; + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + max-link-speed = <2>; + msi-map = <0x4000 &its0 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0xa 0x41000000 0x0 0x00400000>, + <0x0 0xfe190000 0x0 0x00010000>, + <0x0 0xf4000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + gmac1: ethernet@fe1c0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1c0000 0x0 0x10000>; @@ -1119,6 +1378,52 @@ }; }; + sata0: sata@fe210000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe210000 0 0x1000>; + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + sata2: sata@fe230000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe230000 0 0x1000>; + interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, + <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy2_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + sdmmc: mmc@fe2c0000 { compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2c0000 0x0 0x4000>; @@ -1134,6 +1439,21 @@ status = "disabled"; }; + sdio: mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2d0000 0x00 0x4000>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + power-domains = <&power RK3588_PD_SDIO>; + status = "disabled"; + }; + sdhci: mmc@fe2e0000 { compatible = "rockchip,rk3588-dwcmshc"; reg = <0x0 0xfe2e0000 0x0 0x10000>; @@ -1145,6 +1465,9 @@ <&cru TMCLK_EMMC>; clock-names = "core", "bus", "axi", "block", "timer"; max-frequency = <200000000>; + pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, + <&emmc_cmd>, <&emmc_data_strobe>; + pinctrl-names = "default"; resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, <&cru SRST_T_EMMC>; @@ -1742,6 +2065,18 @@ status = "disabled"; }; + saradc: adc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + i2c6: i2c@fec80000 { compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xfec80000 0x0 0x1000>; @@ -1862,6 +2197,38 @@ #dma-cells = <1>; }; + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; + status = "disabled"; + }; + system_sram2: sram@ff001000 { compatible = "mmio-sram"; reg = <0x0 0xff001000 0x0 0xef000>; diff --git a/include/dt-bindings/ata/ahci.h b/include/dt-bindings/ata/ahci.h new file mode 100644 index 0000000000..b3f3b7cf9a --- /dev/null +++ b/include/dt-bindings/ata/ahci.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * This header provides constants for most AHCI bindings. + */ + +#ifndef _DT_BINDINGS_ATA_AHCI_H +#define _DT_BINDINGS_ATA_AHCI_H + +/* Host Bus Adapter generic platform capabilities */ +#define HBA_SSS (1 << 27) +#define HBA_SMPS (1 << 28) + +/* Host Bus Adapter port-specific platform capabilities */ +#define HBA_PORT_HPCP (1 << 18) +#define HBA_PORT_MPSP (1 << 19) +#define HBA_PORT_CPD (1 << 20) +#define HBA_PORT_ESP (1 << 21) +#define HBA_PORT_FBSCP (1 << 22) + +#endif -- 2.39.2

3 6

[PATCH] board: rockchip: add Pine64 QuartzPro64 RK3588 board
by Tom Fitzhenry 07 Oct '23

07 Oct '23

QuartzPro64 is a Rockchip RK3588 based SBC by Pine64. UART and booting over SD card are tested to work. Signed-off-by: Tom Fitzhenry <tom(a)tom-fitzhenry.me.uk> Cc: Eugen Hristev <eugen.hristev(a)collabora.com> Cc: Jonas Karlman <jonas(a)kwiboo.se> --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi | 21 ++++++ arch/arm/dts/rk3588-quartzpro64.dts | 32 +++++++++ arch/arm/mach-rockchip/rk3588/Kconfig | 8 +++ board/pine64/quartzpro64-rk3588/Kconfig | 15 ++++ board/pine64/quartzpro64-rk3588/MAINTAINERS | 8 +++ board/pine64/quartzpro64-rk3588/Makefile | 3 + .../quartzpro64-rk3588/quartzpro64-rk3588.c | 39 +++++++++++ configs/quartzpro64-rk3588_defconfig | 70 +++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/quartzpro64-rk3588.h | 14 ++++ 11 files changed, 213 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588-quartzpro64.dts create mode 100644 board/pine64/quartzpro64-rk3588/Kconfig create mode 100644 board/pine64/quartzpro64-rk3588/MAINTAINERS create mode 100644 board/pine64/quartzpro64-rk3588/Makefile create mode 100644 board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c create mode 100644 configs/quartzpro64-rk3588_defconfig create mode 100644 include/configs/quartzpro64-rk3588.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 85fd5b1157b..87d1b116960 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -190,7 +190,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588-edgeble-neu6b-io.dtb \ rk3588-evb1-v10.dtb \ rk3588s-rock-5a.dtb \ - rk3588-rock-5b.dtb + rk3588-rock-5b.dtb \ + rk3588-quartzpro64.dtb dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ diff --git a/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi new file mode 100644 index 00000000000..0c4cb893c35 --- /dev/null +++ b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Google, Inc + */ + +#include "rk3588-u-boot.dtsi" + +/ { + aliases { + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc; + }; +}; + +&sdmmc { + bus-width = <4>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-quartzpro64.dts b/arch/arm/dts/rk3588-quartzpro64.dts new file mode 100644 index 00000000000..d5d6849e8f8 --- /dev/null +++ b/arch/arm/dts/rk3588-quartzpro64.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Google, Inc + */ + +/dts-v1/; + +#include "rk3588.dtsi" + +/ { + model = "Pine64 QuartzPro64"; + compatible = "pine64,quartzpro64", "rockchip,rk3588"; + + aliases { + mmc1 = &sdmmc; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&sdmmc { + bus-width = <4>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 79fcc99b898..a0ebcdb2e84 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -80,6 +80,13 @@ config TARGET_ROCK5B_RK3588 USB PD over USB Type-C Size: 100mm x 72mm (Pico-ITX form factor) +config TARGET_QUARTZPRO64_RK3588 + bool "Pine64 QuartzPro64 RK3588 board" + select BOARD_LATE_INIT + help + Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board + Computer) by Pine64. + config ROCKCHIP_BOOT_MODE_REG default 0xfd588080 @@ -93,6 +100,7 @@ config SYS_MALLOC_F_LEN default 0x80000 source board/edgeble/neural-compute-module-6/Kconfig +source board/pine64/quartzpro64-rk3588/Kconfig source board/rockchip/evb_rk3588/Kconfig source board/radxa/rock5a-rk3588s/Kconfig source board/radxa/rock5b-rk3588/Kconfig diff --git a/board/pine64/quartzpro64-rk3588/Kconfig b/board/pine64/quartzpro64-rk3588/Kconfig new file mode 100644 index 00000000000..96aa7921d32 --- /dev/null +++ b/board/pine64/quartzpro64-rk3588/Kconfig @@ -0,0 +1,15 @@ +if TARGET_QUARTZPRO64_RK3588 + +config SYS_BOARD + default "quartzpro64-rk3588" + +config SYS_VENDOR + default "pine64" + +config SYS_CONFIG_NAME + default "quartzpro64-rk3588" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/pine64/quartzpro64-rk3588/MAINTAINERS b/board/pine64/quartzpro64-rk3588/MAINTAINERS new file mode 100644 index 00000000000..a7e944b7478 --- /dev/null +++ b/board/pine64/quartzpro64-rk3588/MAINTAINERS @@ -0,0 +1,8 @@ +QUARTZPRO64-RK3588 +M: Tom Fitzhenry <tom(a)tom-fitzhenry.me.uk> +S: Maintained +F: board/pine64/quartzpro64-rk3588 +F: include/configs/quartzpro64-rk3588.h +F: configs/quartzpro64-rk3588_defconfig +F: arch/arm/dts/rk3588-quartzpro64.dts +F: arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi diff --git a/board/pine64/quartzpro64-rk3588/Makefile b/board/pine64/quartzpro64-rk3588/Makefile new file mode 100644 index 00000000000..47819d9be93 --- /dev/null +++ b/board/pine64/quartzpro64-rk3588/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += quartzpro64-rk3588.o diff --git a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c new file mode 100644 index 00000000000..bda804a89e2 --- /dev/null +++ b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Google, Inc + */ + +#include <fdtdec.h> +#include <fdt_support.h> + +#ifdef CONFIG_OF_BOARD_SETUP +int quartzpro64_add_reserved_memory_fdt_nodes(void *new_blob) +{ + struct fdt_memory gap1 = { + .start = 0x3fc000000, + .end = 0x3fc4fffff, + }; + struct fdt_memory gap2 = { + .start = 0x3fff00000, + .end = 0x3ffffffff, + }; + unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; + unsigned int ret; + + /* + * Inject the reserved-memory nodes into the DTS + */ + ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, + NULL, flags); + if (ret) + return ret; + + return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, + NULL, flags); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return quartzpro64_add_reserved_memory_fdt_nodes(blob); +} +#endif diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig new file mode 100644 index 00000000000..3bcc54118b3 --- /dev/null +++ b/configs/quartzpro64-rk3588_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZPRO64_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index de9fe8e642b..c3fb8a69822 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -112,6 +112,7 @@ List of mainline supported Rockchip boards: - Rockchip EVB (evb-rk3588) - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588) - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588) + - Pine64 QuartzPro64 (quartzpro64-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B (rock5b-rk3588) diff --git a/include/configs/quartzpro64-rk3588.h b/include/configs/quartzpro64-rk3588.h new file mode 100644 index 00000000000..a1faa2aad85 --- /dev/null +++ b/include/configs/quartzpro64-rk3588.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * Copyright 2023 Google, Inc + */ + +#ifndef __QUARTZPRO64_RK3588_H +#define __QUARTZPRO64_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3588_common.h> + +#endif /* __QUARTZPRO64_RK3588_H */ base-commit: 2173c4a990664d8228d4dadd814bd64fdc12948f -- 2.42.0

2 2