October 2023 - U-Boot

[PATCH v1] spi: dw: add check for Rx FIFO overflow
by Maksim Kiselev 20 Dec '23

20 Dec '23

If even one byte is lost due to Rx FIFO overflow then we will never exit the read loop. Because the (priv->rx != priv->rx_end) condition will be always true. Let's check if Rx FIFO overflow occurred and exit the read loop in this case. Signed-off-by: Maksim Kiselev <bigunclemax(a)gmail.com> --- drivers/spi/designware_spi.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 1c7d0ca310..0f443bff8e 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -111,6 +111,15 @@ #define SR_TX_ERR BIT(5) #define SR_DCOL BIT(6) +/* Bit fields in ISR, IMR, RISR, 7 bits */ +#define DW_SPI_INT_MASK GENMASK(5, 0) +#define DW_SPI_INT_TXEI BIT(0) +#define DW_SPI_INT_TXOI BIT(1) +#define DW_SPI_INT_RXUI BIT(2) +#define DW_SPI_INT_RXOI BIT(3) +#define DW_SPI_INT_RXFI BIT(4) +#define DW_SPI_INT_MSTI BIT(5) + #define RX_TIMEOUT 1000 /* timeout in ms */ struct dw_spi_plat { @@ -588,7 +597,7 @@ static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) struct dw_spi_priv *priv = dev_get_priv(bus); u8 op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; u8 op_buf[op_len]; - u32 cr0; + u32 cr0, sts; if (read) priv->tmode = CTRLR0_TMOD_EPROMREAD; @@ -632,12 +641,21 @@ static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) * them to fail because we are not reading/writing the fifo fast enough. */ if (read) { - priv->rx = op->data.buf.in; + void *prev_rx = priv->rx = op->data.buf.in; priv->rx_end = priv->rx + op->data.nbytes; dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev)); - while (priv->rx != priv->rx_end) + while (priv->rx != priv->rx_end) { dw_reader(priv); + if (prev_rx == priv->rx) { + sts = dw_read(priv, DW_SPI_RISR); + if (sts & DW_SPI_INT_RXOI) { + dev_err(bus, "FIFO overflow on Rx\n"); + return -EIO; + } + } + prev_rx = priv->rx; + } } else { u32 val; -- 2.40.1

3 3

[RFC PATCH] mxs: Don't enable 4P2 reg if mx28 is powered only from DCDC_BATT without 5V
by Alan Kay 19 Dec '23

19 Dec '23

mxs_power_enable_4p2() was added to mxs_batt_boot() in 'commit a0f97610757d ("ARM: mxs: Enable DCDC converter for battery boot")' to enable DCDC converter when board is powered from 5V and has detected sufficient battery voltage. This involves enabling 4P2 regulator and there is a code in mxs_power_enable_4p2() that disables VDDIO, VDDA, VDDD outputs of the DCDC converter and enables BO for each power rail e.g. setbits_le32(&power_regs->hw_power_vddioctrl, POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); In case the mx28 is powered by the 5V source and linear regulators are supplying power to the VDDIO, VDDA, VDDD rails there is no issue. However if the mx28 is powered by the DCDC_BATT source only without 5V, disabling the DCDC converter outputs causes brownout power down. The proposed solution is not to call mxs_power_enable_4p2() at all if the mx28 is powered by the DCDC_BATT source only. There is no reason to enable 4P2 regulator in this case and setup of all registers is done in mxs_batt_boot(). Also there is no need to enable 5V brownout in mxs_power_init() in this case. Please consider if this is acceptable and I will submit a proper patch. Signed-off-by: Alan Kay <alan(a)londelec.com> --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index c33170f06d..c8feadce54 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -752,7 +752,9 @@ static void mxs_batt_boot(void) POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); +#ifndef CONFIG_SPL_MXS_NO_VDD5V_SOURCE mxs_power_enable_4p2(); +#endif } /** @@ -1267,7 +1269,9 @@ void mxs_power_init(void) POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); +#ifndef CONFIG_SPL_MXS_NO_VDD5V_SOURCE writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); +#endif early_delay(1000); } -- 2.25.1

4 6

[PATCH] mtd: spinand: Add support for XTX XT26xxxDxxxxx
by Bruce Suen 18 Dec '23

18 Dec '23

Add Support XTX Technology XT26G01DXXXXX, XT26G11DXXXXX, XT26Q01DXXXXX, XT26G02DXXXXX, XT26G12DXXXXX, XT26Q02DXXXXX, XT26G04DXXXXX, and XT26Q04DXXXXX SPI NAND. These are 3V/1.8V 1G/2G/4Gbit serial SLC NAND flash device with on-die ECC(8bit strength per 512bytes). Datasheet Links: - http://www.xtxtech.com/download/?AId=458 - http://www.xtxtech.com/download/?AId=495 Signed-off-by: Bruce Suen <bruce_suen(a)163.com> --- drivers/mtd/nand/spi/Makefile | 1 + drivers/mtd/nand/spi/core.c | 1 + drivers/mtd/nand/spi/xtx.c | 180 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 4 files changed, 183 insertions(+) create mode 100644 drivers/mtd/nand/spi/xtx.c diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile index 3051de4f7e..e46cfed446 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o +spinand-objs += xtx.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 597b088ca7..0b4c067425 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -828,6 +828,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { &paragon_spinand_manufacturer, &toshiba_spinand_manufacturer, &winbond_spinand_manufacturer, + &xtx_spinand_manufacturer, }; static int spinand_manufacturer_match(struct spinand_device *spinand, diff --git a/drivers/mtd/nand/spi/xtx.c b/drivers/mtd/nand/spi/xtx.c new file mode 100644 index 0000000000..ced05b5895 --- /dev/null +++ b/drivers/mtd/nand/spi/xtx.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Stefan Roese <sr(a)denx.de> + * + * Derived from drivers/mtd/nand/spi/micron.c + * Copyright (c) 2016-2017 Micron Technology, Inc. + */ + +#ifndef __UBOOT__ +#include <linux/device.h> +#include <linux/kernel.h> +#endif +#include <linux/bitfield.h> +#include <linux/mtd/spinand.h> + +#define SPINAND_MFR_XTX 0x0B + +#define XT26XXXD_STATUS_ECC3_ECC2_MASK GENMASK(7, 6) +#define XT26XXXD_STATUS_ECC_NO_DETECTED (0) +#define XT26XXXD_STATUS_ECC_1_7_CORRECTED (1) +#define XT26XXXD_STATUS_ECC_8_CORRECTED (3) +#define XT26XXXD_STATUS_ECC_UNCOR_ERROR (2) + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +static int xt26xxxd_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = mtd->oobsize / 2; + region->length = mtd->oobsize / 2; + + return 0; +} + +static int xt26xxxd_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 2; + region->length = mtd->oobsize / 2 - 2; + + return 0; +} + +static const struct mtd_ooblayout_ops xt26xxxd_ooblayout = { + .ecc = xt26xxxd_ooblayout_ecc, + .rfree = xt26xxxd_ooblayout_free, +}; + +static int xt26xxxd_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + switch (FIELD_GET(STATUS_ECC_MASK, status)) { + case XT26XXXD_STATUS_ECC_NO_DETECTED: + return 0; + case XT26XXXD_STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + case XT26XXXD_STATUS_ECC_1_7_CORRECTED: + return 4 + FIELD_GET(XT26XXXD_STATUS_ECC3_ECC2_MASK, status); + case XT26XXXD_STATUS_ECC_8_CORRECTED: + return 8; + default: + break; + } + + return -EINVAL; +} + +static const struct spinand_info xtx_spinand_table[] = { + SPINAND_INFO("XT26G01D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x31), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G11D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x34), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26Q01D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G02D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x32), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G12D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x35), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26Q02D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26G04D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x33), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), + SPINAND_INFO("XT26Q04D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x53), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&xt26xxxd_ooblayout, + xt26xxxd_ecc_get_status)), +}; + +static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = { +}; + +const struct spinand_manufacturer xtx_spinand_manufacturer = { + .id = SPINAND_MFR_XTX, + .name = "XTX", + .chips = xtx_spinand_table, + .nchips = ARRAY_SIZE(xtx_spinand_table), + .ops = &xtx_spinand_manuf_ops, +}; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index e8d6feb970..bf7696a981 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -251,6 +251,7 @@ extern const struct spinand_manufacturer micron_spinand_manufacturer; extern const struct spinand_manufacturer paragon_spinand_manufacturer; extern const struct spinand_manufacturer toshiba_spinand_manufacturer; extern const struct spinand_manufacturer winbond_spinand_manufacturer; +extern const struct spinand_manufacturer xtx_spinand_manufacturer; /** * struct spinand_op_variants - SPI NAND operation variants -- 2.34.1

2 1

[PATCH] mtd: spi: flash_is_unlocked return values fix
by Stanislav Bolshakov 18 Dec '23

18 Dec '23

In accordance with the name of the function 'flash_is_unlocked()', it is implied that the return value will be either 'true' or 'false'. Moreover, calling this function from other parts of the program is based precisely on this fact. The value of the pointer to the actual called function 'flash_is_unlocked()' depends on the memory manufacturer and can be stm_is_unlocked() or sst26_is_unlocked(). These two functions have inconsistent return values. This patch fixes this inconsistency. --- drivers/mtd/spi/spi-nor-core.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index db20feb4da..100fce624b 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1373,18 +1373,21 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) * Check if a region of the flash is (completely) unlocked. See stm_lock() for * more info. * - * Returns 1 if entire region is unlocked, 0 if any portion is locked, and - * negative on errors. + * Returns 1 if entire region is unlocked, 0 if any portion is locked or + * on errors. */ static int stm_is_unlocked(struct spi_nor *nor, loff_t ofs, uint64_t len) { int status; + int rv; status = read_sr(nor); if (status < 0) - return status; + return 0; - return stm_is_unlocked_sr(nor, ofs, len, status); + rv = stm_is_unlocked_sr(nor, ofs, len, status); + + return (rv == 1) ? 1 : 0; } #endif /* CONFIG_SPI_FLASH_STMICRO */ @@ -1617,11 +1620,13 @@ static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) } /* - * Returns EACCES (positive value) if region is (partially) locked, 0 if region - * is completely unlocked, and negative on errors. + * Returns 1 if region is completely unlocked + * and 0 on errors or if region is (partially) locked. */ static int sst26_is_unlocked(struct spi_nor *nor, loff_t ofs, uint64_t len) { + int rv; + /* * is_unlocked function is used for check before reading or erasing * flash region, so offset and length might be not 64k aligned, so @@ -1631,7 +1636,8 @@ static int sst26_is_unlocked(struct spi_nor *nor, loff_t ofs, uint64_t len) ofs -= ofs & (SZ_64K - 1); len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len; - return !sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK); + rv = sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK); + return (rv == 0) ? 1 : 0; } static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len, -- 2.30.2

2 1

[PATCH] arm: dts: imx8mm_evk: Fix PMIC definition
by Alexander Koch 15 Dec '23

15 Dec '23

Newer revisions of the i.MX8MM EVK are equipped with a different PMIC than the initial ones (PCA9540 instead of BD71847), which has already been reflected in 4c07a21e5. These changes have been reverted implicitly as part of the device tree re-sync with the Linux kernel done in 24a7a3c1c. This lead to an inconsistent state: while the device tree describes the old PMIC again the code in board/freescale/imx8mm_evk/spl.c tries to initialize the new PMIC: ret = pmic_get("pca9450@25", &dev); if (ret == -ENODEV) { puts("No pmic\n"); return 0; } This leads to the expected error message from SPL: U-Boot SPL 2023.07.02 (Sep 04 2023 - 15:57:57 +0200) -> No pmic SEC0: RNG instantiated WDT: Started watchdog@30280000 with servicing every 1000ms (60s timeout) Trying to boot from NOR NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.6-0-g15e8ff164 NOTICE: BL31: Built : 13:51:09, Sep 4 2023 Fix by re-applying the device tree changes from 4c07a21e5. Signed-off-by: Alexander Koch <akoch(a)initse.com> --- arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 +- arch/arm/dts/imx8mm-evk.dtsi | 126 ++++++++++++++-------------- 2 files changed, 67 insertions(+), 63 deletions(-) diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index 13688ec0d0..1bc7e4a38b 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -121,11 +121,11 @@ bootph-pre-ram; }; -&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { bootph-pre-ram; }; -&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi index 7d6317d95b..f2c15bf0ff 100644 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -183,114 +183,118 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450a"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; - regulator-ramp-delay = <1250>; + regulator-ramp-delay = <3125>; }; - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; + regulator-ramp-delay = <3125>; }; - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; }; - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - ldo1_reg: LDO1 { - regulator-name = "ldo1"; + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo2_reg: LDO2 { - regulator-name = "ldo2"; + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; + regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; }; }; }; -- 2.42.0

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[PATCH] spi: cadence-quadspi: Fix error message on stuck busy state
by Jan Kiszka 14 Dec '23

14 Dec '23

From: Jan Kiszka <jan.kiszka(a)siemens.com> We are not iterating CQSPI_REG_RETRY, we are waiting 'timeout' ms, since day 1. Signed-off-by: Jan Kiszka <jan.kiszka(a)siemens.com> --- We are unfortunately seeing that message right now, rarely but then prominently... drivers/spi/cadence_qspi_apb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 9ce2c0f254f..d033184aa46 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -171,8 +171,7 @@ static unsigned int cadence_qspi_wait_idle(void *reg_base) } /* Timeout, still in busy mode. */ - printf("QSPI: QSPI is still busy after poll for %d times.\n", - CQSPI_REG_RETRY); + printf("QSPI: QSPI is still busy after poll for %d ms.\n", timeout); return 0; } -- 2.35.3

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[PATCH] mtd: spi-nor-ids: add support for xtx XT55Q02G
by Bruce Suen 14 Dec '23

14 Dec '23

Add support for XTX XT55Q02G(1.8V,2Gbit). Signed-off-by: Bruce Suen <bruce_suen(a)163.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4587215984..9aab913356 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -564,6 +564,8 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("xt25q01g", 0x0b601B, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("xt55q02g", 0x0b601C, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, /* adding these wide voltage QSPI flash parts */ { INFO("xt25w512", 0x0b651A, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, -- 2.34.1

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[PATCH v2 0/1] mtd: spinand: add support for ESMT F50x1G41LB
by Igor Prusov 14 Dec '23

14 Dec '23

This series ports ESMT NAND support from Linux. Changes in v2: - Dropped detect procedure rework patch, since similar one was already applied to u-boot in commit b20913e3cb. - Updated NAND_MEMORG values, so that they are correct after mbb parameter was added in 8acaec923b. Igor Prusov (1): mtd: spinand: add support for ESMT F50x1G41LB drivers/mtd/nand/spi/Makefile | 3 +- drivers/mtd/nand/spi/core.c | 1 + drivers/mtd/nand/spi/esmt.c | 137 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 4 files changed, 141 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/spi/esmt.c -- 2.34.1

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[PATCH v1] drivers: mtd: spi: Add support for GD55LB02GEBIR SPI NOR flash
by Jit Loon Lim 14 Dec '23

14 Dec '23

From: Teik Heng Chong <teik.heng.chong(a)intel.com> Add Support for GigaDevice GD55LB02GEBIR SPI NOR flash as QSPI configuration flash Signed-off-by: Teik Heng Chong <teik.heng.chong(a)intel.com> --- drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3f8b796789..3ca46330bb 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -200,6 +200,11 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + { + INFO("gd55lb02ge", 0xc8671c, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ -- 2.26.2

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[PATCH v1] drivers: spi: Add MT25U01G part number for SPI NOR Flash
by Jit Loon Lim 14 Dec '23

14 Dec '23

MT25QU01 OPN with 4B OPCODE support is currently not supported in source code and the driver reuses the definition for "n25q00a" which has the same silicon ID but is a slower part. Adding mt25u01g definition to the source code to support a faster read response for MT25QU01 QSPI NOR Flash device. Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3ca46330bb..1b2e88cd26 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -311,6 +311,8 @@ const struct flash_info spi_nor_ids[] = { { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + { INFO6("mt25qu01g", 0x20bb21, 0x104400, 64 * 1024, 2048, SECT_4K | USE_FSR | +SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, -- 2.26.2

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