October 2023 - U-Boot

[PATCH] arm: mxs: Clear CPSR V bit to activate low vectors
by Marek Vasut 18 Oct '23

18 Oct '23

The MXS starts with CPSR V bit set, which makes the CPU jump to high vectors in case of an exception. Those high vectors are located at 0xffff0000, which is where the BootROM exception table is located as well. U-Boot should handle exceptions on its own using its own exception handling code, which is located at 0x0, i.e. at low vectors. Clear the CPSR V bit, so that the CPU would jump to low vectors on exception instead, and therefore run the U-Boot exception handling code. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: "NXP i.MX U-Boot Team" <uboot-imx(a)nxp.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Lukasz Majewski <lukma(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/cpu/arm926ejs/mxs/mxs.c | 3 +++ arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 4d21e3df76e..d64a8328b04 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -85,6 +85,9 @@ void mx28_fixup_vt(uint32_t start_addr) /* cppcheck-suppress nullPointer */ vt[i + 8] = start_addr + (4 * i); } + + /* Make sure ARM core points to low vectors */ + set_cr(get_cr() & ~CR_V); } #ifdef CONFIG_ARCH_MISC_INIT diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 5598c552ab9..4a7dfc6a2ae 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -17,6 +17,7 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/sections.h> +#include <asm/system.h> #include <linux/compiler.h> #include "mxs_init.h" @@ -104,6 +105,9 @@ static void mxs_spl_fixup_vectors(void) /* cppcheck-suppress nullPointer */ memcpy(0x0, &_start, 0x60); + + /* Make sure ARM core points to low vectors */ + set_cr(get_cr() & ~CR_V); } static void mxs_spl_console_init(void) -- 2.40.1

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[PATCH v1 0/2] arm: dts: meson-a1 Sync DT with Linux
by Igor Prusov 18 Oct '23

18 Oct '23

This series syncs Device Tree for Amlogic A1 with Linux. Currently DTS in Linix has different compatible string for serial devices, which is not recognized by serial_meson driver, so new compatible is added to driver as well. Additional driver changes are not required because new compatible only differentiates between ttyAML and ttyS names for serial console devices. Igor Prusov (2): serial: amlogic: Add UART compatible for A1 board arm: meson-a1: dts: Sync DT with Linux arch/arm/dts/meson-a1.dtsi | 356 +++++++++++++++++++++++++++++++++- drivers/serial/serial_meson.c | 1 + 2 files changed, 352 insertions(+), 5 deletions(-) -- 2.34.1

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[PATCH] phy: meson-g12a-usb2: fix ret check on power_domain_get
by Guillaume La Roque 18 Oct '23

18 Oct '23

Patch which add A1 SoC support create a regression on khadas vim3/vim3l boards when we try to use fastboot command: => fastboot usb 0 failed to get power domain failed to get power domain No USB device found USB init failed: -19 Add ENOENT check on ret in probe function. Fixes: 5533c883ce10 ("phy: support Amlogic A1 family") Signed-off-by: Guillaume La Roque <glaroque(a)baylibre.com> --- drivers/phy/meson-g12a-usb2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/phy/meson-g12a-usb2.c b/drivers/phy/meson-g12a-usb2.c index 4ba3992bda70..3958d2404b85 100644 --- a/drivers/phy/meson-g12a-usb2.c +++ b/drivers/phy/meson-g12a-usb2.c @@ -328,12 +328,12 @@ int meson_g12a_usb2_phy_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(POWER_DOMAIN) ret = power_domain_get(dev, &priv->pwrdm); - if (ret < 0 && ret != -ENODEV) { - pr_err("failed to get power domain\n"); + if (ret < 0 && ret != -ENODEV && ret != -ENOENT) { + pr_err("failed to get power domain : %d\n", ret); return ret; } - if (ret != -ENODEV) { + if (ret != -ENODEV && ret != -ENOENT) { ret = power_domain_on(&priv->pwrdm); if (ret < 0) { pr_err("failed to enable power domain\n"); -- 2.34.1

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[PATCH v2 0/6] spi-nor: Add parallel and stacked memories support
by Venkatesh Yadav Abbarapu 18 Oct '23

18 Oct '23

This series adds support for Xilinx qspi parallel and stacked memeories. In parallel mode, the current implementation assumes that a maximum of two flashes are connected. The QSPI controller splits the data evenly between both the flashes so, both the flashes that are connected in parallel mode should be identical. During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in nor->flags. In stacked mode the current implementation assumes that a maximum of two flashes are connected and both the flashes are of same make but can differ in sizes. So, except the sizes all other flash parameters of both the flashes are identical. Spi-nor will pass on the appropriate flash select flag to low level driver, and it will select pass all the data to that particular flash. Write operation in parallel mode are performed in page size * 2 chunks as each write operation results in writing both the flashes. For doubling the address space each operation is performed at addr/2 flash offset, where addr is the address specified by the user. Similarly for read and erase operations it will read from both flashes, so size and offset are divided by 2 and send to flash. Changes in v2: - Fixed the compilation issues. Ashok Reddy Soma (4): mtd: spi-nor: Add parallel and stacked memories support mtd: spi-nor: Add parallel memories support for read_sr and read_fsr mtd: spi-nor: Add parallel and stacked memories support in read_bar and write_bar spi: spi-uclass: Read chipselect and restrict capabilities Venkatesh Yadav Abbarapu (2): spi: zynqmp_gqspi: Add parallel memories support in GQSPI driver spi: zynq_qspi: Add parallel memories support in QSPI driver drivers/mtd/spi/spi-nor-core.c | 385 ++++++++++++++++++++++++++++----- drivers/spi/altera_spi.c | 4 +- drivers/spi/atcspi200_spi.c | 2 +- drivers/spi/atmel_spi.c | 6 +- drivers/spi/bcm63xx_hsspi.c | 42 ++-- drivers/spi/bcm63xx_spi.c | 6 +- drivers/spi/bcmbca_hsspi.c | 34 +-- drivers/spi/cf_spi.c | 6 +- drivers/spi/davinci_spi.c | 4 +- drivers/spi/fsl_dspi.c | 18 +- drivers/spi/fsl_espi.c | 4 +- drivers/spi/fsl_qspi.c | 4 +- drivers/spi/mpc8xxx_spi.c | 10 +- drivers/spi/mscc_bb_spi.c | 4 +- drivers/spi/mxc_spi.c | 6 +- drivers/spi/npcm_fiu_spi.c | 14 +- drivers/spi/nxp_fspi.c | 2 +- drivers/spi/omap3_spi.c | 4 +- drivers/spi/pic32_spi.c | 2 +- drivers/spi/rk_spi.c | 4 +- drivers/spi/rockchip_sfc.c | 2 +- drivers/spi/spi-aspeed-smc.c | 28 +-- drivers/spi/spi-mxic.c | 6 +- drivers/spi/spi-qup.c | 4 +- drivers/spi/spi-sifive.c | 6 +- drivers/spi/spi-sn-f-ospi.c | 2 +- drivers/spi/spi-sunxi.c | 6 +- drivers/spi/spi-synquacer.c | 4 +- drivers/spi/spi-uclass.c | 21 +- drivers/spi/stm32_qspi.c | 2 +- drivers/spi/stm32_spi.c | 4 +- drivers/spi/ti_qspi.c | 14 +- drivers/spi/xilinx_spi.c | 4 +- drivers/spi/zynq_qspi.c | 146 +++++++++++-- drivers/spi/zynq_spi.c | 6 +- drivers/spi/zynqmp_gqspi.c | 142 ++++++++++-- include/linux/mtd/spi-nor.h | 13 ++ include/spi.h | 30 ++- 38 files changed, 781 insertions(+), 220 deletions(-) -- 2.17.1

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[PATCH] timer: starfive: Add Starfive timer support
by Kuan Lim Lee 18 Oct '23

18 Oct '23

Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee(a)starfivetech.com> Reviewed-by: Wei Liang Lim <weiliang.lim(a)starfivetech.com> --- drivers/timer/Kconfig | 7 +++ drivers/timer/Makefile | 1 + drivers/timer/starfive-timer.c | 94 ++++++++++++++++++++++++++++++++++ 3 files changed, 102 insertions(+) create mode 100644 drivers/timer/starfive-timer.c diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 915b2af160..a98be9dfae 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -326,4 +326,11 @@ config XILINX_TIMER Select this to enable support for the timer found on any Xilinx boards (axi timer). +config STARFIVE_TIMER + bool "Starfive timer support" + depends on TIMER + help + Select this to enable support for the timer found on + Starfive SoC. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 1ca74805fd..1ef814970b 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -34,3 +34,4 @@ obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o +obj-$(CONFIG_STARFIVE_TIMER) += starfive-timer.o diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c new file mode 100644 index 0000000000..816402fdbf --- /dev/null +++ b/drivers/timer/starfive-timer.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 StarFive, Inc. All rights reserved. + * Author: Lee Kuan Lim <kuanlim.lee(a)starfivetech.com> + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <time.h> +#include <timer.h> +#include <asm/io.h> +#include <dm/device-internal.h> +#include <linux/err.h> + +#define STF_TIMER_INT_STATUS 0x00 +#define STF_TIMER_CTL 0x04 +#define STF_TIMER_LOAD 0x08 +#define STF_TIMER_ENABLE 0x10 +#define STF_TIMER_RELOAD 0x14 +#define STF_TIMER_VALUE 0x18 +#define STF_TIMER_INT_CLR 0x20 +#define STF_TIMER_INT_MASK 0x24 + +struct starfive_timer_priv { + void __iomem *base; + u32 timer_size; +}; + +static u64 notrace starfive_get_count(struct udevice *dev) +{ + struct starfive_timer_priv *priv = dev_get_priv(dev); + + /* Read decrement timer value and convert to increment value */ + return priv->timer_size - readl(priv->base + STF_TIMER_VALUE); +} + +static const struct timer_ops starfive_ops = { + .get_count = starfive_get_count, +}; + +static int starfive_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct starfive_timer_priv *priv = dev_get_priv(dev); + int timer_channel; + struct clk clk; + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + timer_channel = dev_read_u32_default(dev, "channel", 0); + priv->base = priv->base + (0x40 * timer_channel); + + /* Get clock rate from channel selectecd*/ + ret = clk_get_by_index(dev, timer_channel, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + uc_priv->clock_rate = clk_get_rate(&clk); + + /* Initiate timer, channel 0 */ + /* Unmask Interrupt Mask */ + writel(0, priv->base + STF_TIMER_INT_MASK); + /* Single run mode Setting */ + if (dev_read_bool(dev, "single-run")) + writel(1, priv->base + STF_TIMER_CTL); + /* Set Reload value */ + priv->timer_size = dev_read_u32_default(dev, "timer-size", 0xffffffff); + writel(priv->timer_size, priv->base + STF_TIMER_LOAD); + /* Enable to start timer */ + writel(1, priv->base + STF_TIMER_ENABLE); + + return 0; +} + +static const struct udevice_id starfive_ids[] = { + { .compatible = "starfive,jh8100-timers" }, + { } +}; + +U_BOOT_DRIVER(jh8100_starfive_timer) = { + .name = "jh8100_starfive_timer", + .id = UCLASS_TIMER, + .of_match = starfive_ids, + .probe = starfive_probe, + .ops = &starfive_ops, + .priv_auto = sizeof(struct starfive_timer_priv), +}; -- 2.34.1

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[PATCH] cros_ec: spi: disable annoying key echo on console
by Milan P. Stanić 18 Oct '23

18 Oct '23

on Peach-pi console every key press is echoed with message 'cros_ec_command: Returned status 1' this is not proper fix, just hack to disable this message --- drivers/misc/cros_ec_spi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c index 001f0a85ca..7317f4b0f1 100644 --- a/drivers/misc/cros_ec_spi.c +++ b/drivers/misc/cros_ec_spi.c @@ -151,7 +151,6 @@ int cros_ec_spi_command(struct udevice *udev, uint8_t cmd, int cmd_version, /* Response code is first byte of message */ if (p[0] != EC_RES_SUCCESS) { - printf("%s: Returned status %d\n", __func__, p[0]); return -(int)(p[0]); } -- 2.42.0

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[PATCH v4 0/8] Add rkmtd command
by Johan Jonker 18 Oct '23

18 Oct '23

The command rkmtd creates a virtual block device to transfer Rockchip boot block data to and from NAND with block orientated tools like "ums" and "rockusb". It uses the Rockchip MTD driver to scan for boot blocks and copies data from the first block in a GPT formatted virtual disk. Data must be written in U-boot "idbloader.img" format and start at partition "loader1" offset 64. The data header is parsed for length and offset. When the last sector is received it erases up to 5 erase blocks on NAND and writes boot blocks in a pattern depending on the NAND ID. Data is then verified. When a block turns out bad the block header is discarded. Changed V4: Sort includes Replace constant by define Enable rkmtd command in sandbox defconfig Fix minor things in test Changed V3: Add documetation Add test Split driver from command Split header Use devm_kzalloc Remove out of memory debug Restyle Changed V2: Rename to rkmtd Johan Jonker (8): mtd: nand: raw: rockchip_nfc: add NAND_SKIP_BBTSCAN option rockchip: dm: prepare rkmtd UCLASS rockchip: block: add rkmtd class and drivers rockchip: block: blk-uclass: disable bounce buffer support for rkmtd rockchip: cmd: add rkmtd command rockchip: test: dm: add rkmtd test rockchip: doc: add rkmtd.rst rockchip: configs: sandbox: enable rkmtd command cmd/Kconfig | 8 + cmd/Makefile | 1 + cmd/rkmtd.c | 204 +++++ configs/sandbox64_defconfig | 1 + configs/sandbox_defconfig | 1 + disk/part.c | 4 + doc/board/rockchip/index.rst | 1 + doc/board/rockchip/rkmtd.rst | 105 +++ drivers/block/Kconfig | 7 + drivers/block/Makefile | 2 + drivers/block/blk-uclass.c | 7 +- drivers/block/rkmtd.c | 1135 +++++++++++++++++++++++++++ drivers/mtd/nand/raw/Kconfig | 9 + drivers/mtd/nand/raw/rockchip_nfc.c | 3 + include/dm/uclass-id.h | 1 + include/rkmtd.h | 191 +++++ test/dm/Makefile | 1 + test/dm/rkmtd.c | 200 +++++ 18 files changed, 1878 insertions(+), 3 deletions(-) create mode 100644 cmd/rkmtd.c create mode 100644 doc/board/rockchip/rkmtd.rst create mode 100644 drivers/block/rkmtd.c create mode 100644 include/rkmtd.h create mode 100644 test/dm/rkmtd.c -- 2.39.2

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[PATCH] doc: build: update description of build dependencies for Alpine Linux
by Milan P. Stanić 18 Oct '23

18 Oct '23

--- doc/build/gcc.rst | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/doc/build/gcc.rst b/doc/build/gcc.rst index a0650a51db..e73f24a304 100644 --- a/doc/build/gcc.rst +++ b/doc/build/gcc.rst @@ -60,8 +60,28 @@ For building U-Boot on Alpine Linux at least the following packages are needed: .. code-block:: bash - apk add alpine-sdk bc bison dtc flex linux-headers ncurses-dev \ - openssl-dev perl python3 py3-setuptools python3-dev sdl2-dev + apk add alpine-sdk bc bison dtc flex gnutls-dev linux-headers \ + openssl-dev py3-elftools py3-setuptools python3-dev swig util-linux-dev + +Dependeing on the build target further packages may be needed + +For build sandbox with lcd + +.. code-block:: bash + + apk add sdl2-dev + +For build riscv64 targets + +.. code-block:: bash + + apk add opensbi + +For build some arm64 targets + +.. code-block:: bash + + apk add arm-trusted-firmware Prerequisites ------------- -- 2.42.0

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Re: failed to build u-boot mt7621_rfb_defconfig
by Fabio Estevam 18 Oct '23

18 Oct '23

[Please keep the list on Cc] On Mon, Oct 16, 2023 at 11:14 PM Xiaobo Liu <cppcoffee(a)gmail.com> wrote: > > Hi > > I found the nand rfb u-boot mt7621_stage_sram.bin, no spi-nor version was found. > > https://u-boot.readthedocs.io/en/latest/board/mediatek/mt7621.html > > Where can I find a version of the mt7621 spi-nor? I am not familiar with the Mediatek chips, but mt7621_stage_sram.bin seems to be generic, independent of the boot medium. https://u-boot.readthedocs.io/en/latest/board/mediatek/mt7621.html shows the same procedure for generating the binary. Then the last line says: "Burn the u-boot-mt7621.bin to the SPI-NOR or NAND flash." Adding the Mediatek maintainers on Cc.

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[PATCH 1/1] efi_loader: expose the device-tree file name
by Heinrich Schuchardt 18 Oct '23

18 Oct '23

Forward and backward compatibility of Linux kernel device-trees is sometimes missing. One solution approach is to load a kernel specific device-tree. This can either be done via a U-Boot scripts (like the one generated by Debian package flash-kernel or by a boot loader like GRUB. The boot loader approach currently requires to know the device-tree name before first boot which makes it unusable for generic images. Expose the device-tree file name as EFI variable FdtFile. This will allow bootloaders to load a kernel specific device-tree. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- lib/efi_loader/efi_setup.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index e6de685e87..b24feb94dc 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -26,6 +26,27 @@ void __weak allow_unaligned(void) { } +/** + * efi_init_fdtfile() - set EFI variable FdtFile + * + * Return: status code + */ +static efi_status_t efi_init_fdtfile(void) +{ + char *val; + + val = env_get("fdtfile"); + if (!val) + return EFI_SUCCESS; + + return efi_set_variable_int(u"FdtFile", + &efi_u_boot_guid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_READ_ONLY, + strlen(val) + 1, val, false); +} + /** * efi_init_platform_lang() - define supported languages * @@ -250,6 +271,11 @@ efi_status_t efi_init_obj_list(void) if (ret != EFI_SUCCESS) goto out; + /* Define EFI variable FdtFile */ + ret = efi_init_fdtfile(); + if (ret != EFI_SUCCESS) + goto out; + /* Indicate supported features */ ret = efi_init_os_indications(); if (ret != EFI_SUCCESS) -- 2.40.1

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