October 2023 - U-Boot

[PATCH v2 0/3] Add spi flash lock option
by Venkatesh Yadav Abbarapu 19 Oct '23

19 Oct '23

Disabling the flash lock option for versal and versal-net mini ospi and qspi defconfigs. Changes in v2: - Updated the commit message. - Added SPI_FLASH_LOCK in cmd/sf.c, so when disabling this option "sf protect" commands wont appear to users. Venkatesh Yadav Abbarapu (3): mtd: spi-nor: Add spi flash lock config option arm64: versal: Disable the lock option for mini ospi and qspi arm64: versal_net: Disable the lock option for mini ospi and qspi cmd/sf.c | 4 +++- configs/xilinx_versal_mini_ospi_defconfig | 3 ++- configs/xilinx_versal_mini_qspi_defconfig | 3 ++- configs/xilinx_versal_net_mini_ospi_defconfig | 3 ++- configs/xilinx_versal_net_mini_qspi_defconfig | 3 ++- drivers/mtd/spi/Kconfig | 7 +++++++ drivers/mtd/spi/spi-nor-core.c | 8 +++++++- 7 files changed, 25 insertions(+), 6 deletions(-) -- 2.17.1

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[PATCH v1] zynqmp: migrate gqspi debug to logging
by Ibai Erkiaga 19 Oct '23

19 Oct '23

The following patch migrates the usage of debug and printf functions to the relevant logging function as per U-Boot DM guidelines. Additionally some of the debugging statements have been rearanged for a more meaningfull debug experience. aarch64-linux-gnu-size reports 229 bytes less when debug is enabled at file level, while is just 5bytes more when disabled. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza(a)amd.com> --- drivers/spi/zynqmp_gqspi.c | 82 +++++++++++++++----------------------- 1 file changed, 33 insertions(+), 49 deletions(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index ec59ef5804..a323994fb2 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -5,6 +5,8 @@ * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only) */ +#define LOG_CATEGORY UCLASS_SPI + #include <common.h> #include <cpu_func.h> #include <log.h> @@ -192,8 +194,6 @@ static int zynqmp_qspi_of_to_plat(struct udevice *bus) { struct zynqmp_qspi_plat *plat = dev_get_plat(bus); - debug("%s\n", __func__); - plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) + GQSPI_REG_OFFSET); plat->dma_regs = (struct zynqmp_qspi_dma_regs *) @@ -250,7 +250,7 @@ static u32 zynqmp_qspi_genfifo_mode(u8 buswidth) case 4: return GQSPI_SPI_MODE_QSPI; default: - debug("Unsupported bus width %u\n", buswidth); + log_warning("Unsupported bus width %u\n", buswidth); return GQSPI_SPI_MODE_SPI; } } @@ -262,6 +262,8 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, u32 config_reg, ier; int ret = 0; + log_content("%s, GFIFO_CMD: 0x%X\n", __func__, gqspi_fifo_reg); + writel(gqspi_fifo_reg, &regs->genfifo); config_reg = readl(&regs->confr); @@ -278,7 +280,7 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1, GQSPI_TIMEOUT, 1); if (ret) - printf("%s Timeout\n", __func__); + log_warning("%s, Timeout\n", __func__); } @@ -286,6 +288,8 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on) { u32 gqspi_fifo_reg = 0; + log_debug("%s, assert: %d\r\n", __func__, is_on); + if (is_on) { gqspi_fifo_reg = zynqmp_qspi_bus_select(priv); gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI | @@ -295,8 +299,6 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on) gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT; } - debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg); - zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg); } @@ -311,8 +313,8 @@ static void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) clk_rate = plat->frequency; reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval)); - debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n", - __func__, reqhz, clk_rate, baudrateval); + log_debug("%s, clk_rate:%d, baudrateval:%d, bus_clk: %d\n", + __func__, clk_rate, baudrateval, reqhz); if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) || IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) { @@ -362,7 +364,8 @@ static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed) u32 confr; u8 baud_rate_val = 0; - debug("%s\n", __func__); + log_debug("%s, Speed: %d, Max: %d\n", __func__, speed, plat->frequency); + if (speed > plat->frequency) speed = plat->frequency; @@ -383,9 +386,8 @@ static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed) confr &= ~GQSPI_BAUD_DIV_MASK; confr |= (baud_rate_val << 3); writel(confr, &regs->confr); - zynqmp_qspi_set_tapdelay(bus, baud_rate_val); - debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz); + zynqmp_qspi_set_tapdelay(bus, baud_rate_val); } return 0; @@ -399,8 +401,6 @@ static int zynqmp_qspi_probe(struct udevice *bus) unsigned long clock; int ret; - debug("%s: bus:%p, priv:%p\n", __func__, bus, priv); - priv->regs = plat->regs; priv->dma_regs = plat->dma_regs; priv->io_mode = plat->io_mode; @@ -416,7 +416,6 @@ static int zynqmp_qspi_probe(struct udevice *bus) dev_err(bus, "failed to get rate\n"); return clock; } - debug("%s: CLK %ld\n", __func__, clock); ret = clk_enable(&clk); if (ret) { @@ -429,6 +428,8 @@ static int zynqmp_qspi_probe(struct udevice *bus) /* init the zynq spi hw */ zynqmp_qspi_init_hw(priv); + log_debug("%s, Rerence clock frequency: %ld\n", __func__, clock); + return 0; } @@ -438,7 +439,8 @@ static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode) struct zynqmp_qspi_regs *regs = priv->regs; u32 confr; - debug("%s\n", __func__); + log_debug("%s, 0x%X\n", __func__, mode); + /* Set the SPI Clock phase and polarities */ confr = readl(&regs->confr); confr &= ~(GQSPI_CONFIG_CPHA_MASK | GQSPI_CONFIG_CPOL_MASK); @@ -461,16 +463,11 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) u32 *buf = (u32 *)priv->tx_buf; u32 len = size; - debug("TxFIFO: 0x%x, size: 0x%x\n", readl(&regs->isr), - size); - while (size) { ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXNFULL_MASK, 1, GQSPI_TIMEOUT, 1); - if (ret) { - printf("%s: Timeout\n", __func__); - return ret; - } + if (ret) + return log_msg_ret("Timeout\n", ret); if (size >= 4) { writel(*buf, &regs->txd0r); @@ -501,10 +498,8 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1, GQSPI_TIMEOUT, 1); - if (ret) { - printf("%s: Timeout\n", __func__); - return ret; - } + if (ret) + return log_msg_ret("Timeout\n", ret); priv->tx_buf += len; return 0; @@ -516,6 +511,9 @@ static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv) u32 gen_fifo_cmd; u8 i, dummy_cycles, addr; + log_debug("%s, opcode: 0x%0X, addr.nbytes: %d, dummy.mbytes: %d\r\n", + __func__, op->cmd.opcode, op->addr.nbytes, op->dummy.nbytes); + /* Send opcode */ gen_fifo_cmd = zynqmp_qspi_bus_select(priv); gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth); @@ -532,8 +530,6 @@ static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv) gen_fifo_cmd |= GQSPI_GFIFO_TX; gen_fifo_cmd |= addr; - debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd); - zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); } @@ -583,6 +579,8 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) u32 len; int ret = 0; + log_debug("%s, length: %d\r\n", __func__, priv->len); + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK; @@ -591,8 +589,6 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); - debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd); - if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) ret = zynqmp_qspi_fill_tx_fifo(priv, 1 << len); else @@ -608,7 +604,6 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, u32 gen_fifo_cmd, u32 *buf) { u32 len; - u32 actuallen = priv->len; u32 config_reg, ier, isr; u32 timeout = GQSPI_TIMEOUT; struct zynqmp_qspi_regs *regs = priv->regs; @@ -623,7 +618,7 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, else priv->bytes_to_receive = len; zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); - debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); + /* Manual start */ config_reg = readl(&regs->confr); config_reg |= GQSPI_STRT_GEN_FIFO; @@ -652,13 +647,8 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, } } - debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n", - (unsigned long)buf, (unsigned long)priv->rx_buf, - *buf, actuallen); - if (!timeout) { - printf("IO timeout: %d\n", readl(&regs->isr)); - return -1; - } + if (!timeout) + return log_msg_retz("Timeout\n", timeout); } return 0; @@ -695,26 +685,18 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, while (priv->len) { zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); - - debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); } ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE, 1, GQSPI_TIMEOUT, 1); - if (ret) { - printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr)); - return -ETIMEDOUT; - } + if (ret) + return log_msg_ret("Timeout:\n", ret); invalidate_dcache_range(addr, addr + size); writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr); - debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n", - (unsigned long)buf, (unsigned long)priv->rx_buf, *buf, - actuallen); - if (buf != priv->rx_buf) memcpy(priv->rx_buf, buf, actuallen); @@ -731,6 +713,8 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv) u32 *buf; u32 actuallen = priv->len; + log_debug("%s, length: %d\r\n", __func__, priv->len); + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK; -- 2.42.0.325.g3a06386e31

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[PATCH] arm64: dts: zynqmp: make hw-ecc as the default ecc mode
by Michal Simek 19 Oct '23

19 Oct '23

From: Amit Kumar Mahapatra <amit.kumar-mahapatra(a)amd.com> Except for Linux no other component (i.e., u-boot, fsbl or BootRom) of the software stack supports software ecc engine. So, make hw-ecc as the default ecc mode. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra(a)amd.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 23a3ff2fed98..160c6c58b36d 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -141,8 +141,7 @@ reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "bch"; + nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; nand-ecc-step-size = <1024>; @@ -178,8 +177,7 @@ reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "bch"; + nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; -- 2.36.1

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[PATCH 0/5] arm64: xilinx: DT sync
by Michal Simek 19 Oct '23

19 Oct '23

Hi, I have found 5 more patches internally which should be also upstreamed to get DT in sync and descrease amount of differences. Thanks, Michal Michal Simek (4): arm64: zynqmp: Use mdio node by vp-x-a2785-00-revA and vpk120-revA arm64: zynqmp: Remove xlnx,zynqmp-aes node Revert "arm64: zynqmp: Add power domain description for PL" arm64: zynqmp: Remove address/size-cells from ams node Piyush Mehta (1): arm64: zynqmp: remove snps,xhci-stream-quirk property for usb arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts | 10 +++++++--- arch/arm/dts/zynqmp-vpk120-revA.dts | 10 +++++++--- arch/arm/dts/zynqmp.dtsi | 9 --------- 3 files changed, 14 insertions(+), 15 deletions(-) -- 2.36.1

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[PATCH] arm64: zynqmp: Remove fclk driver
by Michal Simek 19 Oct '23

19 Oct '23

fclk will never go upstream that's why removing this node from DT. All PL (programmable logic) based IPs should handle clocks self without using this workaround. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 5f1b0b23c124..dd4569e7bd95 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -10,12 +10,6 @@ #include <dt-bindings/clock/xlnx-zynqmp-clk.h> / { - fclk0: fclk0 { - status = "okay"; - compatible = "xlnx,fclk"; - clocks = <&zynqmp_clk PL0_REF>; - }; - pss_ref_clk: pss_ref_clk { bootph-all; compatible = "fixed-clock"; -- 2.36.1

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[PATCH] spi: cadence_ospi_versal: Add support for 64-bit address
by Venkatesh Yadav Abbarapu 19 Oct '23

19 Oct '23

When 64-bit address is passed only lower 32-bit address is getting updated. Program the upper 32-bit address in the DMA destination memory address MSBs register. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- drivers/spi/cadence_ospi_versal.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index a7685a2f51..e02a3b3de3 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -44,8 +44,10 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, priv->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE); writel(CQSPI_DFLT_DMA_PERIPH_CFG, priv->regbase + CQSPI_REG_DMA_PERIPH_CFG); - writel((unsigned long)rxbuf, priv->regbase + + writel(lower_32_bits((unsigned long)rxbuf), priv->regbase + CQSPI_DMA_DST_ADDR_REG); + writel(upper_32_bits((unsigned long)rxbuf), priv->regbase + + CQSPI_DMA_DST_ADDR_MSB_REG); writel(priv->trigger_address, priv->regbase + CQSPI_DMA_SRC_RD_ADDR_REG); writel(bytes_to_dma, priv->regbase + -- 2.17.1

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[PATCH v2] drivers: firmware: Handle error case in the zynqmp_pm_feature
by Venkatesh Yadav Abbarapu 19 Oct '23

19 Oct '23

Unhandled error coming from xilinx_pm_request() but return value is not read back that's why getting sparse warning as below: warning: variable 'ret' set but not used [-Wunused-but-set-variable]. In case of error return the "ret" value. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- Changes in v2: - Fixed the commit description. - Removed the newline. --- drivers/firmware/firmware-zynqmp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 43fb7fa778..8ea15c7ed3 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -203,6 +203,8 @@ int zynqmp_pm_feature(const u32 api_id) /* Check feature check API version */ ret = xilinx_pm_request(PM_FEATURE_CHECK, api_id, 0, 0, 0, ret_payload); + if (ret) + return ret; /* Return feature check version */ return ret_payload[1] & FIRMWARE_VERSION_MASK; -- 2.17.1

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[PATCH v8 0/2] Add support to fetch baudrate from dtb
by Venkatesh Yadav Abbarapu 19 Oct '23

19 Oct '23

In this patch series - Add support in Kconfig and convert for armada boards - Fetch baudrate from the dtb and update Changes in v8: - Added test to cover fetch_baud_from_dtb. - Changed this check_valid_baudrate() to static and removed from serial.h - Fixed the compilation error. Changes in v7: - Updated the commit message. Changes in v6: - Changed Kconfig OF_SERIAL_DT_BAUD to OF_SERIAL_BAUD. - Added IS_ENABLED() in place of #ifdef CONFIG_OF_SERIAL_AUD Changes in v5: - Adding DEFAULT_ENV_IS_RW Kconfig in missing files - Updating DEFAULT_ENV_IS_RW to CONFIG_DEFAULT_ENV_IS_RW Changes in v4: - Moved SERIAL_DT_BAUD to another patch - Added doc file for fetching serial baudrate from DT. - Changed Kconfig SERIAL_DT_BAUD to OF_SERIAL_DT_BAUD - Added function docs wherever required. - Moved changes from fdtdec api to ofnode - Changed serial_get_valid_baudrate to check_valid_baudrate - Added function fetch_baud_from_dtb to fetch baud from DT - Used dectoul() for parsing baudrate Changes in v3: - Add SERIAL_DT_BAUD to Kconfig - Moved DEFAULT_ENV_IS_RW to Kconfig also updated armada files - Moved filler changes from zynqmp.h to generic file env_default.h - Removed ENV_RW_FILLER and added padding in the generic file env_default.h. - Print baudrate parameter properly when SERIAL_DT is enabled. Changes in v2: - Changed to #ifdef from #if CONFIG_IS_ENABLED to enable patching in spl. - Added SPL_ENV_SUPPORT dependency in SERIAL_DT_BAUD to allow SPL compilation. - Moved DEFAULT_ENV_IS_RW to Kconfig also updated armada files - Moved ENV_RW_FILLER to generic file env_default.h. - Increased the ENV_RW_FILLER padding to support 8000000 baud. Algapally Santosh Sagar (2): configs: Add support in Kconfig and convert for armada boards serial: zynqmp: Fetch baudrate from dtb and update arch/sandbox/dts/test.dts | 1 + configs/eDPU_defconfig | 1 + configs/mvebu_db-88f3720_defconfig | 1 + configs/mvebu_espressobin-88f3720_defconfig | 1 + configs/uDPU_defconfig | 1 + doc/README.serial_dt_baud | 41 +++++++++++++++++ drivers/core/ofnode.c | 18 ++++++++ drivers/serial/Kconfig | 15 +++++++ drivers/serial/serial-uclass.c | 49 +++++++++++++++++++++ include/configs/mvebu_armada-37xx.h | 1 - include/dm/ofnode.h | 14 +++++- include/env_default.h | 8 +++- include/env_internal.h | 2 +- include/serial.h | 7 +++ test/dm/serial.c | 1 + 15 files changed, 155 insertions(+), 6 deletions(-) create mode 100644 doc/README.serial_dt_baud -- 2.25.1

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[PATCH v4] imx8mp-evk: Add USB0 OTG support
by Fabio Estevam 19 Oct '23

19 Oct '23

From: Fabio Estevam <festevam(a)denx.de> Add USB0 OTG support. Currently, the USB0 OTG nodes are not enabled in the Linux kernel devicetree. For this reason, enable the USB0 OTG nodes inside imx8mp-evk-u-boot.dtsi for now. Also select several useful options such as USB gadget and fastboot. Tested by running "ums 0 mmc 2". Signed-off-by: Fabio Estevam <festevam(a)denx.de> Reviewed-by: Marek Vasut <marex(a)denx.de> --- Changes since v3: - Fixed the alphabetical order once again. arch/arm/dts/imx8mp-evk-u-boot.dtsi | 13 ++++++++++++ configs/imx8mp_evk_defconfig | 31 +++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 6784ed2e7c92..f4fd2432ca8f 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -111,6 +111,19 @@ bootph-pre-ram; }; +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + &usdhc1 { bootph-pre-ram; }; diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 14c749f44308..820dc36e9cdd 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -59,6 +59,9 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y @@ -74,6 +77,14 @@ CONFIG_ETHPRIME="eth1" CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y @@ -94,10 +105,15 @@ CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_IMX=y CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y @@ -109,4 +125,19 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_MX7 is not set +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_SDP_LOADADDR=0x0 CONFIG_IMX_WATCHDOG=y -- 2.34.1

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[PATCH] riscv: Add Zbb support for building U-Boot
by Yu Chien Peter Lin 19 Oct '23

19 Oct '23

This patch adds ISA string to the -march to generate zbb instructions for U-Boot binaries, along with optimized string functions introduced from Linux kernel. Signed-off-by: Yu Chien Peter Lin <peterlin(a)andestech.com> --- arch/riscv/Kconfig | 92 +++++++++++++++++++++++++++++ arch/riscv/Makefile | 5 +- arch/riscv/include/asm/string.h | 18 ++++++ arch/riscv/lib/Makefile | 3 + arch/riscv/lib/strcmp_zbb.S | 81 +++++++++++++++++++++++++ arch/riscv/lib/strlen_zbb.S | 101 ++++++++++++++++++++++++++++++++ arch/riscv/lib/strncmp_zbb.S | 94 +++++++++++++++++++++++++++++ 7 files changed, 393 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/lib/strcmp_zbb.S create mode 100644 arch/riscv/lib/strlen_zbb.S create mode 100644 arch/riscv/lib/strncmp_zbb.S diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 867cbcbe74..49dd714e99 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -177,6 +177,98 @@ config RISCV_ISA_D riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to lp64d. +config RISCV_ISA_ZBB + bool "Zbb extension support for bit manipulation instructions" + default n + help + Adds ZBB extension (basic bit manipulation) to the ISA subsets + that the toolchain is allowed to emit when building U-Boot. + The Zbb extension provides instructions to accelerate a number + of bit-specific operations (count bit population, sign extending, + bitrotation, etc) and enables optimized string routines. + +menu "Use assembly optimized implementation of string routines" + +config USE_ARCH_STRLEN + bool "Use an assembly optimized implementation of strlen" + default y + depends on RISCV_ISA_ZBB + help + Enable the generation of an optimized version of strlen using + Zbb extension. + +config SPL_USE_ARCH_STRLEN + bool "Use an assembly optimized implementation of strlen for SPL" + default y if USE_ARCH_STRLEN + depends on RISCV_ISA_ZBB + depends on SPL + help + Enable the generation of an optimized version of strlen using + Zbb extension. + +config TPL_USE_ARCH_STRLEN + bool "Use an assembly optimized implementation of strlen for TPL" + default y if USE_ARCH_STRLEN + depends on RISCV_ISA_ZBB + depends on TPL + help + Enable the generation of an optimized version of strlen using + Zbb extension. + +config USE_ARCH_STRCMP + bool "Use an assembly optimized implementation of strcmp" + default y + depends on RISCV_ISA_ZBB + help + Enable the generation of an optimized version of strcmp using + Zbb extension. + +config SPL_USE_ARCH_STRCMP + bool "Use an assembly optimized implementation of strcmp for SPL" + default y if USE_ARCH_STRCMP + depends on RISCV_ISA_ZBB + depends on SPL + help + Enable the generation of an optimized version of strcmp using + Zbb extension. + +config TPL_USE_ARCH_STRCMP + bool "Use an assembly optimized implementation of strcmp for TPL" + default y if USE_ARCH_STRCMP + depends on RISCV_ISA_ZBB + depends on TPL + help + Enable the generation of an optimized version of strcmp using + Zbb extension. + +config USE_ARCH_STRNCMP + bool "Use an assembly optimized implementation of strncmp" + default y + depends on RISCV_ISA_ZBB + help + Enable the generation of an optimized version of strncmp using + Zbb extension. + +config SPL_USE_ARCH_STRNCMP + bool "Use an assembly optimized implementation of strncmp for SPL" + default y if USE_ARCH_STRNCMP + depends on RISCV_ISA_ZBB + depends on SPL + help + Enable the generation of an optimized version of strncmp using + Zbb extension. + +config TPL_USE_ARCH_STRNCMP + bool "Use an assembly optimized implementation of strncmp for TPL" + default y if USE_ARCH_STRNCMP + depends on RISCV_ISA_ZBB + depends on TPL + help + Enable the generation of an optimized version of strncmp using + Zbb extension. + +endmenu + config RISCV_ISA_A def_bool y diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 4963b5109b..b3ef87078b 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -24,6 +24,9 @@ endif ifeq ($(CONFIG_RISCV_ISA_C),y) ARCH_C = c endif +ifeq ($(CONFIG_RISCV_ISA_ZBB),y) + ARCH_ZBB = _zbb +endif ifeq ($(CONFIG_CMODEL_MEDLOW),y) CMODEL = medlow endif @@ -32,7 +35,7 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) endif -RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C) +RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C)$(ARCH_ZBB) ABI = $(ABI_BASE)$(ABI_D) # Newer binutils versions default to ISA spec version 20191213 which moves some diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h index 7dee3e4c9f..38ad85fe3b 100644 --- a/arch/riscv/include/asm/string.h +++ b/arch/riscv/include/asm/string.h @@ -40,4 +40,22 @@ extern void *memmove(void *, const void *, __kernel_size_t); #endif extern void *memset(void *, int, __kernel_size_t); +#undef __HAVE_ARCH_STRLEN +#if CONFIG_IS_ENABLED(USE_ARCH_STRLEN) +#define __HAVE_ARCH_STRLEN +#endif +extern __kernel_size_t strlen(const char *); + +#undef __HAVE_ARCH_STRCMP +#if CONFIG_IS_ENABLED(USE_ARCH_STRCMP) +#define __HAVE_ARCH_STRCMP +#endif +extern int strcmp(const char *, const char *); + +#undef __HAVE_ARCH_STRNCMP +#if CONFIG_IS_ENABLED(USE_ARCH_STRNCMP) +#define __HAVE_ARCH_STRNCMP +#endif +extern int strncmp(const char *, const char *, size_t __kernel_size_t); + #endif /* __ASM_RISCV_STRING_H */ diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 02c4d8fcc6..9a05b662fd 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -42,5 +42,8 @@ extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC) obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o +obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_STRLEN) += strlen_zbb.o +obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_STRCMP) += strcmp_zbb.o +obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_STRNCMP) += strncmp_zbb.o obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o diff --git a/arch/riscv/lib/strcmp_zbb.S b/arch/riscv/lib/strcmp_zbb.S new file mode 100644 index 0000000000..e5a367c0e5 --- /dev/null +++ b/arch/riscv/lib/strcmp_zbb.S @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Taken from Linux arch/riscv/lib/strcmp.S + */ + +#include <linux/linkage.h> +#include <asm/asm.h> + +ENTRY(__strcmp) +WEAK(strcmp) +.option push +.option arch,+zbb + /* + * Returns + * a0 - comparison result, value like strcmp + * + * Parameters + * a0 - string1 + * a1 - string2 + * + * Clobbers + * t0, t1, t2, t3, t4 + */ + + or t2, a0, a1 + li t4, -1 + and t2, t2, SZREG-1 + bnez t2, 3f + + /* Main loop for aligned string. */ + .p2align 3 +1: + REG_L t0, 0(a0) + REG_L t1, 0(a1) + orc.b t3, t0 + bne t3, t4, 2f + addi a0, a0, SZREG + addi a1, a1, SZREG + beq t0, t1, 1b + + /* + * Words don't match, and no null byte in the first + * word. Get bytes in big-endian order and compare. + */ +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + rev8 t0, t0 + rev8 t1, t1 +#endif + + /* Synthesize (t0 >= t1) ? 1 : -1 in a branchless sequence. */ + sltu a0, t0, t1 + neg a0, a0 + ori a0, a0, 1 + ret + +2: + /* + * Found a null byte. + * If words don't match, fall back to simple loop. + */ + bne t0, t1, 3f + + /* Otherwise, strings are equal. */ + li a0, 0 + ret + + /* Simple loop for misaligned strings. */ + .p2align 3 +3: + lbu t0, 0(a0) + lbu t1, 0(a1) + addi a0, a0, 1 + addi a1, a1, 1 + bne t0, t1, 4f + bnez t0, 3b + +4: + sub a0, t0, t1 + ret +.option pop +END(__strcmp) diff --git a/arch/riscv/lib/strlen_zbb.S b/arch/riscv/lib/strlen_zbb.S new file mode 100644 index 0000000000..bd8fa4c0bd --- /dev/null +++ b/arch/riscv/lib/strlen_zbb.S @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Taken from Linux arch/riscv/lib/strlen.S + */ + +#include <linux/linkage.h> +#include <asm/asm.h> + +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ +# define CZ ctz +# define SHIFT srl +#else +# define CZ clz +# define SHIFT sll +#endif + +ENTRY(__strlen) +WEAK(strlen) +.option push +.option arch,+zbb + /* + * Returns + * a0 - string length + * + * Parameters + * a0 - String to measure + * + * Clobbers + * t0, t1, t2, t3 + */ + + /* Number of irrelevant bytes in the first word. */ + andi t2, a0, SZREG-1 + + /* Align pointer. */ + andi t0, a0, -SZREG + + li t3, SZREG + sub t3, t3, t2 + slli t2, t2, 3 + + /* Get the first word. */ + REG_L t1, 0(t0) + + /* + * Shift away the partial data we loaded to remove the irrelevant bytes + * preceding the string with the effect of adding NUL bytes at the + * end of the string's first word. + */ + SHIFT t1, t1, t2 + + /* Convert non-NUL into 0xff and NUL into 0x00. */ + orc.b t1, t1 + + /* Convert non-NUL into 0x00 and NUL into 0xff. */ + not t1, t1 + + /* + * Search for the first set bit (corresponding to a NUL byte in the + * original chunk). + */ + CZ t1, t1 + + /* + * The first chunk is special: compare against the number + * of valid bytes in this chunk. + */ + srli a0, t1, 3 + bgtu t3, a0, 2f + + /* Prepare for the word comparison loop. */ + addi t2, t0, SZREG + li t3, -1 + + /* + * Our critical loop is 4 instructions and processes data in + * 4 byte or 8 byte chunks. + */ + .p2align 3 +1: + REG_L t1, SZREG(t0) + addi t0, t0, SZREG + orc.b t1, t1 + beq t1, t3, 1b + + not t1, t1 + CZ t1, t1 + srli t1, t1, 3 + + /* Get number of processed bytes. */ + sub t2, t0, t2 + + /* Add number of characters in the first word. */ + add a0, a0, t2 + + /* Add number of characters in the last word. */ + add a0, a0, t1 +2: + ret +.option pop +END(__strlen) diff --git a/arch/riscv/lib/strncmp_zbb.S b/arch/riscv/lib/strncmp_zbb.S new file mode 100644 index 0000000000..00e0fec3a6 --- /dev/null +++ b/arch/riscv/lib/strncmp_zbb.S @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Taken from Linux arch/riscv/lib/strncmp.S + */ + +#include <linux/linkage.h> +#include <asm/asm.h> + +ENTRY(__strncmp) +WEAK(strncmp) +.option push +.option arch,+zbb + /* + * Returns + * a0 - comparison result, like strncmp + * + * Parameters + * a0 - string1 + * a1 - string2 + * a2 - number of characters to compare + * + * Clobbers + * t0, t1, t2, t3, t4, t5, t6 + */ + + or t2, a0, a1 + li t5, -1 + and t2, t2, SZREG-1 + add t4, a0, a2 + bnez t2, 3f + + /* Adjust limit for fast-path. */ + andi t6, t4, -SZREG + + /* Main loop for aligned string. */ + .p2align 3 +1: + bge a0, t6, 3f + REG_L t0, 0(a0) + REG_L t1, 0(a1) + orc.b t3, t0 + bne t3, t5, 2f + orc.b t3, t1 + bne t3, t5, 2f + addi a0, a0, SZREG + addi a1, a1, SZREG + beq t0, t1, 1b + + /* + * Words don't match, and no null byte in the first + * word. Get bytes in big-endian order and compare. + */ +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + rev8 t0, t0 + rev8 t1, t1 +#endif + + /* Synthesize (t0 >= t1) ? 1 : -1 in a branchless sequence. */ + sltu a0, t0, t1 + neg a0, a0 + ori a0, a0, 1 + ret + +2: + /* + * Found a null byte. + * If words don't match, fall back to simple loop. + */ + bne t0, t1, 3f + + /* Otherwise, strings are equal. */ + li a0, 0 + ret + + /* Simple loop for misaligned strings. */ + .p2align 3 +3: + bge a0, t4, 5f + lbu t0, 0(a0) + lbu t1, 0(a1) + addi a0, a0, 1 + addi a1, a1, 1 + bne t0, t1, 4f + bnez t0, 3b + +4: + sub a0, t0, t1 + ret + +5: + li a0, 0 + ret +.option pop +END(__strncmp) -- 2.34.1

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