October 2023 - U-Boot

Re: [PATCH v2 30/32] fdt: Allow the devicetree to come from a bloblist
by Raymond Mao 21 Oct '23

21 Oct '23

Hi Simon, On Thu, 21 Sept 2023 at 04:58, Simon Glass <sjg(a)chromium.org> wrote: > > Standard passage provides for a bloblist to be passed from one firmware > phase to the next. That can be used to pass the devicetree along as well. > Add an option to support this. > > Tests for this will be added as part of the Universal Payload work. > > Signed-off-by: Simon Glass <sjg(a)chromium.org> > --- > > Changes in v2: > - No changes as it still seems unclear what should be done > [...] > diff --git a/include/bloblist.h b/include/bloblist.h > index 080cc46a1266..e16d122f4fb1 100644 > --- a/include/bloblist.h > +++ b/include/bloblist.h > @@ -103,6 +103,11 @@ enum bloblist_tag_t { > BLOBLISTT_ACPI_TABLES = 0x104, /* ACPI tables for x86 */ > BLOBLISTT_SMBIOS_TABLES = 0x105, /* SMBIOS tables for x86 */ > BLOBLISTT_VBOOT_CTX = 0x106, /* Chromium OS verified boot context */ > + /* > + * Devicetree for use by firmware. On some platforms this is passed to > + * the OS also > + */ > + BLOBLISTT_CONTROL_FDT = 0x107, Shall we re-define all the `BLOBLISTT_` tags according to the firmware handoff spec v0.9? According to the latest discussion (in https://github.com/FirmwareHandoff/firmware_handoff/pull/19) It is preferred that generic ones to start from `0`, and Arm specific ones starts from `0x100`. In this case, the FDT should be re-defined as `1` and other existing non-arm ones (e.g. for x86 or Chromium OS) should have their placeholder before `0xff_f000`, while generic ones (e.g. for TPM) should be placed somewhere between `0` and `0x100`. [...] Regards, Raymond

2 1

[PATCH 0/1] Fix for U-Boot SPL hang on sunxi H6 due to incorrect ram size detection
by Gunjan Gupta 21 Oct '23

21 Oct '23

On Orange Pi 3 LTS, sometimes on reboot, SPL detects ram as 4 GB instead of 2 GB. This leads to a hang later and board fails to boot. Fix is tested by leaving the device in a reboot loop overnight where device successfully rebooted 1350+ times by the time I stopped rebooting it. Gunjan Gupta (1): sunxi: dram: Fix incorrect ram size detection for some H6 boards arch/arm/mach-sunxi/dram_helpers.c | 1 + arch/arm/mach-sunxi/dram_sun50i_h6.c | 2 ++ 2 files changed, 3 insertions(+) -- 2.42.0

3 9

[PATCH 0/3] sunxi: devicetree updates from Linux v6.6
by Andre Przywara 21 Oct '23

21 Oct '23

This updates the devicetree files to match the Linux kernel repository as of v6.6-rc6. Mostly cosmetic changes, but we gain some new board files and the T113s board .dtsi files, which are needed for the pending U-Boot patches. Split per architecture, with the T113s being separate due to its RISC-V relationship. Andre Przywara (3): sunxi: dts: arm64: update devicetree files from Linux-v6.6-rc6 sunxi: dts: arm: update devicetree files from Linux-v6.6-rc6 sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6 arch/arm/dts/axp209.dtsi | 7 + arch/arm/dts/sun50i-a64.dtsi | 3 +- arch/arm/dts/sun50i-h6-pine-h64-model-b.dts | 2 +- arch/arm/dts/sun50i-h616-orangepi-zero.dtsi | 134 +++ arch/arm/dts/sun50i-h616-orangepi-zero2.dts | 121 +-- arch/arm/dts/sun50i-h616-x96-mate.dts | 2 +- arch/arm/dts/sun50i-h618-orangepi-zero3.dts | 94 ++ arch/arm/dts/sun5i-r8-chip.dts | 6 + arch/arm/dts/sun5i.dtsi | 11 +- arch/arm/dts/sun7i-a20-icnova-a20-adb4006.dts | 137 +++ arch/arm/dts/sun7i-a20-icnova-a20.dtsi | 62 ++ arch/arm/dts/sun8i-a23-a33.dtsi | 2 +- arch/arm/dts/sun8i-a83t.dtsi | 2 +- .../arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts | 35 + arch/arm/dts/sun8i-t113s.dtsi | 59 ++ arch/arm/dts/sun8i-v3s.dtsi | 2 +- arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi | 126 +++ arch/riscv/dts/sunxi-d1-t113.dtsi | 15 + arch/riscv/dts/sunxi-d1s-t113.dtsi | 927 ++++++++++++++++++ include/dt-bindings/clock/sun20i-d1-ccu.h | 158 +++ include/dt-bindings/clock/sun20i-d1-r-ccu.h | 19 + include/dt-bindings/clock/sun50i-h6-ccu.h | 2 +- include/dt-bindings/clock/sun50i-h616-ccu.h | 2 +- include/dt-bindings/clock/sun6i-rtc.h | 2 +- include/dt-bindings/reset/sun20i-d1-ccu.h | 79 ++ include/dt-bindings/reset/sun20i-d1-r-ccu.h | 16 + include/dt-bindings/reset/sun50i-h6-ccu.h | 2 +- include/dt-bindings/reset/sun50i-h6-r-ccu.h | 2 +- include/dt-bindings/reset/sun50i-h616-ccu.h | 2 +- 29 files changed, 1899 insertions(+), 132 deletions(-) create mode 100644 arch/arm/dts/sun50i-h616-orangepi-zero.dtsi create mode 100644 arch/arm/dts/sun50i-h618-orangepi-zero3.dts create mode 100644 arch/arm/dts/sun7i-a20-icnova-a20-adb4006.dts create mode 100644 arch/arm/dts/sun7i-a20-icnova-a20.dtsi create mode 100644 arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts create mode 100644 arch/arm/dts/sun8i-t113s.dtsi create mode 100644 arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi create mode 100644 arch/riscv/dts/sunxi-d1-t113.dtsi create mode 100644 arch/riscv/dts/sunxi-d1s-t113.dtsi create mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h create mode 100644 include/dt-bindings/clock/sun20i-d1-r-ccu.h create mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h create mode 100644 include/dt-bindings/reset/sun20i-d1-r-ccu.h -- 2.35.8

2 4

[PATCH v2 0/1] sunxi: H616: add LPDDR4 support
by Mikhail Kalashnikov 21 Oct '23

21 Oct '23

From: iuncuim <iuncuim(a)gmail.com> At the moment, the driver only supports DDR3 and LPDDR3 memory. Add support for a new type DRAM. These changes have been successfully tested by me with orangepi zero3 4GB (DRAM: Rayson RS1G32LO4D2BDS-53BT). This patch should be applied after this: https://lore.kernel.org/all/20231014170236.16211-1-andre.przywara@arm.com/ Changes from v1: * replaced the phy_init array with one compatible with opizero3 * added DRAM TPR6 parameter * adaptation to new mctl_phy_configure_odt() * added timings for the board orangepi zero3 4GB https://lore.kernel.org/u-boot/20230729111331.173768-2-iuncuim@gmail.com/ Signed-off-by: Mikhail Kalashnikov <iuncuim(a)gmail.com> iuncuim (1): sunxi: H616: add LPDDR4 DRAM support .../include/asm/arch-sunxi/dram_sun50i_h616.h | 2 + arch/arm/mach-sunxi/Kconfig | 16 ++ arch/arm/mach-sunxi/dram_sun50i_h616.c | 176 ++++++++++++++---- arch/arm/mach-sunxi/dram_timings/Makefile | 1 + .../dram_timings/h616_lpddr4_2133.c | 97 ++++++++++ 5 files changed, 258 insertions(+), 34 deletions(-) create mode 100644 arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c -- 2.42.0

3 3

[PATCH] arm: mvebu: AC5/AC5X: use fixed page table size
by Chris Packham 21 Oct '23

21 Oct '23

Since commit 6cdf6b7a340d ("arm64: Use FEAT_HAFDBS to track dirty pages when available") the default get_page_table_size() sets some flags for more efficient handling of dirty page table entries. This causes problems on the AC5/AC5X SoC (specifically a lockup when calling __asm_switch_ttbr() via mmu_set_region_dcache_behaviour()). The reason for the lockup isn't at all clear but it can be avoided if we provide our own get_page_table_size() which stops gd->arch.has_hafdbs from being set to true effectively returning the AC5/AC5X to the older behaviour. This also opts for a simple fixed page table size rather than trying to duplicate the more complicated logic to optimise the table size. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- arch/arm/mach-mvebu/alleycat5/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index 8204d9627515..7ba57ae75e76 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -63,6 +63,11 @@ static struct mm_region ac5_mem_map[] = { struct mm_region *mem_map = ac5_mem_map; +u64 get_page_table_size(void) +{ + return 0x80000; +} + void reset_cpu(void) { } -- 2.42.0

3 5

error on h616 ID axp806 legacy kernel
by project-tvbox project-tvbox 21 Oct '23

21 Oct '23

In the legacy kernel, when starting, the error appears: the chip id is 0x5d00 ic cant match axp, please check... well, in the axp.h code the id is defined as 0x40, I tried changing it to 0x5d00, but it does not accept the u-boot compilation error, does anyone know how to change it, it seems to be an error in the number of registers available in the .h

2 1

H616 DRAM support on mailine kernel
by project-tvbox project-tvbox 21 Oct '23

21 Oct '23

dears, How can I edit the drm parameters directly in the mainline kernel, since the mainline dts does not have these options like the legacy one, I saw that the dram.c drives in the legacy and mailline are similar, for example: [dram_para] dram_clk = 600 dram_type = 3 dram_dx_odt = 0x03030303 dram_dx_dri = 0x0e0e0e0e dram_ca_dri = 0x1f12 dram_odt_en = 1 dram_para1 = 0x30fb dram_para2 = 0x0000 dram_mr0 = 0x840 in the mainline kernel

2 1

[RFC] CTAGS prototypes
by Philip Richard Oberfichtner 20 Oct '23

20 Oct '23

Hi, is there a specific reason why the ctags make target is compiled without using '--kinds-c=+p'? Maybe it would make sense to (optionally) include that in the Makefile? I personally find it useful to jump to the header where a function is declared to view the documentary comment. Or am I missing another option to quickly get there? Regards, Philip -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-22 Fax: +49-8142-66989-80 Email: pro(a)denx.de ===================================================================== --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index e0040a40d3..7f108330a5 100644 --- a/Makefile +++ b/Makefile @@ -2085,7 +2085,7 @@ FIND := find FINDFLAGS := -L tags ctags: - ctags -w -o ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ + ctags -w -o ctags --kinds-c=+p `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ -name '*.[chS]' -print` ln -s ctags tags -- 2.42.0

2 1

[PULL] u-boot-sh/master_uart_test
by Marek Vasut 20 Oct '23

20 Oct '23

The following changes since commit e463222cce0df86f05a117f06e1737f539841fe6: Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv (2023-10-19 09:40:04 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-sh.git master_uart_test for you to fetch changes up to 966caedfa89acaeceb6968f051b7ae26c4c6673f: serial: sh: Add RZ/G2L SCIF support (2023-10-19 17:03:20 +0200) ---------------------------------------------------------------- Paul Barker (2): serial: sh: Fix error handling serial: sh: Add RZ/G2L SCIF support arch/arm/mach-rmobile/Kconfig | 1 + drivers/serial/serial_sh.c | 31 +++++++++++++++++++++++++++++-- drivers/serial/serial_sh.h | 19 ++++++++++++++++++- 3 files changed, 48 insertions(+), 3 deletions(-)

2 1

Please pull u-boot-marvell/master
by Stefan Roese 20 Oct '23

20 Oct '23

Hi Tom, please pull this next small batch of Marvell related patches: ---------------------------------------------------------------- - kirkwood: Pogo v4: Enable LTO (Tony) - mvebu: AC5/AC5X: use fixed page table size (Chris) ---------------------------------------------------------------- Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=322&view=results Thanks, Stefan The following changes since commit e463222cce0df86f05a117f06e1737f539841fe6: Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv (2023-10-19 09:40:04 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-marvell.git for you to fetch changes up to 37047b4c378d7707ffb86295c6d24ca5240a07dc: arm: mvebu: AC5/AC5X: use fixed page table size (2023-10-20 11:57:26 +0200) ---------------------------------------------------------------- Chris Packham (1): arm: mvebu: AC5/AC5X: use fixed page table size Tony Dinh (1): arm: kirkwood: Pogo v4: Enable LTO arch/arm/mach-mvebu/alleycat5/cpu.c | 5 +++++ configs/pogo_v4_defconfig | 1 + 2 files changed, 6 insertions(+)

2 4