October 2023 - U-Boot

[PATCH] dfu: add CONFIG_DFU_NAME_MAX_SIZE configuration
by Jaehoon Chung 07 Nov '23

07 Nov '23

Add CONFIG_DFU_NAME_MAX_SIZE to change the proper size. If name is longer than default size, it can do wrong behavior during updating image. So it need to change the proper maximum size. This patch is proviced the solution to change value with configuration. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/dfu/Kconfig | 9 +++++++++ include/dfu.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 8d7f13dcb0b5..a181f0b8d7ba 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -111,5 +111,14 @@ config SYS_DFU_MAX_FILE_SIZE the buffer once we've been given the whole file. Define this to the maximum filesize (in bytes) for the buffer. If undefined it defaults to the CONFIG_SYS_DFU_DATA_BUF_SIZE. + +config DFU_NAME_MAX_SIZE + int "Size of the name to be added in dfu entity" + default 32 + depends on DFU + help + This value is used to maximum size. If name is longer than default size, + we need to change the proper maximum size. + endif endmenu diff --git a/include/dfu.h b/include/dfu.h index dcb9cd9d799a..948596f367d9 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -99,7 +99,7 @@ struct virt_internal_data { int dev_num; }; -#define DFU_NAME_SIZE 32 +#define DFU_NAME_SIZE CONFIG_DFU_NAME_MAX_SIZE #ifndef DFU_DEFAULT_POLL_TIMEOUT #define DFU_DEFAULT_POLL_TIMEOUT 0 #endif -- 2.25.1

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[PATCH 0/4] mkimage: also honour -B even without external data
by Rasmus Villemoes 07 Nov '23

07 Nov '23

I was surprised to discover that mkimage effectively ignores -B when used by itself - the help text suggests otherwise, and it's a completely reasonable thing to have. Also, binman already translates a fit,align property into a -B argument, without requiring fit,external-offset to be set. Rasmus Villemoes (4): mkimage: also honour -B even without external data binman: test: rename 275_fit_align.dts -> 275_fit_align_external.dts tools: binman: add test case for fit,align without fit,external-offset binman: update documentation for fit,align property tools/binman/entries.rst | 5 +- tools/binman/ftest.py | 14 ++++- ...t_align.dts => 275_fit_align_external.dts} | 0 tools/binman/test/311_fit_align.dts | 58 +++++++++++++++++++ tools/fit_image.c | 40 +++++++++++++ 5 files changed, 112 insertions(+), 5 deletions(-) rename tools/binman/test/{275_fit_align.dts => 275_fit_align_external.dts} (100%) create mode 100644 tools/binman/test/311_fit_align.dts -- 2.37.2

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[PATCH v3] rockchip: include: asm: fix entering download mode rk3066
by Johan Jonker 07 Nov '23

07 Nov '23

Keep track of the re-entries with help of the lr register. This binary can be re-used and called from various BROM functions. Only when it's called from the part that handles SPI, NAND or EMMC hardware it needs to early return to BROM ones. In download mode when it handles data on USB OTG and UART0 this section must be skipped. Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in support to enter download mode on return to BROM. This binary must check the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set. It then returns to BROM to the end of the function that reads boot blocks. >From there the BROM code goes into a download mode and waits for data on USB OTG and UART0. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- Note: Normal U-boot flow is OK. In download mode this binary hangs after return to BROM for unknown reasons. Replace CODE471_OPTION with 30_LPDDR2_300MHz_DD.bin for now. Changed V3: Kconfig option for rk3066 only Restyle Changed V2: Move file to rk3066 specific location Replace retry_counter by LR check Add DNL mode return address Restyle Reword --- arch/arm/include/asm/arch-rk3066/boot0.h | 77 +++++++++++++++++++++++- arch/arm/mach-rockchip/Kconfig | 2 +- arch/arm/mach-rockchip/rk3066/Kconfig | 8 +++ 3 files changed, 85 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h index 28c0fb9a4c6b..6bf3828c84e9 100644 --- a/arch/arm/include/asm/arch-rk3066/boot0.h +++ b/arch/arm/include/asm/arch-rk3066/boot0.h @@ -3,6 +3,81 @@ #ifndef __ASM_ARCH_BOOT0_H__ #define __ASM_ARCH_BOOT0_H__ -#include <asm/arch-rockchip/boot0.h> +#include <asm/arch-rockchip/boot_mode.h> +/* + * Execution starts on the instruction following this 4-byte header + * (containing the magic 'RK30'). This magic constant will be written into + * the final image by the rkimage tool, but we need to reserve space for it here. + */ +#ifdef CONFIG_SPL_BUILD + b 1f /* if overwritten, entry-address is at the next word */ +1: +#endif + +#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM) +/* + * Keep track of the re-entries with help of the lr register. + * This binary can be re-used and called from various BROM functions. + * Only when it's called from the part that handles SPI, NAND or EMMC + * hardware it needs to early return to BROM ones. + * In download mode when it handles data on USB OTG and UART0 + * this section must be skipped. + */ + ldr r3, =CONFIG_ROCKCHIP_BOOT_LR_REG + cmp lr, r3 /* if (LR != CONFIG_ROCKCHIP_BOOT_LR_REG) */ + bne reset /* goto reset; */ +/* + * Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in + * support to enter download mode on return to BROM. This binary must check + * the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set. + * It then returns to BROM to the end of the function that reads boot blocks. + * From there the BROM code goes into a download mode and waits for data + * on USB OTG and UART0. + */ + ldr r2, =BOOT_BROM_DOWNLOAD + ldr r3, =CONFIG_ROCKCHIP_BOOT_MODE_REG + ldr r0, [r3] /* if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) != */ + cmp r0, r2 /* BOOT_BROM_DOWNLOAD) { */ + bne early_return /* goto early_return; */ + /* } else { */ + mov r0, #0 + str r0, [r3] /* writel(0, CONFIG_ROCKCHIP_BOOT_MODE_REG); */ + + ldr r3, =CONFIG_ROCKCHIP_BOOT_RETURN_REG + bx r3 /* return to CONFIG_ROCKCHIP_BOOT_RETURN_REG;*/ + /* } */ +early_return: + bx lr /* return to LR in BROM */ + +SAVE_SP_ADDR: + .word 0 + + .globl save_boot_params +save_boot_params: + push {r1-r12, lr} + ldr r0, =SAVE_SP_ADDR + str sp, [r0] + b save_boot_params_ret + + .globl back_to_bootrom +back_to_bootrom: + ldr r0, =SAVE_SP_ADDR + ldr sp, [r0] + mov r0, #0 + pop {r1-r12, pc} +#endif + +#if (defined(CONFIG_SPL_BUILD)) +/* U-Boot proper of armv7 does not need this */ + b reset +#endif + +/* + * For armv7, the addr '_start' will be used as vector start address + * and is written to the VBAR register, which needs to aligned to 0x20. + */ + .align(5), 0x0 +_start: + ARM_VECTORS #endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c43c185c17c5..6c56324f66bc 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -401,7 +401,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" default y - select ROCKCHIP_BROM_HELPER + select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066 select TPL_BOOTROM_SUPPORT depends on TPL help diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig index 95d7fc8a2917..4a79a829adec 100644 --- a/arch/arm/mach-rockchip/rk3066/Kconfig +++ b/arch/arm/mach-rockchip/rk3066/Kconfig @@ -10,6 +10,14 @@ config TARGET_MK808 config ROCKCHIP_BOOT_MODE_REG default 0x20004040 +config ROCKCHIP_BOOT_LR_REG + hex + default 0x00001058 + +config ROCKCHIP_BOOT_RETURN_REG + hex + default 0x00001100 + config SYS_SOC default "rk3066" -- 2.39.2

2 1

[PATCH] rockchip: dts: fix bootph tags for rv1126
by Tim Lunn 07 Nov '23

07 Nov '23

RV1126 fails to boot on 2024.01-rc1. Commit 9e64428 changed the behaviour of bootph-pre-ram, to limit nodes to spl phase. This caused rv1126 boards to fail to boot with the current dts. This patch updates the pmu/grf nodes to bootph-all tags as they are needed in all phases. This fixes the boot issue on rv1126 boards. Signed-off-by: Tim Lunn <tim(a)feathertop.org> --- arch/arm/dts/rv1126-u-boot.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi index 5e348278f2..918c307743 100644 --- a/arch/arm/dts/rv1126-u-boot.dtsi +++ b/arch/arm/dts/rv1126-u-boot.dtsi @@ -26,15 +26,15 @@ }; &grf { - bootph-pre-ram; + bootph-all; }; &pmu { - bootph-pre-ram; + bootph-all; }; &pmugrf { - bootph-pre-ram; + bootph-all; }; &xin24m { -- 2.40.1

2 1

[PATCH 0/2] rockchip: Support otp on rv1126
by Tim Lunn 07 Nov '23

07 Nov '23

This series adds support for reading the otp on rv1126 and then uses this to generate a persistant MAC address from cpuid. Tim Lunn (2): rockchip: otp: Add support for RV1126 rockchip: rv1126: Read cpuid from otp and set ethaddr arch/arm/dts/rv1126-u-boot.dtsi | 12 ++++++ arch/arm/mach-rockchip/Kconfig | 2 + drivers/misc/rockchip-otp.c | 76 +++++++++++++++++++++++++++++++++ 3 files changed, 90 insertions(+) base-commit: cbba1b7766bd93d74e28202c46e69095ac13760b -- 2.40.1

2 4

bootstd: Scanning for USB bootflow will remove existing SCSI bootflow
by Tony Dinh 07 Nov '23

07 Nov '23

Hi Simon, Here is an observation during testing the bootflow command. If there is a SCSI bootflow, scanning for USB bootflow will remove that existing SCSI bootflow. To bring it back, I scanned for SCSI bootflow again, and it was back to normal. Perhaps there is some kind of indexing problem? Please see the log below after the break. All the best, Tony =============== <BEGIN LOG> U-Boot 2023.10-rc4-tld-1-00044-g9c21b2a350-dirty (Sep 18 2023 - 12:16:59 -0700) Thecus N2350 <snip> N2350 > env def -a ## Resetting to default environment N2350 > bootflow scan scsi pcie0.0: Link down pcie1.0: Link down scanning bus for devices... SATA link 0 timeout. Target spinup took 0 ms. AHCI 0001.0000 32 slots 2 ports 6 Gbps 0x3 impl SATA mode flags: 64bit ncq led only pmp fbss pio slum part sxs Device 0: (1:0) Vendor: ATA Prod.: ST750LX003-1AC15 Rev: SM12 Type: Hard Disk Capacity: 715404.8 MB = 698.6 GB (1465149168 x 512) ** File not found /boot/boot.bmp ** N2350 > bootflow l Showing all bootflows Seq Method State Uclass Part Name Filename --- ----------- ------ -------- ---- ------------------------ ---------------- 0 script ready scsi 1 ahci_scsi.id1lun0.bootdev /boot/boot.scr --- ----------- ------ -------- ---- ------------------------ ---------------- (1 bootflow, 1 valid) N2350 > bootflow scan usb Bus usb@58000: USB EHCI 1.00 Bus usb3@f0000: MVEBU XHCI INIT controller @ 0xf10f4000 Register 2000120 NbrPorts 2 Starting the controller USB XHCI 1.00 Bus usb3@f8000: MVEBU XHCI INIT controller @ 0xf10fc000 Register 2000120 NbrPorts 2 Starting the controller USB XHCI 1.00 scanning bus usb@58000 for devices... 1 USB Device(s) found scanning bus usb3@f0000 for devices... 1 USB Device(s) found scanning bus usb3@f8000 for devices... 2 USB Device(s) found ** File not found /boot/boot.bmp ** N2350 > bootflow l Showing all bootflows Seq Method State Uclass Part Name Filename --- ----------- ------ -------- ---- ------------------------ ---------------- 0 script ready usb_mass_ 1 usb_mass_storage.lun0.boo /boot/boot.scr --- ----------- ------ -------- ---- ------------------------ ---------------- (1 bootflow, 1 valid) N2350 > bootflow scan scsi ** File not found /boot/boot.bmp ** ** File not found /boot/boot.bmp ** N2350 > bootflow l Showing all bootflows Seq Method State Uclass Part Name Filename --- ----------- ------ -------- ---- ------------------------ ---------------- 0 script ready scsi 1 ahci_scsi.id1lun0.bootdev /boot/boot.scr 1 script ready usb_mass_ 1 usb_mass_storage.lun0.boo /boot/boot.scr --- ----------- ------ -------- ---- ------------------------ ---------------- (2 bootflows, 2 valid) <END LOG>

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[PATCH] net: designware: add DMA offset awareness
by Baruch Siach 06 Nov '23

06 Nov '23

Older DesignWare Ethernet MAC versions that this driver supports can only work with 32-bit DMA source/destination addresses. Some platforms have no physical RAM at the lowest 4GB address space. For these platforms the driver must translate DMA addresses to/from physical memory addresses. Call translation routines so that properly configured platforms can use the DesignWare Ethernet MAC. For platforms using device-tree this usually means adding dma-ranges property to the bus the device node is in. Signed-off-by: Baruch Siach <baruch(a)tkos.co.il> --- drivers/net/designware.c | 31 ++++++++++++++++++++----------- drivers/net/designware.h | 1 + 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 20b86e74cecf..a174344b3ef5 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -19,6 +19,7 @@ #include <net.h> #include <pci.h> #include <reset.h> +#include <phys2bus.h> #include <asm/cache.h> #include <dm/device_compat.h> #include <dm/device-internal.h> @@ -232,8 +233,10 @@ static void tx_descs_init(struct dw_eth_dev *priv) for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; - desc_p->dmamac_addr = (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE]; - desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; + desc_p->dmamac_addr = dev_phys_to_bus(priv->dev, + (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE]); + desc_p->dmamac_next = dev_phys_to_bus(priv->dev, + (ulong)&desc_table_p[idx + 1]); #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | @@ -251,14 +254,15 @@ static void tx_descs_init(struct dw_eth_dev *priv) } /* Correcting the last pointer of the chain */ - desc_p->dmamac_next = (ulong)&desc_table_p[0]; + desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]); /* Flush all Tx buffer descriptors at once */ flush_dcache_range((ulong)priv->tx_mac_descrtable, (ulong)priv->tx_mac_descrtable + sizeof(priv->tx_mac_descrtable)); - writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); + writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]), + &dma_p->txdesclistaddr); priv->tx_currdescnum = 0; } @@ -280,8 +284,10 @@ static void rx_descs_init(struct dw_eth_dev *priv) for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; - desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE]; - desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; + desc_p->dmamac_addr = dev_phys_to_bus(priv->dev, + (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE]); + desc_p->dmamac_next = dev_phys_to_bus(priv->dev, + (ulong)&desc_table_p[idx + 1]); desc_p->dmamac_cntl = (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | @@ -291,14 +297,15 @@ static void rx_descs_init(struct dw_eth_dev *priv) } /* Correcting the last pointer of the chain */ - desc_p->dmamac_next = (ulong)&desc_table_p[0]; + desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]); /* Flush all Rx buffer descriptors at once */ flush_dcache_range((ulong)priv->rx_mac_descrtable, (ulong)priv->rx_mac_descrtable + sizeof(priv->rx_mac_descrtable)); - writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); + writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]), + &dma_p->rxdesclistaddr); priv->rx_currdescnum = 0; } @@ -448,7 +455,7 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) ulong desc_start = (ulong)desc_p; ulong desc_end = desc_start + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); - ulong data_start = desc_p->dmamac_addr; + ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr); ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); /* * Strictly we only need to invalidate the "txrx_status" field @@ -515,7 +522,7 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) ulong desc_start = (ulong)desc_p; ulong desc_end = desc_start + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); - ulong data_start = desc_p->dmamac_addr; + ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr); ulong data_end; /* Invalidate entire buffer descriptor */ @@ -532,7 +539,8 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) /* Invalidate received data */ data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); invalidate_dcache_range(data_start, data_end); - *packetp = (uchar *)(ulong)desc_p->dmamac_addr; + *packetp = (uchar *)(ulong)dev_bus_to_phys(priv->dev, + desc_p->dmamac_addr); } return length; @@ -757,6 +765,7 @@ int designware_eth_probe(struct udevice *dev) goto mdio_err; } priv->bus = miiphy_get_dev_by_name(dev->name); + priv->dev = dev; ret = dw_phy_init(priv, dev); debug("%s, ret=%d\n", __func__, ret); diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 9da4e902cb0d..918a38615ad6 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -241,6 +241,7 @@ struct dw_eth_dev { int clock_count; /* number of clock in clock list */ #endif + struct udevice *dev; struct phy_device *phydev; struct mii_dev *bus; }; -- 2.42.0

2 1

[PATCH] net: e1000: Drop e1000_eth_ids[]
by Bin Meng 06 Nov '23

06 Nov '23

e1000_eth_ids holds compatible strings for e1000 devices, but it is meaningless as e1000 is a PCI device and there is no such compatible string assigned to e1000 by the DT bindings community. Drop it. Signed-off-by: Bin Meng <bmeng(a)tinylab.org> --- drivers/net/e1000.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 41e6ba760e..84a2a7cf90 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -5718,15 +5718,9 @@ static const struct eth_ops e1000_eth_ops = { .write_hwaddr = e1000_write_hwaddr, }; -static const struct udevice_id e1000_eth_ids[] = { - { .compatible = "intel,e1000" }, - { } -}; - U_BOOT_DRIVER(eth_e1000) = { .name = "eth_e1000", .id = UCLASS_ETH, - .of_match = e1000_eth_ids, .bind = e1000_eth_bind, .probe = e1000_eth_probe, .ops = &e1000_eth_ops, -- 2.34.1

3 2

[PATCH] net: Add option for tracing packets
by Sean Anderson 06 Nov '23

06 Nov '23

Add an option to trace all packets send/received. This can be helpful when debugging protocol issues, as the packets can then be imported into wireshark [1] and analyzed further. [1] https://www.wireshark.org/docs/wsug_html_chunked/ChIOImportSection.html Signed-off-by: Sean Anderson <seanga2(a)gmail.com> --- include/net.h | 4 ++++ net/net.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/include/net.h b/include/net.h index e254df7d7f4..e63a946002d 100644 --- a/include/net.h +++ b/include/net.h @@ -16,6 +16,7 @@ #include <asm/cache.h> #include <asm/byteorder.h> /* for nton* / ntoh* stuff */ #include <env.h> +#include <hexdump.h> #include <log.h> #include <time.h> #include <linux/if_ether.h> @@ -29,6 +30,7 @@ struct udevice; #define DEBUG_DEV_PKT 0 /* Packets or info directed to the device */ #define DEBUG_NET_PKT 0 /* Packets on info on the network at large */ #define DEBUG_INT_STATE 0 /* Internal network state changes */ +#define DEBUG_NET_PKT_TRACE 0 /* Trace all packet data */ /* * The number of receive packet buffers, and the required packet buffer @@ -640,6 +642,8 @@ uchar * net_get_async_tx_pkt_buf(void); /* Transmit a packet */ static inline void net_send_packet(uchar *pkt, int len) { + if (DEBUG_NET_PKT_TRACE) + print_hex_dump_bytes("tx: ", DUMP_PREFIX_OFFSET, pkt, len); /* Currently no way to return errors from eth_send() */ (void) eth_send(pkt, len); } diff --git a/net/net.c b/net/net.c index 43abbac7c32..53eb9ef1324 100644 --- a/net/net.c +++ b/net/net.c @@ -1201,6 +1201,9 @@ void net_process_received_packet(uchar *in_packet, int len) ushort cti = 0, vlanid = VLAN_NONE, myvlanid, mynvlanid; debug_cond(DEBUG_NET_PKT, "packet received\n"); + if (DEBUG_NET_PKT_TRACE) + print_hex_dump_bytes("rx: ", DUMP_PREFIX_OFFSET, in_packet, + len); #if defined(CONFIG_CMD_PCAP) pcap_post(in_packet, len, false); -- 2.37.1

3 2

[PATCH] net: phy: TI DP83869 fix invalid clock delay configuration
by Frank de Brabander 06 Nov '23

06 Nov '23

Setting the clock delay from the device tree settings rx-internal-delay-ps and tx-internal-delay-ps was broken: - The expected value in the device tree is suppose to be a delay in picoseconds, but the driver only allowed an array index. - Driver converted this array index to the actual delay in picoseconds and tried to apply this in the device register. This however is not a valid register value. The actual logic here was reversed, it converted an register representation of the delay to the device tree delay in picoseconds. Only when the internal delays were NOT configured in the device tree and they default value of 7 (=2000ps) was used, a valid value was loaded in the register. Signed-off-by: Frank de Brabander <debrabander(a)gmail.com> --- drivers/net/phy/dp83869.c | 53 +++++++++++++++++++++++---------------- 1 file changed, 32 insertions(+), 21 deletions(-) diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index 8d32d73b07..f9d4782580 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -81,7 +81,10 @@ /* RGMIIDCTL bits */ #define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 -#define DP83869_CLK_DELAY_DEF 7 +#define DP83869_CLK_DELAY_STEP 250 +#define DP83869_CLK_DELAY_MIN 250 +#define DP83869_CLK_DELAY_MAX 4000 +#define DP83869_CLK_DELAY_DEFAULT 2000 /* CFG2 bits */ #define MII_DP83869_CFG2_SPEEDOPT_10EN 0x0040 @@ -157,10 +160,6 @@ static int dp83869_config_port_mirroring(struct phy_device *phydev) return 0; } -static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, - 1750, 2000, 2250, 2500, 2750, 3000, - 3250, 3500, 3750, 4000}; - static int dp83869_set_strapped_mode(struct phy_device *phydev) { struct dp83869_private *dp83869 = phydev->priv; @@ -183,7 +182,6 @@ static int dp83869_set_strapped_mode(struct phy_device *phydev) static int dp83869_of_init(struct phy_device *phydev) { struct dp83869_private * const dp83869 = phydev->priv; - const int delay_entries = ARRAY_SIZE(dp83869_internal_delay); int ret; ofnode node; @@ -238,32 +236,45 @@ static int dp83869_of_init(struct phy_device *phydev) dp83869->tx_fifo_depth = ofnode_read_s32_default(node, "tx-fifo-depth", DP83869_PHYCR_FIFO_DEPTH_4_B_NIB); + /* Internal clock delay values can be configured in steps of + * 250ps (0.25ns). The register field for clock delay is 4-bits wide, + * the values range from 0b0000 for 0.25ns to 0b1111 for 4ns. + */ + /* RX delay *must* be specified if internal delay of RX is used. */ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { - dp83869->rx_int_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", - DP83869_CLK_DELAY_DEF); - if (dp83869->rx_int_delay > delay_entries) { - dp83869->rx_int_delay = DP83869_CLK_DELAY_DEF; - pr_debug("rx-internal-delay-ps not set/invalid, default to %ups\n", - dp83869_internal_delay[dp83869->rx_int_delay]); + dp83869->rx_int_delay = ofnode_read_u32_default(node, + "rx-internal-delay-ps", DP83869_CLK_DELAY_DEFAULT); + if (dp83869->rx_int_delay > DP83869_CLK_DELAY_MAX || + dp83869->rx_int_delay < DP83869_CLK_DELAY_MIN || + dp83869->rx_int_delay % DP83869_CLK_DELAY_STEP) { + dp83869->rx_int_delay = DP83869_CLK_DELAY_DEFAULT; + pr_warn("rx-internal-delay-ps not set/invalid, default" + " to %ups\n", DP83869_CLK_DELAY_DEFAULT); } - dp83869->rx_int_delay = dp83869_internal_delay[dp83869->rx_int_delay]; + dp83869->rx_int_delay = + (dp83869->rx_int_delay - DP83869_CLK_DELAY_STEP) + / DP83869_CLK_DELAY_STEP; } - /* TX delay *must* be specified if internal delay of RX is used. */ + /* TX delay *must* be specified if internal delay of TX is used. */ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { - dp83869->tx_int_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", - DP83869_CLK_DELAY_DEF); - if (dp83869->tx_int_delay > delay_entries) { - dp83869->tx_int_delay = DP83869_CLK_DELAY_DEF; - pr_debug("tx-internal-delay-ps not set/invalid, default to %ups\n", - dp83869_internal_delay[dp83869->tx_int_delay]); + dp83869->tx_int_delay = ofnode_read_u32_default(node, + "tx-internal-delay-ps", DP83869_CLK_DELAY_DEFAULT); + if (dp83869->tx_int_delay > DP83869_CLK_DELAY_MAX || + dp83869->tx_int_delay < DP83869_CLK_DELAY_MIN || + dp83869->tx_int_delay % DP83869_CLK_DELAY_STEP) { + dp83869->tx_int_delay = DP83869_CLK_DELAY_DEFAULT; + pr_warn("tx-internal-delay-ps not set/invalid, default" + " to %ups\n", DP83869_CLK_DELAY_DEFAULT); } - dp83869->tx_int_delay = dp83869_internal_delay[dp83869->tx_int_delay]; + dp83869->tx_int_delay = + (dp83869->tx_int_delay - DP83869_CLK_DELAY_STEP) + / DP83869_CLK_DELAY_STEP; } return 0; -- 2.30.2

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