January 2023 - U-Boot

[PATCH 00/23] Add i.MX8ULP A1 revision support
by Ye Li 29 Mar '23

29 Mar '23

The patch set is used to support i.MX8ULP A1 revision. It includes below changes: a) XRDC/TRDC are enabled by default on A1 via DBD_EN fuse programmed. So necessary changes for XRDC setting are added. And TRDC is totally moved to RTD. A handshake is added to sync with RTD for the XRDC and TRDC setting completion. b) S400 API update and fuse update c) DDR timing and driver update d) clock setting update to match max rate restriction e) uPower API update and code clean Jacky Bai (2): ddr: imx: Update the ddr init flow on imx8ulp imx8ulp_evk: Update the DDR timing Peng Fan (3): imx: imx8ulp: upower: replace magic number with macro imx: imx8ulp: upower: make code cleaner imx8ulp_evk: disable overflow of port0 for LPAV Ye Li (18): imx: imx8ulp: Fix MU device probe failure imx: imx8ulp: Get chip revision from Sentinel imx: imx8ulp: Limit the eMMC ROM API workaround to A0.1 part imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APD imx: imx8ulp: Remove the TRDC configure from A35 imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion imx: imx8ulp: configure XRDC for DRAM access from S400 ddr: imx8ulp: Change DRAM timing save area to 0x20055000 imx: imx8ulp: Reconfigure MRC3 for SRAM0 access imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only imx: imx8ulp: Update clocks to meet max rate restrictions imx: sentinel: Update S400 API get info message structure misc: fuse: Update fuse mapping for 8ULP S400 API misc: fuse: Lock 8ULP ECC-protected fuse when programming imx8ulp_evk: Change to use DDR driver imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun imx8ulp_evk: Clear data at fdt_addr_r before booting kernel arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 1 + arch/arm/include/asm/arch-imx8ulp/rdc.h | 1 + arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 2 + arch/arm/include/asm/global_data.h | 3 + arch/arm/include/asm/mach-imx/s400_api.h | 2 + arch/arm/mach-imx/imx8ulp/Kconfig | 1 + arch/arm/mach-imx/imx8ulp/cgc.c | 70 ++++---- arch/arm/mach-imx/imx8ulp/clock.c | 50 +++--- arch/arm/mach-imx/imx8ulp/rdc.c | 71 ++++++++ arch/arm/mach-imx/imx8ulp/soc.c | 208 ++++++++++++++++++----- arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 112 +++++++++++-- board/freescale/imx8ulp_evk/Makefile | 2 +- board/freescale/imx8ulp_evk/ddr_init.c | 207 ----------------------- board/freescale/imx8ulp_evk/imx8ulp_evk.c | 16 +- board/freescale/imx8ulp_evk/lpddr4_timing.c | 210 ++++++++++++------------ board/freescale/imx8ulp_evk/lpddr4_timing_266.c | 6 +- board/freescale/imx8ulp_evk/spl.c | 18 +- drivers/ddr/imx/imx8ulp/Kconfig | 2 +- drivers/ddr/imx/imx8ulp/ddr_init.c | 55 +++++-- drivers/misc/sentinel/fuse.c | 32 +++- 20 files changed, 605 insertions(+), 464 deletions(-) delete mode 100644 board/freescale/imx8ulp_evk/ddr_init.c -- 2.7.4

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Status of dma-range issues with BCM2711
by Stefan Wahren 27 Mar '23

27 Mar '23

Hi, there has been some attempts to fix the booting issues of newer Raspberry Pi 4 (BCM2711 C0) [1] [2]. Since none of them has been applied yet, i wanted to know the status of this? Best regards [1] - https://lists.denx.de/pipermail/u-boot/2022-August/491455.html [2] - https://marc.info/?l=u-boot&m=166678304628542&w=2

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[PATCH] renesas: rcar: Apply ATF overlay for reserved-memory
by Detlev Casanova 23 Mar '23

23 Mar '23

The function fdtdec_board_setup() is only called by fdtdec_setup() which needs to be called by the board file. This is not the case for the renesas boards so rename the fdtdec_board_setup() function to a local name and call it directly from ft_board_setup(), before cleaning up the memory nodes. Signed-off-by: Detlev Casanova <detlev.casanova(a)collabora.com> --- board/renesas/rcar-common/common.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index daa1beb14f..6eaa0d1a65 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -25,14 +25,12 @@ extern u64 rcar_atf_boot_args[]; #define FDT_RPC_PATH "/soc/spi@ee200000" -int fdtdec_board_setup(const void *fdt_blob) +void apply_atf_overlay(void *fdt_blob) { void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) - fdt_overlay_apply_node((void *)fdt_blob, 0, atf_fdt_blob, 0); - - return 0; + fdt_overlay_apply_node(fdt_blob, 0, atf_fdt_blob, 0); } int dram_init(void) @@ -159,6 +157,7 @@ static void update_rpc_status(void *blob) int ft_board_setup(void *blob, struct bd_info *bd) { + apply_atf_overlay(blob); scrub_duplicate_memory(blob); update_rpc_status(blob); -- 2.38.1

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[PATCH] README.mpc85xx-sd-spi-boot: Suggest the NXP boot format github repo
by Fabio Estevam 22 Mar '23

22 Mar '23

As explained in the text at the bottom of the page https://source.codeaurora.org/external/qoriq/qoriq-yocto-sdk/boot-format: "QUIC repositories on this site will not receive any updates after March 31, 2022, and will be deleted on March 31, 2023." Point to the NXP boot format github repo instead. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- doc/README.mpc85xx-sd-spi-boot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/README.mpc85xx-sd-spi-boot b/doc/README.mpc85xx-sd-spi-boot index 329de4e6c4..7608fc3aac 100644 --- a/doc/README.mpc85xx-sd-spi-boot +++ b/doc/README.mpc85xx-sd-spi-boot @@ -14,7 +14,7 @@ Where to get boot_format: ======================== you can browse it online at: -https://source.codeaurora.org/external/qoriq/qoriq-yocto-sdk/boot-format +https://github.com/nxp-qoriq-yocto-sdk/boot-format Building ======== -- 2.25.1

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[PATCH] pci: Handle failed calloc in decode_regions()
by Pierre-Clément Tosi 22 Mar '23

22 Mar '23

Add a check for calloc() failing to allocate the requested memory. Make decode_regions() return an error code. Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stefan Roese <sr(a)denx.de> Signed-off-by: Pierre-Clément Tosi <ptosi(a)google.com> --- drivers/pci/pci-uclass.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 970ee1adf1..2c85e78a13 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -954,7 +954,7 @@ int pci_bind_bus_devices(struct udevice *bus) return 0; } -static void decode_regions(struct pci_controller *hose, ofnode parent_node, +static int decode_regions(struct pci_controller *hose, ofnode parent_node, ofnode node) { int pci_addr_cells, addr_cells, size_cells; @@ -968,7 +968,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, prop = ofnode_get_property(node, "ranges", &len); if (!prop) { debug("%s: Cannot decode regions\n", __func__); - return; + return -EINVAL; } pci_addr_cells = ofnode_read_simple_addr_cells(node); @@ -986,6 +986,8 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS; hose->regions = (struct pci_region *) calloc(1, max_regions * sizeof(struct pci_region)); + if (!hose->regions) + return -ENOMEM; for (i = 0; i < max_regions; i++, len -= cells_per_record) { u64 pci_addr, addr, size; @@ -1053,7 +1055,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, /* Add a region for our local memory */ bd = gd->bd; if (!bd) - return; + return 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { if (bd->bi_dram[i].size) { @@ -1068,7 +1070,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, } } - return; + return 0; } static int pci_uclass_pre_probe(struct udevice *bus) @@ -1097,7 +1099,10 @@ static int pci_uclass_pre_probe(struct udevice *bus) /* For bridges, use the top-level PCI controller */ if (!device_is_on_pci_bus(bus)) { hose->ctlr = bus; - decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus)); + ret = decode_regions(hose, dev_ofnode(bus->parent), + dev_ofnode(bus)); + if (ret) + return ret; } else { struct pci_controller *parent_hose; -- 2.36.1.124.g0e6072fb45-goog

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kwboot: Marvell Dove UART booting
by Tony Dinh 20 Mar '23

20 Mar '23

Hi all, With great help from Pali, I've made some good progress on kwboot the HP Thin Client T5335z (Marvell Dove SoC) board. I had been unsuccessful running kwboot with this box until Pali pointed out a few important aspects of the Dove SoC, and how the BootROM commands work (my apology for forgetting to include the u-boot-mailing list and Marek on previous email exchanges). Here is the summary of the attempt to kwboot. HP Thin Client T5335z Marvell Dove SoC 88AP510 (A1) 1Ghz CPU 1 GB RAM - Reset Strapping: As with all Dove SoCs, there is no preamble when we send the u-boot image over the serial line. IOW, no magic handshake string to tell the BootROM that we are booting over UART. Instead, the hardware must explicitly set to UART mode booting. For boards like the Solidrun Cubox, there is a button, and some other board, a DIP switch, to enable this mode. For the T55335z, there is no button or DIP switch on the board for that purpose. Instead, there is a jumper (the exact purpose is unknown), but I found that this jumper will put the BootROM into debug mode. And from the BootROM debug prompt, we can execute a command to set the boot mode to UART with "x command. Here is the log and my commentary starting with *** <Begin log> *** With jumper inserted, serial console connected, start serial console # picocom --b 115200 --f n --p n --d 8 /dev/ttyUSB0 Terminal ready *** Hit <Enter> here to get to the prompt and execute "x 0x0E" Bootstrap 2.33> Bootstrap 2.33>x 0x0E *** No more input possible here, so Control-A-X to exit serial console Terminating... Thanks for using picocom *** Run kwboot # kwboot -t -p -B 115200 /dev/ttyUSB0 -D /localdisk/mtd0.t5335z Patching image boot signature to UART Aligning image header to Xmodem block size Waiting 2s and flushing tty Sending boot image header (512 bytes)... 25 % [.... ] Done Sending boot image data (607664 bytes)... 0 % [......................................................................] 1 % [......................................................................] 2 % [......................................................................] <snip> 95 % [......................................................................] 97 % [......................................................................] 98 % [.......................................................... ] Done Finishing transfer [Type Ctrl-\ + c to quit] *** Hung here! BootROM did not execute the image payload. *** *** The file mtd0.t5335z is a dd dump from the SPI flash mtd0 with *** this command: *** # dd if=/dev/mtd0 of=mtd0.t5335z bs=768k conv=sync <End log> - Pali's observation: It looks like Dove uses kwbimage v0 format with extensions, at least according to Function Spec. See 'Binary Code Extension' and 'Header Extension'. Currently kwboot and kwbimage supports v0 image only with one extension. - My comments in response: Indeed. I've seen that in the Functional Spec, too. The mdt0 binwalk also shows what looks like the extension header. DECIMAL HEXADECIMAL DESCRIPTION -------------------------------------------------------------------------------- 118161 0x1CD91 Certificate in DER format (x509 v3), header length: 4, sequence length: 3 199169 0x30A01 Certificate in DER format (x509 v3), header length: 4, sequence length: 5464 380652 0x5CEEC CRC32 polynomial table, little endian 387072 0x5E800 CRC32 polynomial table, little endian 608166 0x947A6 LZMA compressed data, properties: 0x66, dictionary size: 0 bytes, uncompressed size: 147351982848 bytes Thanks, Tony

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[PATCH] dfu: mtd: mark bad the MTD block on erase error
by Patrick Delaunay 17 Mar '23

17 Mar '23

In the MTD DFU backend, it is needed to mark the NAND block bad when the erase failed with the -EIO error, as it is done in UBI and JFFS2 code. This operation is not done in the MTD framework, but the bad block tag (in BBM or in BBT) is required to avoid to write data on this block in the next DFU_OP_WRITE loop in mtd_block_op(): the code skip the bad blocks, tested by mtd_block_isbad(). Without this patch, when the NAND block become bad on DFU write operation - low probability on new NAND - the DFU write operation will always failed because the failing block is never marked bad. This patch also adds a test to avoid to request an erase operation on a block already marked bad; this test is not performed in MTD framework in mtd_erase(). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/dfu/dfu_mtd.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c index c7075f12eca9..4fb02c4c806c 100644 --- a/drivers/dfu/dfu_mtd.c +++ b/drivers/dfu/dfu_mtd.c @@ -91,22 +91,32 @@ static int mtd_block_op(enum dfu_op op, struct dfu_entity *dfu, return -EIO; } + /* Skip the block if it is bad, don't erase it again */ + if (mtd_block_isbad(mtd, off)) { + erase_op.addr += mtd->erasesize; + continue; + } + ret = mtd_erase(mtd, &erase_op); if (ret) { - /* Abort if its not a bad block error */ - if (ret != -EIO) { - printf("Failure while erasing at offset 0x%llx\n", - erase_op.fail_addr); - return 0; + /* If this is not -EIO, we have no idea what to do. */ + if (ret == -EIO) { + printf("Marking bad block at 0x%08llx (%d)\n", + erase_op.fail_addr, ret); + ret = mtd_block_markbad(mtd, erase_op.addr); + } + /* Abort if it is not -EIO or can't mark bad */ + if (ret) { + printf("Failure while erasing at offset 0x%llx (%d)\n", + erase_op.fail_addr, ret); + return ret; } - printf("Skipping bad block at 0x%08llx\n", - erase_op.addr); } else { remaining -= mtd->erasesize; } - /* Continue erase behind bad block */ + /* Continue erase behind the current block */ erase_op.addr += mtd->erasesize; } } -- 2.25.1

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[PATCH] board_r: Relocate OF_EMBED if NEEDS_MANUAL_RELOC only
by Pierre-Clément Tosi 16 Mar '23

16 Mar '23

When the embedded device tree is pointed to by the __dtb_dt_*begin symbols, it seems to be covered by the early relocation code and doesn't need to be manually patched. Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Pierre-Clément Tosi <ptosi(a)google.com> --- common/board_r.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/board_r.c b/common/board_r.c index 56eb60fa27..00926dcb1e 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -150,13 +150,13 @@ static int initr_reloc_global_data(void) */ gd->env_addr += gd->reloc_off; #endif -#ifdef CONFIG_OF_EMBED /* * The fdt_blob needs to be moved to new relocation address * incase of FDT blob is embedded with in image */ - gd->fdt_blob += gd->reloc_off; -#endif + if (CONFIG_IS_ENABLED(OF_EMBED) && CONFIG_IS_ENABLED(NEEDS_MANUAL_RELOC)) + gd->fdt_blob += gd->reloc_off; + #ifdef CONFIG_EFI_LOADER /* * On the ARM architecture gd is mapped to a fixed register (r9 or x18). -- 2.37.2.789.g6183377224-goog

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[RFC PATCH 00/16] arm: Add Rockchip RK3588 support
by Jagan Teki 13 Mar '23

13 Mar '23

This series support Rockchip RK3588. All the device tree files are synced from linux-next with the proper SHA1 mentioned in the commit messages. Unfortunately, the BL31 from rkbin is not compatible with U-Boot so it is failing to load ATF entry from SPL and hang. Verified below BL31 versions, bl31-v1.15 bl31-v1.21 bl31-v1.22 bl31-v1.23 bl31-v1.24 bl31-v1.25 bl31-v1.26 Rever-engineered with respect to rockchip u-boot by using the same FIT_GENERATOR being used in Mainline, rockchip u-boot is booting but mainline showing the same issue. Log: LPDDR4X, 2112MHz01-00642-g6bdfd31756-dirty (Jan 26 2023 ��3:44:34 +0530) channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=8 Size=4096MB change to F1: 528MHz change to F2: 1068MHz change to F3: 1560MHz change to F0: 2112MHz out U-Boot SPL 2023.01-00642-g6bdfd31756-dirty (Jan 26 2023 - 03:44:34 +0530) Trying to boot from MMC1 bl31_entry: atf_entry start << hang >> Any information on BL31 for RK3588 please share. Any inputs? Jagan. Jagan Teki (16): rockchip: mkimage: Add rk3588 support arm: rockchip: Add cru header for rk3588 arm: rockchip: Add grf header for rk3588 dt-bindings: clk: Add dt-binding header for RK3588 clk: rockchip: Add rk3588 clk support clk: rockchip: pll: Add pll_rk3588 type for rk3588 ram: rockchip: Add rk3588 ddr driver support dt-bindings: power: Add power-domain header for rk3588 dt-bindings: reset: add rk3588 reset definitions arm: rockchip: Add ioc header for rk3588 arm64: dts: rockchip: Add base DT for rk3588 SoC arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoM arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IO arm: rockchip: Add RK3588 arch core support ARM: dts: rockchip: Add rk3588-u-boot.dtsi board: rockchip: Add Edgeble Neural Compute Module 6 arch/arm/dts/Makefile | 3 + .../dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 23 + arch/arm/dts/rk3588-edgeble-neu6a-io.dts | 27 + arch/arm/dts/rk3588-edgeble-neu6a.dtsi | 32 + arch/arm/dts/rk3588-pinctrl.dtsi | 516 +++ arch/arm/dts/rk3588-u-boot.dtsi | 101 + arch/arm/dts/rk3588.dtsi | 58 + arch/arm/dts/rk3588s-pinctrl.dtsi | 3403 +++++++++++++++++ arch/arm/dts/rk3588s.dtsi | 1703 +++++++++ arch/arm/include/asm/arch-rk3588/boot0.h | 11 + arch/arm/include/asm/arch-rk3588/gpio.h | 11 + arch/arm/include/asm/arch-rockchip/clock.h | 24 + .../include/asm/arch-rockchip/cru_rk3588.h | 451 +++ .../include/asm/arch-rockchip/grf_rk3588.h | 35 + .../include/asm/arch-rockchip/ioc_rk3588.h | 102 + arch/arm/mach-rockchip/Kconfig | 20 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3588/Kconfig | 30 + arch/arm/mach-rockchip/rk3588/Makefile | 9 + arch/arm/mach-rockchip/rk3588/clk_rk3588.c | 33 + arch/arm/mach-rockchip/rk3588/rk3588.c | 162 + arch/arm/mach-rockchip/rk3588/syscon_rk3588.c | 32 + board/edgeble/neural-compute-module-6/Kconfig | 15 + .../neural-compute-module-6/MAINTAINERS | 6 + .../edgeble/neural-compute-module-6/Makefile | 7 + board/edgeble/neural-compute-module-6/neu6.c | 4 + configs/neu6a-io-rk3588_defconfig | 68 + doc/board/rockchip/rockchip.rst | 2 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_pll.c | 267 +- drivers/clk/rockchip/clk_rk3588.c | 2019 ++++++++++ drivers/ram/rockchip/Makefile | 1 + drivers/ram/rockchip/sdram_rk3588.c | 56 + include/configs/neural-compute-module-6.h | 15 + include/configs/rk3588_common.h | 32 + .../dt-bindings/clock/rockchip,rk3588-cru.h | 766 ++++ include/dt-bindings/power/rk3588-power.h | 69 + .../dt-bindings/reset/rockchip,rk3588-cru.h | 754 ++++ tools/rkcommon.c | 1 + 39 files changed, 10867 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588-edgeble-neu6a-io.dts create mode 100644 arch/arm/dts/rk3588-edgeble-neu6a.dtsi create mode 100644 arch/arm/dts/rk3588-pinctrl.dtsi create mode 100644 arch/arm/dts/rk3588-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588.dtsi create mode 100644 arch/arm/dts/rk3588s-pinctrl.dtsi create mode 100644 arch/arm/dts/rk3588s.dtsi create mode 100644 arch/arm/include/asm/arch-rk3588/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3588/gpio.h create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3588.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3588.h create mode 100644 arch/arm/include/asm/arch-rockchip/ioc_rk3588.h create mode 100644 arch/arm/mach-rockchip/rk3588/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3588/Makefile create mode 100644 arch/arm/mach-rockchip/rk3588/clk_rk3588.c create mode 100644 arch/arm/mach-rockchip/rk3588/rk3588.c create mode 100644 arch/arm/mach-rockchip/rk3588/syscon_rk3588.c create mode 100644 board/edgeble/neural-compute-module-6/Kconfig create mode 100644 board/edgeble/neural-compute-module-6/MAINTAINERS create mode 100644 board/edgeble/neural-compute-module-6/Makefile create mode 100644 board/edgeble/neural-compute-module-6/neu6.c create mode 100644 configs/neu6a-io-rk3588_defconfig create mode 100644 drivers/clk/rockchip/clk_rk3588.c create mode 100644 drivers/ram/rockchip/sdram_rk3588.c create mode 100644 include/configs/neural-compute-module-6.h create mode 100644 include/configs/rk3588_common.h create mode 100644 include/dt-bindings/clock/rockchip,rk3588-cru.h create mode 100644 include/dt-bindings/power/rk3588-power.h create mode 100644 include/dt-bindings/reset/rockchip,rk3588-cru.h -- 2.25.1

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[RFC/PATCH] lib/Kconfig: Enable OF_LIBFDT_OVERLAY by default when FIT is enabled
by Laurent Pinchart 12 Mar '23

12 Mar '23

FIT image support is commonly used to bundle a kernel image, a device tree, and device tree overlays. Applying overlays requires the OF_LIBFDT_OVERLAY config option to be set, which lots of boards fail to select, most likely because developers never noticed. This leads to an error when trying to apply overlays: "config with overlays but CONFIG_OF_LIBFDT_OVERLAY not set" TI ARM boards select the option by default. Extend this to all systems that select the FIT option. This only affects the default, overlay support can still be disabled manually in the configuration. Signed-off-by: Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> --- I'm posting this as an RFC to get feedback. If the idea is generally appreciated, I'll update the defconfig files accordingly. --- lib/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Kconfig b/lib/Kconfig index 549bd3577851..d309ccf83c03 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -823,7 +823,7 @@ config OF_LIBFDT_ASSUME_MASK config OF_LIBFDT_OVERLAY bool "Enable the FDT library overlay support" depends on OF_LIBFDT - default y if ARCH_OMAP2PLUS || ARCH_KEYSTONE + default y if FIT help This enables the FDT library (libfdt) overlay support. base-commit: f147aa80f52989c7455022ca1ab959e8545feccc -- Regards, Laurent Pinchart

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