January 2023 - U-Boot

[PATCH 1/5] mtd/spinand: rework detect procedure for different READ_ID operation
by Frieder Schrempf 31 May '23

31 May '23

From: Mikhail Kshevetskiy <mikhail.kshevetskiy(a)iopsys.eu> Currently there are 3 different variants of read_id implementation: 1. opcode only. Found in GD5FxGQ4xF. 2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E 3. opcode + 1 dummy byte. Found in other currently supported chips. Original implementation was for variant 1 and let detect function of chips with variant 2 and 3 to ignore the first byte. This isn't robust: 1. For chips of variant 2, if SPI master doesn't keep MOSI low during read, chip will get a random id offset, and the entire id buffer will shift by that offset, causing detect failure. 2. For chips of variant 1, if it happens to get a devid that equals to manufacture id of variant 2 or 3 chips, it'll get incorrectly detected. This patch reworks detect procedure to address problems above. New logic do detection for all variants separatedly, in 1-2-3 order. Since all current detect methods do exactly the same id matching procedure, unify them into core.c and remove detect method from manufacture_ops. This is a rework of Chuanhong Guo <gch981213(a)gmail.com> patch submitted to linux kernel Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy(a)iopsys.eu> Signed-off-by: Frieder Schrempf <frieder.schrempf(a)kontron.de> --- drivers/mtd/nand/spi/core.c | 104 +++++++++++++++++++----------- drivers/mtd/nand/spi/gigadevice.c | 30 ++------- drivers/mtd/nand/spi/macronix.c | 45 +++++-------- drivers/mtd/nand/spi/micron.c | 50 ++++++-------- drivers/mtd/nand/spi/toshiba.c | 66 +++++++++---------- drivers/mtd/nand/spi/winbond.c | 34 ++-------- include/linux/mtd/spinand.h | 66 ++++++++++++------- 7 files changed, 187 insertions(+), 208 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 134bf22c805..d92de9c24e3 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -17,6 +17,7 @@ #include <linux/mtd/spinand.h> #include <linux/of.h> #include <linux/slab.h> +#include <linux/string.h> #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> #else @@ -451,9 +452,11 @@ out: return status & STATUS_BUSY ? -ETIMEDOUT : 0; } -static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf) +static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr, + u8 ndummy, u8 *buf) { - struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf, + struct spi_mem_op op = SPINAND_READID_OP(naddr, ndummy, + spinand->scratchbuf, SPINAND_MAX_ID_LEN); int ret; @@ -807,21 +810,6 @@ static int spinand_mtd_block_isreserved(struct mtd_info *mtd, loff_t offs) return ret; } -const struct spi_mem_op * -spinand_find_supported_op(struct spinand_device *spinand, - const struct spi_mem_op *ops, - unsigned int nops) -{ - unsigned int i; - - for (i = 0; i < nops; i++) { - if (spi_mem_supports_op(spinand->slave, &ops[i])) - return &ops[i]; - } - - return NULL; -} - static const struct nand_ops spinand_ops = { .erase = spinand_erase, .markbad = spinand_markbad, @@ -836,24 +824,62 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { &winbond_spinand_manufacturer, }; -static int spinand_manufacturer_detect(struct spinand_device *spinand) +static int spinand_manufacturer_match(struct spinand_device *spinand, + enum spinand_readid_method rdid_method) { + u8 *id = spinand->id.data; unsigned int i; int ret; for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) { - ret = spinand_manufacturers[i]->ops->detect(spinand); - if (ret > 0) { - spinand->manufacturer = spinand_manufacturers[i]; - return 0; - } else if (ret < 0) { - return ret; - } - } + const struct spinand_manufacturer *manufacturer = + spinand_manufacturers[i]; + if (id[0] != manufacturer->id) + continue; + + ret = spinand_match_and_init(spinand, + manufacturer->chips, + manufacturer->nchips, + rdid_method); + if (ret < 0) + continue; + + spinand->manufacturer = manufacturer; + return 0; + } return -ENOTSUPP; } +static int spinand_id_detect(struct spinand_device *spinand) +{ + u8 *id = spinand->id.data; + int ret; + + ret = spinand_read_id_op(spinand, 0, 0, id); + if (ret) + return ret; + ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE); + if (!ret) + return 0; + + ret = spinand_read_id_op(spinand, 1, 0, id); + if (ret) + return ret; + ret = spinand_manufacturer_match(spinand, + SPINAND_READID_METHOD_OPCODE_ADDR); + if (!ret) + return 0; + + ret = spinand_read_id_op(spinand, 0, 1, id); + if (ret) + return ret; + ret = spinand_manufacturer_match(spinand, + SPINAND_READID_METHOD_OPCODE_DUMMY); + + return ret; +} + static int spinand_manufacturer_init(struct spinand_device *spinand) { if (spinand->manufacturer->ops->init) @@ -909,9 +935,9 @@ spinand_select_op_variant(struct spinand_device *spinand, * @spinand: SPI NAND object * @table: SPI NAND device description table * @table_size: size of the device description table + * @rdid_method: read id method to match * - * Should be used by SPI NAND manufacturer drivers when they want to find a - * match between a device ID retrieved through the READ_ID command and an + * Match between a device ID retrieved through the READ_ID command and an * entry in the SPI NAND description table. If a match is found, the spinand * object will be initialized with information provided by the matching * spinand_info entry. @@ -920,8 +946,10 @@ spinand_select_op_variant(struct spinand_device *spinand, */ int spinand_match_and_init(struct spinand_device *spinand, const struct spinand_info *table, - unsigned int table_size, u8 devid) + unsigned int table_size, + enum spinand_readid_method rdid_method) { + u8 *id = spinand->id.data; struct nand_device *nand = spinand_to_nand(spinand); unsigned int i; @@ -929,13 +957,17 @@ int spinand_match_and_init(struct spinand_device *spinand, const struct spinand_info *info = &table[i]; const struct spi_mem_op *op; - if (devid != info->devid) + if (rdid_method != info->devid.method) + continue; + + if (memcmp(id + 1, info->devid.id, info->devid.len)) continue; nand->memorg = table[i].memorg; nand->eccreq = table[i].eccreq; spinand->eccinfo = table[i].eccinfo; spinand->flags = table[i].flags; + spinand->id.len = 1 + table[i].devid.len; spinand->select_target = table[i].select_target; op = spinand_select_op_variant(spinand, @@ -971,13 +1003,7 @@ static int spinand_detect(struct spinand_device *spinand) if (ret) return ret; - ret = spinand_read_id_op(spinand, spinand->id.data); - if (ret) - return ret; - - spinand->id.len = SPINAND_MAX_ID_LEN; - - ret = spinand_manufacturer_detect(spinand); + ret = spinand_id_detect(spinand); if (ret) { dev_err(spinand->slave->dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN, spinand->id.data); @@ -1081,11 +1107,11 @@ static int spinand_init(struct spinand_device *spinand) for (i = 0; i < nand->memorg.ntargets; i++) { ret = spinand_select_target(spinand, i); if (ret) - goto err_free_bufs; + goto err_manuf_cleanup; ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED); if (ret) - goto err_free_bufs; + goto err_manuf_cleanup; } ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c index a2c93486f49..43b353a3e7e 100644 --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c @@ -158,7 +158,8 @@ static const struct mtd_ooblayout_ops gd5fxgqxxexxg_ooblayout = { }; static const struct spinand_info gigadevice_spinand_table[] = { - SPINAND_INFO("GD5F1GQ4UExxG", 0xd1, + SPINAND_INFO("GD5F1GQ4UExxG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1), NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&gd5fxgq4_read_cache_variants, @@ -167,7 +168,8 @@ static const struct spinand_info gigadevice_spinand_table[] = { 0, SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout, gd5fxgq4xexxg_ecc_get_status)), - SPINAND_INFO("GD5F1GQ5UExxG", 0x51, + SPINAND_INFO("GD5F1GQ5UExxG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), NAND_ECCREQ(4, 512), SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants, @@ -178,33 +180,13 @@ static const struct spinand_info gigadevice_spinand_table[] = { gd5fxgq5xexxg_ecc_get_status)), }; -static int gigadevice_spinand_detect(struct spinand_device *spinand) -{ - u8 *id = spinand->id.data; - int ret; - - /* - * For GD NANDs, There is an address byte needed to shift in before IDs - * are read out, so the first byte in raw_id is dummy. - */ - if (id[1] != SPINAND_MFR_GIGADEVICE) - return 0; - - ret = spinand_match_and_init(spinand, gigadevice_spinand_table, - ARRAY_SIZE(gigadevice_spinand_table), - id[2]); - if (ret) - return ret; - - return 1; -} - static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { - .detect = gigadevice_spinand_detect, }; const struct spinand_manufacturer gigadevice_spinand_manufacturer = { .id = SPINAND_MFR_GIGADEVICE, .name = "GigaDevice", + .chips = gigadevice_spinand_table, + .nchips = ARRAY_SIZE(gigadevice_spinand_table), .ops = &gigadevice_spinand_manuf_ops, }; diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c index 6d643a8000d..08f7d69d8c6 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -105,7 +105,8 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand, } static const struct spinand_info macronix_spinand_table[] = { - SPINAND_INFO("MX35LF1GE4AB", 0x12, + SPINAND_INFO("MX35LF1GE4AB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12), NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), NAND_ECCREQ(4, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -114,7 +115,8 @@ static const struct spinand_info macronix_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, mx35lf1ge4ab_ecc_get_status)), - SPINAND_INFO("MX35LF2GE4AB", 0x22, + SPINAND_INFO("MX35LF2GE4AB", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22), NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), NAND_ECCREQ(4, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -122,7 +124,8 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), - SPINAND_INFO("MX35UF4GE4AD", 0xb7, + SPINAND_INFO("MX35UF4GE4AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7), NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -131,7 +134,8 @@ static const struct spinand_info macronix_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, mx35lf1ge4ab_ecc_get_status)), - SPINAND_INFO("MX35UF2GE4AD", 0xa6, + SPINAND_INFO("MX35UF2GE4AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6), NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -140,7 +144,8 @@ static const struct spinand_info macronix_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, mx35lf1ge4ab_ecc_get_status)), - SPINAND_INFO("MX35UF2GE4AC", 0xa2, + SPINAND_INFO("MX35UF2GE4AC", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2), NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), NAND_ECCREQ(4, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -149,7 +154,8 @@ static const struct spinand_info macronix_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, mx35lf1ge4ab_ecc_get_status)), - SPINAND_INFO("MX35UF1GE4AD", 0x96, + SPINAND_INFO("MX35UF1GE4AD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96), NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -158,7 +164,8 @@ static const struct spinand_info macronix_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, mx35lf1ge4ab_ecc_get_status)), - SPINAND_INFO("MX35UF1GE4AC", 0x92, + SPINAND_INFO("MX35UF1GE4AC", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92), NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), NAND_ECCREQ(4, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -170,33 +177,13 @@ static const struct spinand_info macronix_spinand_table[] = { }; -static int macronix_spinand_detect(struct spinand_device *spinand) -{ - u8 *id = spinand->id.data; - int ret; - - /* - * Macronix SPI NAND read ID needs a dummy byte, so the first byte in - * raw_id is garbage. - */ - if (id[1] != SPINAND_MFR_MACRONIX) - return 0; - - ret = spinand_match_and_init(spinand, macronix_spinand_table, - ARRAY_SIZE(macronix_spinand_table), - id[2]); - if (ret) - return ret; - - return 1; -} - static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = { - .detect = macronix_spinand_detect, }; const struct spinand_manufacturer macronix_spinand_manufacturer = { .id = SPINAND_MFR_MACRONIX, .name = "Macronix", + .chips = macronix_spinand_table, + .nchips = ARRAY_SIZE(macronix_spinand_table), .ops = &macronix_spinand_manuf_ops, }; diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index 6bacf14aafe..cecd3db9584 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -120,7 +120,8 @@ static int micron_8_ecc_get_status(struct spinand_device *spinand, static const struct spinand_info micron_spinand_table[] = { /* M79A 2Gb 3.3V */ - SPINAND_INFO("MT29F2G01ABAGD", 0x24, + SPINAND_INFO("MT29F2G01ABAGD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24), NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -130,7 +131,8 @@ static const struct spinand_info micron_spinand_table[] = { SPINAND_ECCINFO(&micron_8_ooblayout, micron_8_ecc_get_status)), /* M79A 2Gb 1.8V */ - SPINAND_INFO("MT29F2G01ABBGD", 0x25, + SPINAND_INFO("MT29F2G01ABBGD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25), NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -140,7 +142,8 @@ static const struct spinand_info micron_spinand_table[] = { SPINAND_ECCINFO(&micron_8_ooblayout, micron_8_ecc_get_status)), /* M78A 1Gb 3.3V */ - SPINAND_INFO("MT29F1G01ABAFD", 0x14, + SPINAND_INFO("MT29F1G01ABAFD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14), NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -150,7 +153,8 @@ static const struct spinand_info micron_spinand_table[] = { SPINAND_ECCINFO(&micron_8_ooblayout, micron_8_ecc_get_status)), /* M78A 1Gb 1.8V */ - SPINAND_INFO("MT29F1G01ABAFD", 0x15, + SPINAND_INFO("MT29F1G01ABAFD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15), NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -160,7 +164,8 @@ static const struct spinand_info micron_spinand_table[] = { SPINAND_ECCINFO(&micron_8_ooblayout, micron_8_ecc_get_status)), /* M79A 4Gb 3.3V */ - SPINAND_INFO("MT29F4G01ADAGD", 0x36, + SPINAND_INFO("MT29F4G01ADAGD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36), NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 2), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -171,7 +176,8 @@ static const struct spinand_info micron_spinand_table[] = { micron_8_ecc_get_status), SPINAND_SELECT_TARGET(micron_select_target)), /* M70A 4Gb 3.3V */ - SPINAND_INFO("MT29F4G01ABAFD", 0x34, + SPINAND_INFO("MT29F4G01ABAFD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34), NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -181,7 +187,8 @@ static const struct spinand_info micron_spinand_table[] = { SPINAND_ECCINFO(&micron_8_ooblayout, micron_8_ecc_get_status)), /* M70A 4Gb 1.8V */ - SPINAND_INFO("MT29F4G01ABBFD", 0x35, + SPINAND_INFO("MT29F4G01ABBFD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -191,7 +198,8 @@ static const struct spinand_info micron_spinand_table[] = { SPINAND_ECCINFO(&micron_8_ooblayout, micron_8_ecc_get_status)), /* M70A 8Gb 3.3V */ - SPINAND_INFO("MT29F8G01ADAFD", 0x46, + SPINAND_INFO("MT29F8G01ADAFD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46), NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -202,7 +210,8 @@ static const struct spinand_info micron_spinand_table[] = { micron_8_ecc_get_status), SPINAND_SELECT_TARGET(micron_select_target)), /* M70A 8Gb 1.8V */ - SPINAND_INFO("MT29F8G01ADBFD", 0x47, + SPINAND_INFO("MT29F8G01ADBFD", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47), NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -214,26 +223,6 @@ static const struct spinand_info micron_spinand_table[] = { SPINAND_SELECT_TARGET(micron_select_target)), }; -static int micron_spinand_detect(struct spinand_device *spinand) -{ - u8 *id = spinand->id.data; - int ret; - - /* - * Micron SPI NAND read ID need a dummy byte, - * so the first byte in raw_id is dummy. - */ - if (id[1] != SPINAND_MFR_MICRON) - return 0; - - ret = spinand_match_and_init(spinand, micron_spinand_table, - ARRAY_SIZE(micron_spinand_table), id[2]); - if (ret) - return ret; - - return 1; -} - static int micron_spinand_init(struct spinand_device *spinand) { /* @@ -248,12 +237,13 @@ static int micron_spinand_init(struct spinand_device *spinand) } static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = { - .detect = micron_spinand_detect, .init = micron_spinand_init, }; const struct spinand_manufacturer micron_spinand_manufacturer = { .id = SPINAND_MFR_MICRON, .name = "Micron", + .chips = micron_spinand_table, + .nchips = ARRAY_SIZE(micron_spinand_table), .ops = &micron_spinand_manuf_ops, }; diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c index c2cd3b426b3..e057b08c703 100644 --- a/drivers/mtd/nand/spi/toshiba.c +++ b/drivers/mtd/nand/spi/toshiba.c @@ -111,7 +111,8 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand, static const struct spinand_info toshiba_spinand_table[] = { /* 3.3V 1Gb (1st generation) */ - SPINAND_INFO("TC58CVG0S3HRAIG", 0xC2, + SPINAND_INFO("TC58CVG0S3HRAIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2), NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -121,7 +122,8 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 3.3V 2Gb (1st generation) */ - SPINAND_INFO("TC58CVG1S3HRAIG", 0xCB, + SPINAND_INFO("TC58CVG1S3HRAIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB), NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -131,7 +133,8 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 3.3V 4Gb (1st generation) */ - SPINAND_INFO("TC58CVG2S0HRAIG", 0xCD, + SPINAND_INFO("TC58CVG2S0HRAIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD), NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -141,7 +144,8 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 1Gb (1st generation) */ - SPINAND_INFO("TC58CYG0S3HRAIG", 0xB2, + SPINAND_INFO("TC58CYG0S3HRAIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2), NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -151,7 +155,8 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 2Gb (1st generation) */ - SPINAND_INFO("TC58CYG1S3HRAIG", 0xBB, + SPINAND_INFO("TC58CYG1S3HRAIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB), NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -161,7 +166,8 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 4Gb (1st generation) */ - SPINAND_INFO("TC58CYG2S0HRAIG", 0xBD, + SPINAND_INFO("TC58CYG2S0HRAIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD), NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -176,7 +182,8 @@ static const struct spinand_info toshiba_spinand_table[] = { * QE_BIT. */ /* 3.3V 1Gb (2nd generation) */ - SPINAND_INFO("TC58CVG0S3HRAIJ", 0xE2, + SPINAND_INFO("TC58CVG0S3HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2), NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -186,7 +193,8 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 3.3V 2Gb (2nd generation) */ - SPINAND_INFO("TC58CVG1S3HRAIJ", 0xEB, + SPINAND_INFO("TC58CVG1S3HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB), NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -196,7 +204,8 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 3.3V 4Gb (2nd generation) */ - SPINAND_INFO("TC58CVG2S0HRAIJ", 0xED, + SPINAND_INFO("TC58CVG2S0HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED), NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -206,7 +215,8 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 3.3V 8Gb (2nd generation) */ - SPINAND_INFO("TH58CVG3S0HRAIJ", 0xE4, + SPINAND_INFO("TH58CVG3S0HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4), NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -216,7 +226,8 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 1Gb (2nd generation) */ - SPINAND_INFO("TC58CYG0S3HRAIJ", 0xD2, + SPINAND_INFO("TC58CYG0S3HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2), NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -226,7 +237,8 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 2Gb (2nd generation) */ - SPINAND_INFO("TC58CYG1S3HRAIJ", 0xDB, + SPINAND_INFO("TC58CYG1S3HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB), NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -236,7 +248,8 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 4Gb (2nd generation) */ - SPINAND_INFO("TC58CYG2S0HRAIJ", 0xDD, + SPINAND_INFO("TC58CYG2S0HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD), NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -246,7 +259,8 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), /* 1.8V 8Gb (2nd generation) */ - SPINAND_INFO("TH58CYG3S0HRAIJ", 0xD4, + SPINAND_INFO("TH58CYG3S0HRAIJ", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4), NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -257,33 +271,13 @@ static const struct spinand_info toshiba_spinand_table[] = { tx58cxgxsxraix_ecc_get_status)), }; -static int toshiba_spinand_detect(struct spinand_device *spinand) -{ - u8 *id = spinand->id.data; - int ret; - - /* - * Toshiba SPI NAND read ID needs a dummy byte, - * so the first byte in id is garbage. - */ - if (id[1] != SPINAND_MFR_TOSHIBA) - return 0; - - ret = spinand_match_and_init(spinand, toshiba_spinand_table, - ARRAY_SIZE(toshiba_spinand_table), - id[2]); - if (ret) - return ret; - - return 1; -} - static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = { - .detect = toshiba_spinand_detect, }; const struct spinand_manufacturer toshiba_spinand_manufacturer = { .id = SPINAND_MFR_TOSHIBA, .name = "Toshiba", + .chips = toshiba_spinand_table, + .nchips = ARRAY_SIZE(toshiba_spinand_table), .ops = &toshiba_spinand_manuf_ops, }; diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index c119486efb7..66ed0a51d2f 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -79,7 +79,8 @@ static int w25m02gv_select_target(struct spinand_device *spinand, } static const struct spinand_info winbond_spinand_table[] = { - SPINAND_INFO("W25M02GV", 0xAB, + SPINAND_INFO("W25M02GV", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab), NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2), NAND_ECCREQ(1, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -88,7 +89,8 @@ static const struct spinand_info winbond_spinand_table[] = { 0, SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL), SPINAND_SELECT_TARGET(w25m02gv_select_target)), - SPINAND_INFO("W25N01GV", 0xAA, + SPINAND_INFO("W25N01GV", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa), NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), NAND_ECCREQ(1, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -98,31 +100,6 @@ static const struct spinand_info winbond_spinand_table[] = { SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), }; -/** - * winbond_spinand_detect - initialize device related part in spinand_device - * struct if it is a Winbond device. - * @spinand: SPI NAND device structure - */ -static int winbond_spinand_detect(struct spinand_device *spinand) -{ - u8 *id = spinand->id.data; - int ret; - - /* - * Winbond SPI NAND read ID need a dummy byte, - * so the first byte in raw_id is dummy. - */ - if (id[1] != SPINAND_MFR_WINBOND) - return 0; - - ret = spinand_match_and_init(spinand, winbond_spinand_table, - ARRAY_SIZE(winbond_spinand_table), id[2]); - if (ret) - return ret; - - return 1; -} - static int winbond_spinand_init(struct spinand_device *spinand) { struct nand_device *nand = spinand_to_nand(spinand); @@ -142,12 +119,13 @@ static int winbond_spinand_init(struct spinand_device *spinand) } static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = { - .detect = winbond_spinand_detect, .init = winbond_spinand_init, }; const struct spinand_manufacturer winbond_spinand_manufacturer = { .id = SPINAND_MFR_WINBOND, .name = "Winbond", + .chips = winbond_spinand_table, + .nchips = ARRAY_SIZE(winbond_spinand_table), .ops = &winbond_spinand_manuf_ops, }; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 15bcd59f341..1ae4dc6b15b 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -39,9 +39,9 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) -#define SPINAND_READID_OP(ndummy, buf, len) \ +#define SPINAND_READID_OP(naddr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ - SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_ADDR(naddr, 0, 1), \ SPI_MEM_OP_DUMMY(ndummy, 1), \ SPI_MEM_OP_DATA_IN(len, buf, 1)) @@ -153,37 +153,46 @@ struct spinand_device; * @data: buffer containing the id bytes. Currently 4 bytes large, but can * be extended if required * @len: ID length - * - * struct_spinand_id->data contains all bytes returned after a READ_ID command, - * including dummy bytes if the chip does not emit ID bytes right after the - * READ_ID command. The responsibility to extract real ID bytes is left to - * struct_manufacurer_ops->detect(). */ struct spinand_id { u8 data[SPINAND_MAX_ID_LEN]; int len; }; +enum spinand_readid_method { + SPINAND_READID_METHOD_OPCODE, + SPINAND_READID_METHOD_OPCODE_ADDR, + SPINAND_READID_METHOD_OPCODE_DUMMY, +}; + +/** + * struct spinand_devid - SPI NAND device id structure + * @id: device id of current chip + * @len: number of bytes in device id + * @method: method to read chip id + * There are 3 possible variants: + * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately + * after read_id opcode. + * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after + * read_id opcode + 1-byte address. + * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after + * read_id opcode + 1 dummy byte. + */ +struct spinand_devid { + const u8 *id; + const u8 len; + const enum spinand_readid_method method; +}; + /** * struct manufacurer_ops - SPI NAND manufacturer specific operations - * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed - * the core calls the struct_manufacurer_ops->detect() hook of each - * registered manufacturer until one of them return 1. Note that - * the first thing to check in this hook is that the manufacturer ID - * in struct_spinand_device->id matches the manufacturer whose - * ->detect() hook has been called. Should return 1 if there's a - * match, 0 if the manufacturer ID does not match and a negative - * error code otherwise. When true is returned, the core assumes - * that properties of the NAND chip (spinand->base.memorg and - * spinand->base.eccreq) have been filled * @init: initialize a SPI NAND device * @cleanup: cleanup a SPI NAND device * * Each SPI NAND manufacturer driver should implement this interface so that - * NAND chips coming from this vendor can be detected and initialized properly. + * NAND chips coming from this vendor can be initialized properly. */ struct spinand_manufacturer_ops { - int (*detect)(struct spinand_device *spinand); int (*init)(struct spinand_device *spinand); void (*cleanup)(struct spinand_device *spinand); }; @@ -192,11 +201,16 @@ struct spinand_manufacturer_ops { * struct spinand_manufacturer - SPI NAND manufacturer instance * @id: manufacturer ID * @name: manufacturer name + * @devid_len: number of bytes in device ID + * @chips: supported SPI NANDs under current manufacturer + * @nchips: number of SPI NANDs available in chips array * @ops: manufacturer operations */ struct spinand_manufacturer { u8 id; char *name; + const struct spinand_info *chips; + const size_t nchips; const struct spinand_manufacturer_ops *ops; }; @@ -268,7 +282,7 @@ struct spinand_ecc_info { */ struct spinand_info { const char *model; - u8 devid; + struct spinand_devid devid; u32 flags; struct nand_memory_organization memorg; struct nand_ecc_req eccreq; @@ -282,6 +296,13 @@ struct spinand_info { unsigned int target); }; +#define SPINAND_ID(__method, ...) \ + { \ + .id = (const u8[]){ __VA_ARGS__ }, \ + .len = sizeof((u8[]){ __VA_ARGS__ }), \ + .method = __method, \ + } + #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ { \ .read_cache = __read, \ @@ -440,9 +461,10 @@ static inline void spinand_set_ofnode(struct spinand_device *spinand, } #endif /* __UBOOT__ */ -int spinand_match_and_init(struct spinand_device *dev, +int spinand_match_and_init(struct spinand_device *spinand, const struct spinand_info *table, - unsigned int table_size, u8 devid); + unsigned int table_size, + enum spinand_readid_method rdid_method); int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); int spinand_select_target(struct spinand_device *spinand, unsigned int target); -- 2.39.0

6 21

[PATCH] ARM: imx: Fix parsing of ROM log event IDs on iMX8M
by fedorross＠gmail.com 21 May '23

21 May '23

From: Fedor Ross <fedor.ross(a)ifm.com> It seems like the ROM log events for the iMX8M are not fully covered by AN12853 i.MX ROMs Log Events, Rev. 0, May 2020. On iMX8M the ROM event ID 0x82 seems to use parameter0 which stops the parsing because the end of list is detected too early. This patch adds ROM event ID 0x82 and skips the next word if ID 0x82 is parsed. Fixes: a5ee05cf71 ("ARM: imx: Pick correct eMMC boot partition from ROM log") Signed-off-by: Fedor Ross <fedor.ross(a)ifm.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/mach-imx/imx8m/soc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 8171631db1..4df57cb150 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -677,6 +677,7 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc) /* Log entries with 1 parameter, skip 1 */ case 0x80: /* Start to perform the device initialization */ case 0x81: /* The boot device initialization completes */ + case 0x82: /* Starts to execute boot device driver pre-config */ case 0x8f: /* The boot device initialization fails */ case 0x90: /* Start to read data from boot device */ case 0x91: /* Reading data from boot device completes */ -- 2.20.1

4 6

commit 787f04bb6a - imx: add USB2_BOOT type
by Rasmus Villemoes 21 May '23

21 May '23

Hi Peng It seems that commit 787f04bb6a (imx: add USB2_BOOT type) broke our board logic which relies on whether get_boot_device() returns USB_BOOT or not. Instrumenting get_boot_device() shows that on our imx8mp board, boot_instance is 3 when we're booting over USB, so boot_dev becomes 20 instead of 17 aka USB_BOOT. I assume that for the boards/socs you mentioned in the commit message, boot_instance could be 0 or 1. However, I don't see anywhere that uses that USB2_BOOT define. Short-term, I'll probably just revert 787f04bb6a locally. A bit longer term, I'm thinking I should be doing rom_api_query_boot_infor() and "decoding" the return value myself. Is there any chance you could make some information on that ROM API public so it's possible for outsiders to understand what's going on? Rasmus

4 8

[u-boot, v2019.04-aspeed-openbmc] ARM: dts: aspeed: add Meta greatlakes board (AST2600)
by Delphine CC Chiu 18 May '23

18 May '23

Add initial version of device tree for Meta Greatlakes BMC which is equipped with Aspeed AST2600 BMC SoC. Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu(a)Wiwynn.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/ast2600-greatlakes.dts | 191 ++++++++++++++++++++++++++ configs/ast2600_openbmc_spl_defconfig | 1 + 3 files changed, 193 insertions(+) create mode 100644 arch/arm/dts/ast2600-greatlakes.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6c34b83336..c9cb54cddd 100755 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -686,6 +686,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ ast2600-evb.dtb \ ast2600-dcscm.dtb \ ast2600-fpga.dtb \ + ast2600-greatlakes.dtb \ ast2600-intel.dtb \ ast2600-ncsi.dtb \ ast2600-p10bmc.dtb \ diff --git a/arch/arm/dts/ast2600-greatlakes.dts b/arch/arm/dts/ast2600-greatlakes.dts new file mode 100644 index 0000000000..94caf295da --- /dev/null +++ b/arch/arm/dts/ast2600-greatlakes.dts @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2022 Meta Platforms Inc. +/dts-v1/; + +#include "ast2600-u-boot.dtsi" + +/ { + model = "Facebook Greatlakes BMC"; + compatible = "facebook,greatlakes-bmc", "aspeed,ast2600"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + stdout-path = &uart5; + }; + + aliases { + spi0 = &fmc; + ethernet3 = &mac3; + }; + + cpus { + cpu@0 { + clock-frequency = <800000000>; + }; + cpu@1 { + clock-frequency = <800000000>; + }; + }; +}; + +&uart5 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&sdrammc { + clock-frequency = <400000000>; +}; + +&wdt1 { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&wdt3 { + status = "okay"; +}; + +&mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio4_default>; + #address-cells = <1>; + #size-cells = <0>; + ethphy3: ethernet-phy@3 { + reg = <0>; + }; +}; + +&mac3 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&ethphy3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; +}; + +&fmc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fmcquad_default>; +}; + +&gpio0 { + status = "okay"; + line_148 { + gpio-hog; + gpios = <148 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc-slot1-isolated-enabled"; + }; + line_149 { + gpio-hog; + gpios = <149 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc-slot2-isolated-enabled"; + }; + line_150 { + gpio-hog; + gpios = <150 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc-slot3-isolated-enabled"; + }; + line_151 { + gpio-hog; + gpios = <151 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc-slot4-isolated-enabled"; + }; +}; + +&i2c0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; +}; + +&i2c1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_default>; +}; + +&i2c2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; +}; + +&i2c3 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; +}; + +&i2c4 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; +}; + +&i2c5 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; +}; + +&i2c6 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; +}; + +&i2c7 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; +}; + +&i2c8 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; +}; + +&scu { + mac0-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; + mac1-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; + mac2-clk-delay = <0x08 0x04 + 0x08 0x04 + 0x08 0x04>; + mac3-clk-delay = <0x08 0x04 + 0x08 0x04 + 0x08 0x04>; +}; + +&hace { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/configs/ast2600_openbmc_spl_defconfig b/configs/ast2600_openbmc_spl_defconfig index 95d7651b8e..efd683570f 100644 --- a/configs/ast2600_openbmc_spl_defconfig +++ b/configs/ast2600_openbmc_spl_defconfig @@ -100,6 +100,7 @@ CONFIG_ASPEED_ACRY=y CONFIG_DM_GPIO=y CONFIG_SPL_GPIO_HOG=y CONFIG_ASPEED_GPIO=y +CONFIG_GPIO_HOG=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_ASPEED=y CONFIG_MISC=y -- 2.17.1

2 1

[PATCH] gpio: renesas: Simplify .request/.rfree callbacks
by Pali Rohár 16 May '23

16 May '23

Remove identify wrapper functions. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/gpio/gpio-rcar.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index 138801850d3e..ba00bb459679 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -130,20 +130,9 @@ static int rcar_gpio_get_function(struct udevice *dev, unsigned offset) return GPIOF_INPUT; } -static int rcar_gpio_request(struct udevice *dev, unsigned offset, - const char *label) -{ - return pinctrl_gpio_request(dev, offset, label); -} - -static int rcar_gpio_free(struct udevice *dev, unsigned offset) -{ - return pinctrl_gpio_free(dev, offset); -} - static const struct dm_gpio_ops rcar_gpio_ops = { - .request = rcar_gpio_request, - .rfree = rcar_gpio_free, + .request = pinctrl_gpio_request, + .rfree = pinctrl_gpio_free, .direction_input = rcar_gpio_direction_input, .direction_output = rcar_gpio_direction_output, .get_value = rcar_gpio_get_value, -- 2.20.1

3 8

[PATCH v3] console: usb: kbd: Limit poll frequency to improve performance
by Filip Žaludek 15 May '23

15 May '23

Hello, change seems to be unfriendly to RPi3B+, it allows to enter 'U-Boot>' shell but usb keyboard does not respond. Keyboard is detected by 'usb info' in v2023.01-rc3, not in v2022.10. When reverted, usb keyboard works as expected. Anybody sitting front of RPi3B+ care to confirm? Regards, Filip Patch: https://github.com/u-boot/u-boot/commit/96991e652f541323a03c5b7e075d54a1170… Debug: USB KBD: found interrupt EP: 0x81 USB KBD: set boot protocol dwc2_submit_control_msg: dev='usb@7e980000', udev=000000003af4be00, udev->dev='usb_kbd', portnr=3 USB KBD: set idle interval... dwc2_submit_control_msg: dev='usb@7e980000', udev=000000003af4be00, udev->dev='usb_kbd', portnr=3 USB KBD: enable interrupt pipe... usb_kbd usb_kbd: Timeout poll on interrupt endpoint Tested: SW: v2022.10 & v2023.01-rc3 compiled from sources as 'rpiarm64' HW: USB 1.1 and 2.0 keyboards, RPi3B+ JeOS: http://download.opensuse.org/ports/aarch64/tumbleweed/appliances/openSUSE-T… (u-boot-rpiarm64-2022.10-1.1.aarch64)

4 20

[RFC] Proposed location to host the firmware handoff specification.
by Jose Marinho 09 May '23

09 May '23

Hi, Arm worked to draft a firmware handoff [1] specification, evolving it based on community feedback. This activity followed the request of some members of the Arm ecosystem [2]. The spec (still at ALP – feedback/comments welcome!) standardizes how information is propagated between different firmware components during boot. The spec hopes to remove the reliance on bespoke/platform-specific information handoff mechanisms, thus reducing the code maintenance burden. The concept of entry types is present in the spec – these are data structure layouts that carry a specific type of data. New types are meant to be added, following the needs and use-cases of the different communities. Thus, these communities should be empowered to request new types! To enable community contributions, the specification must be hosted in a location that is friendly to change requests. We propose to host the spec in trustedfirmware.org (tf.org). Tf.org hosts several open-source projects and already has an open governance model. TF-A, and the associated community, rely on tf.org, and thus are already well equipped to maintain this specification and keep it up to date. Tf.org is agnostic of any downstream projects that would adopt this specification (e.g. U-boot, EDK2, etc.). We welcome the views of the communities and want to understand if there are any strong objections to what’s being proposed! If anyone has objections, we are happy to consider alternatives and associated trade-offs. Regards [1] https://developer.arm.com/documentation/den0135/latest [2] Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages - TF-A - lists.trustedfirmware.org<https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…>

9 26

[PATCH] fw_env: add fallback to Linux's NVMEM based access
by Rafał Miłecki 09 May '23

09 May '23

From: Rafał Miłecki <rafal(a)milecki.pl> A new DT binding for describing environment data block has been added in Linux's commit 5db1c2dbc04c ("dt-bindings: nvmem: add U-Boot environment variables binding"). Once we get a proper Linux NVMEM driver it'll be possible to use Linux's binary interface for user-space as documented in the: https://www.kernel.org/doc/html/latest/driver-api/nvmem.html This commits makes fw_env fallback to looking for a compatible NVMEM device in case config file isn't present. In a long term this may make config files redundant and avoid code (info) duplication. Signed-off-by: Rafał Miłecki <rafal(a)milecki.pl> --- tools/env/fw_env.c | 70 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 67 insertions(+), 3 deletions(-) diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 31afef6f3b..be77bbf054 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -1713,6 +1713,67 @@ static int check_device_config(int dev) return rc; } +static int find_nvmem_device(void) +{ + const char *path = "/sys/bus/nvmem/devices"; + struct dirent *dent; + char *nvmem = NULL; + char comp[256]; + char buf[32]; + int bytes; + DIR *dir; + + dir = opendir(path); + if (!dir) { + return -EIO; + } + + while (!nvmem && (dent = readdir(dir))) { + FILE *fp; + + if (!strcmp(dent->d_name, ".") || !strcmp(dent->d_name, "..")) { + continue; + } + + bytes = snprintf(comp, sizeof(comp), "%s/%s/of_node/compatible", path, dent->d_name); + if (bytes < 0 || bytes == sizeof(comp)) { + continue; + } + + fp = fopen(comp, "r"); + if (!fp) { + continue; + } + + fread(buf, sizeof(buf), 1, fp); + + if (!strcmp(buf, "u-boot,env")) { + bytes = asprintf(&nvmem, "%s/%s/nvmem", path, dent->d_name); + if (bytes < 0) { + nvmem = NULL; + } + } + + fclose(fp); + } + + closedir(dir); + + if (nvmem) { + struct stat s; + + stat(nvmem, &s); + + DEVNAME(0) = nvmem; + DEVOFFSET(0) = 0; + ENVSIZE(0) = s.st_size; + + return 0; + } + + return -ENOENT; +} + static int parse_config(struct env_opts *opts) { int rc; @@ -1723,9 +1784,12 @@ static int parse_config(struct env_opts *opts) #if defined(CONFIG_FILE) /* Fills in DEVNAME(), ENVSIZE(), DEVESIZE(). Or don't. */ if (get_config(opts->config_file)) { - fprintf(stderr, "Cannot parse config file '%s': %m\n", - opts->config_file); - return -1; + if (find_nvmem_device()) { + fprintf(stderr, "Cannot parse config file '%s': %m\n", + opts->config_file); + fprintf(stderr, "Failed to find NVMEM device\n"); + return -1; + } } #else DEVNAME(0) = DEVICE1_NAME; -- 2.34.1

3 2

[PATCH] build_bug.h: Also define static_assert() when __CHECKER__ is defined
by Christophe Leroy 05 May '23

05 May '23

When doing a build with C=2, the following failure is encountered on several files: CHECK arch/powerpc/cpu/mpc8xxx/fsl_lbc.c arch/powerpc/cpu/mpc8xxx/fsl_lbc.c: note: in included file (through arch/powerpc/include/asm/global_data.h, include/init.h): include/asm-generic/global_data.h:494:21: error: Expected ) in function declarator include/asm-generic/global_data.h:494:21: error: got ( And because of the error, the interesting part which are the warnings don't appear. This is because static_assert() is defined only when __CHECKER__ is not defined. Add a stub when __CHECKER__ is defined. With that fix, the expected warnings are now seen: CHECK arch/powerpc/cpu/mpc8xxx/fsl_lbc.c arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:32:27: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:32:27: expected unsigned int const volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:32:27: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:32:45: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:32:45: expected unsigned int const volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:32:45: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:35:24: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:35:24: expected unsigned int const volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:35:24: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:35:40: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:35:40: expected unsigned int const volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:35:40: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:67:17: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:67:17: expected unsigned int volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:67:17: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:68:17: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:68:17: expected unsigned int volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:68:17: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:72:17: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:72:17: expected unsigned int volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:72:17: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:73:17: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:73:17: expected unsigned int volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:73:17: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:78:9: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:78:9: expected unsigned int volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:78:9: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:79:9: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:79:9: expected unsigned int volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:79:9: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:131:22: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:131:22: expected unsigned int const volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:131:22: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:132:49: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:132:49: expected unsigned int const volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:132:49: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:144:26: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:144:26: expected unsigned int volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:144:26: got unsigned int [usertype] *mxmr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:144:41: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:144:41: expected unsigned int const volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:144:41: got unsigned int [usertype] *mxmr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:145:27: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:145:27: expected unsigned int volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:145:27: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:146:32: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:146:32: expected unsigned int const volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:146:32: got unsigned int * arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:149:39: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:149:39: expected unsigned int const volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:149:39: got unsigned int [usertype] *mxmr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:155:18: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:155:18: expected unsigned int volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:155:18: got unsigned int [usertype] *mxmr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:155:33: warning: incorrect type in argument 1 (different address spaces) arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:155:33: expected unsigned int const volatile [noderef] <asn:2> *addr arch/powerpc/cpu/mpc8xxx/fsl_lbc.c:155:33: got unsigned int [usertype] *mxmr Signed-off-by: Christophe Leroy <christophe.leroy(a)csgroup.eu> --- CC: Masahiro Yamada <masahiroy(a)kernel.org> --- include/linux/build_bug.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/build_bug.h b/include/linux/build_bug.h index 9c7088bafa4..5a819961f15 100644 --- a/include/linux/build_bug.h +++ b/include/linux/build_bug.h @@ -12,6 +12,7 @@ #define BUILD_BUG_ON_MSG(cond, msg) (0) #define BUILD_BUG_ON(condition) (0) #define BUILD_BUG() (0) +#define static_assert(expr, ...) #else /* __CHECKER__ */ /* Force a compilation error if a constant expression is not a power of 2 */ -- 2.38.1

3 10

[PATCH] mpc83xx: Don't allow W and G bits in IBATs
by Christophe Leroy 02 May '23

02 May '23

The "Programming Environments Manual for 32-Bit Implementations of the PowerPC™ Architecture" says "W and G bits are not defined for IBAT registers. Attempting to write to these bits causes boundedly-undefined results" The "e300 Power Architecture™ Core Family Reference Manual" says the same: "Neither the W or G bits of the IBAT registers should be set. Attempting to write to these bits causes boundedly-undefined results." Remove the possibility to set those bytes. Fixes: 30915ab95d9 ("mpc83xx: Migrate BATS config to Kconfig") Signed-off-by: Christophe Leroy <christophe.leroy(a)csgroup.eu> Cc: Mario Six <mario.six(a)gdsys.cc> --- arch/powerpc/cpu/mpc83xx/bats/Kconfig | 208 ++++---------------------- configs/MPC837XERDB_defconfig | 3 - configs/gazerbeam_defconfig | 1 - configs/kmcoge5ne_defconfig | 3 - configs/kmeter1_defconfig | 2 - configs/kmopti2_defconfig | 2 - configs/kmsupx5_defconfig | 2 - configs/kmtepr2_defconfig | 2 - configs/tuge1_defconfig | 2 - configs/tuxx1_defconfig | 2 - 10 files changed, 32 insertions(+), 195 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/bats/Kconfig b/arch/powerpc/cpu/mpc83xx/bats/Kconfig index 218920cfc9a..1cdb390e79b 100644 --- a/arch/powerpc/cpu/mpc83xx/bats/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/bats/Kconfig @@ -65,18 +65,12 @@ config BAT0_ACCESS_RW endchoice -config BAT0_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT0_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT0_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT0_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT0_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -120,22 +114,10 @@ config BAT0_PAGE_PROTECTION config BAT0_WIMG_ICACHE hex - default 0x0 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x8 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x10 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x18 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x20 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x28 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x30 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x38 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x40 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x48 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x50 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x58 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x60 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x68 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED - default 0x70 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED - default 0x78 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED + default 0x0 if !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE config BAT0_WIMG_DCACHE hex @@ -228,18 +210,12 @@ config BAT1_ACCESS_RW endchoice -config BAT1_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT1_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT1_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT1_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT1_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -283,22 +259,10 @@ config BAT1_PAGE_PROTECTION config BAT1_WIMG_ICACHE hex - default 0x0 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x8 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x10 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x18 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x20 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x28 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x30 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x38 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x40 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x48 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x50 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x58 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x60 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x68 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED - default 0x70 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED - default 0x78 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED + default 0x0 if !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE config BAT1_WIMG_DCACHE hex @@ -391,18 +355,12 @@ config BAT2_ACCESS_RW endchoice -config BAT2_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT2_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT2_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT2_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT2_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -446,22 +404,10 @@ config BAT2_PAGE_PROTECTION config BAT2_WIMG_ICACHE hex - default 0x0 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x8 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x10 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x18 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x20 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x28 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x30 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x38 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x40 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x48 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x50 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x58 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x60 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x68 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED - default 0x70 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED - default 0x78 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED + default 0x0 if !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE config BAT2_WIMG_DCACHE hex @@ -554,18 +500,12 @@ config BAT3_ACCESS_RW endchoice -config BAT3_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT3_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT3_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT3_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT3_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -609,22 +549,10 @@ config BAT3_PAGE_PROTECTION config BAT3_WIMG_ICACHE hex - default 0x0 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x8 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x10 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x18 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x20 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x28 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x30 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x38 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x40 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x48 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x50 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x58 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x60 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x68 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED - default 0x70 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED - default 0x78 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED + default 0x0 if !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE config BAT3_WIMG_DCACHE hex @@ -719,18 +647,12 @@ config BAT4_ACCESS_RW endchoice -config BAT4_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT4_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT4_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT4_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT4_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -774,22 +696,10 @@ config BAT4_PAGE_PROTECTION config BAT4_WIMG_ICACHE hex - default 0x0 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x8 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x10 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x18 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x20 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x28 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x30 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x38 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x40 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x48 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x50 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x58 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x60 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x68 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED - default 0x70 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED - default 0x78 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED + default 0x0 if !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE config BAT4_WIMG_DCACHE hex @@ -882,18 +792,12 @@ config BAT5_ACCESS_RW endchoice -config BAT5_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT5_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT5_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT5_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT5_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -937,22 +841,10 @@ config BAT5_PAGE_PROTECTION config BAT5_WIMG_ICACHE hex - default 0x0 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x8 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x10 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x18 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x20 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x28 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x30 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x38 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x40 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x48 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x50 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x58 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x60 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x68 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED - default 0x70 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED - default 0x78 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED + default 0x0 if !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE config BAT5_WIMG_DCACHE hex @@ -1045,18 +937,12 @@ config BAT6_ACCESS_RW endchoice -config BAT6_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT6_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT6_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT6_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT6_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -1100,22 +986,10 @@ config BAT6_PAGE_PROTECTION config BAT6_WIMG_ICACHE hex - default 0x0 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x8 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x10 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x18 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x20 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x28 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x30 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x38 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x40 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x48 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x50 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x58 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x60 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x68 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED - default 0x70 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED - default 0x78 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED + default 0x0 if !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE config BAT6_WIMG_DCACHE hex @@ -1208,18 +1082,12 @@ config BAT7_ACCESS_RW endchoice -config BAT7_ICACHE_WRITETHROUGH - bool "I-cache Write-through" - config BAT7_ICACHE_INHIBITED bool "I-cache Inhibited" config BAT7_ICACHE_MEMORYCOHERENCE bool "I-cache Memory coherence" -config BAT7_ICACHE_GUARDED - bool "I-cache Guarded" - config BAT7_DCACHE_WRITETHROUGH bool "D-cache Write-through" @@ -1263,22 +1131,10 @@ config BAT7_PAGE_PROTECTION config BAT7_WIMG_ICACHE hex - default 0x0 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x8 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x10 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x18 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x20 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x28 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x30 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x38 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x40 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x48 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x50 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x58 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x60 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x68 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED - default 0x70 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED - default 0x78 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED + default 0x0 if !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE + default 0x10 if !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE + default 0x20 if BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE + default 0x30 if BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE config BAT7_WIMG_DCACHE hex diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 675b2de151c..c6eb4153d9c 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -45,7 +45,6 @@ CONFIG_BAT2_BASE=0xE0000000 CONFIG_BAT2_LENGTH_8_MBYTES=y CONFIG_BAT2_ACCESS_RW=y CONFIG_BAT2_ICACHE_INHIBITED=y -CONFIG_BAT2_ICACHE_GUARDED=y CONFIG_BAT2_DCACHE_INHIBITED=y CONFIG_BAT2_DCACHE_GUARDED=y CONFIG_BAT2_USER_MODE_VALID=y @@ -55,7 +54,6 @@ CONFIG_BAT3_NAME="L2_SWITCH" CONFIG_BAT3_BASE=0xF0000000 CONFIG_BAT3_ACCESS_RW=y CONFIG_BAT3_ICACHE_INHIBITED=y -CONFIG_BAT3_ICACHE_GUARDED=y CONFIG_BAT3_DCACHE_INHIBITED=y CONFIG_BAT3_DCACHE_GUARDED=y CONFIG_BAT3_USER_MODE_VALID=y @@ -91,7 +89,6 @@ CONFIG_BAT7_BASE=0x90000000 CONFIG_BAT7_LENGTH_256_MBYTES=y CONFIG_BAT7_ACCESS_RW=y CONFIG_BAT7_ICACHE_INHIBITED=y -CONFIG_BAT7_ICACHE_GUARDED=y CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index 3974e3d2bd3..b58ed5d1da8 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -33,7 +33,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_8_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 298ff16b7eb..582b946c5bc 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -26,7 +26,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -37,7 +36,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y @@ -94,7 +92,6 @@ CONFIG_BAT7_BASE=0x10000000 CONFIG_BAT7_LENGTH_256_MBYTES=y CONFIG_BAT7_ACCESS_RW=y CONFIG_BAT7_ICACHE_INHIBITED=y -CONFIG_BAT7_ICACHE_GUARDED=y CONFIG_BAT7_DCACHE_INHIBITED=y CONFIG_BAT7_DCACHE_GUARDED=y CONFIG_BAT7_USER_MODE_VALID=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 9386f2c5121..445433986ef 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -27,7 +27,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -38,7 +37,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 173306668fb..c024aa7aac1 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -21,7 +21,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -32,7 +31,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index c281611dd4c..902d3036b07 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -21,7 +21,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -32,7 +31,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index e099f74de1c..683b2ab1b94 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -21,7 +21,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -32,7 +31,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 3b8560f3e06..f9dd2327ffd 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -21,7 +21,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -32,7 +31,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 04ce0b3afec..e782a97013a 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -21,7 +21,6 @@ CONFIG_BAT0_BASE=0x00000000 CONFIG_BAT0_LENGTH_256_MBYTES=y CONFIG_BAT0_ACCESS_RW=y CONFIG_BAT0_ICACHE_INHIBITED=y -CONFIG_BAT0_ICACHE_GUARDED=y CONFIG_BAT0_DCACHE_INHIBITED=y CONFIG_BAT0_DCACHE_GUARDED=y CONFIG_BAT0_USER_MODE_VALID=y @@ -32,7 +31,6 @@ CONFIG_BAT1_BASE=0xE0000000 CONFIG_BAT1_LENGTH_4_MBYTES=y CONFIG_BAT1_ACCESS_RW=y CONFIG_BAT1_ICACHE_INHIBITED=y -CONFIG_BAT1_ICACHE_GUARDED=y CONFIG_BAT1_DCACHE_INHIBITED=y CONFIG_BAT1_DCACHE_GUARDED=y CONFIG_BAT1_USER_MODE_VALID=y -- 2.38.1

2 1