September 2022 - U-Boot

[PATCH] x86: Fix i8259 ifdef include guard
by Alistair Delva 14 Dec '22

14 Dec '22

When building U-Boot with clang, it notices that the i8259.h include guard does not work correctly due to a typo. Fix it. Signed-off-by: Alistair Delva <adelva(a)google.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Nick Desaulniers <ndesaulniers(a)google.com> --- arch/x86/include/asm/i8259.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h index b73052a6d2..90f2d3866c 100644 --- a/arch/x86/include/asm/i8259.h +++ b/arch/x86/include/asm/i8259.h @@ -7,7 +7,7 @@ /* i8259.h i8259 PIC Registers */ #ifndef _ASMI386_I8259_H_ -#define _ASMI386_I8959_H_ +#define _ASMI386_I8259_H_ /* PIC I/O mapped registers */ #define IRR 0x0 /* Interrupt Request Register */ @@ -73,4 +73,4 @@ int i8259_init(void); -#endif /* _ASMI386_I8959_H_ */ +#endif /* _ASMI386_I8259_H_ */ -- 2.30.2

3 2

[PATCH] phy: usbphyc: use regulator_set_enable_if_allowed for disabling vbus supply
by Patrick Delaunay 12 Dec '22

12 Dec '22

Use regulator_set_enable_if_allowed() api instead of regulator_set_enable() while disabling vbus supply. This way the driver doesn't see an error when it disable an always-on regulator for VBUS. This patch is needed for STM32MP157C-DK2 board when the regulator v3v3: buck4 used as the phy vbus supply in kernel device tree is always on with the next hack for low power use-case: &usbphyc_port0 { ... /* * Hack to keep hub active until all connected devices are suspended * otherwise the hub will be powered off as soon as the v3v3 is disabled * and it can disturb connected devices. */ connector { compatible = "usb-a-connector"; vbus-supply = <&v3v3>; }; }; Without this patch and the previous update in DT the command "usb stop" failed and the next command "usb start" cause a crash. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/phy/phy-stm32-usbphyc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index 9f0b7d71187..dcf2194e9a7 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -375,7 +375,7 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy) return 0; if (usbphyc_phy->vbus) { - ret = regulator_set_enable(usbphyc_phy->vbus, false); + ret = regulator_set_enable_if_allowed(usbphyc_phy->vbus, false); if (ret) return ret; } -- 2.25.1

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[PATCH v2 1/2] usb: hub: allow to increase HUB_DEBOUNCE_TIMEOUT
by Patrick Delaunay 09 Dec '22

09 Dec '22

Add a new CONFIG_USB_HUB_DEBOUNCE_TIMEOUT to increase the HUB_DEBOUNCE_TIMEOUT value, for example to 2s because some usb device needs around 1.5s or more to make the hub port status to be connected steadily after being powered off and powered on. This 2s value is aligned with Linux driver and avoids to configure "usb_pgood_delay" as a workaround for connection timeout on some USB device; normally the env variable "usb_pgood_delay" is used to delay the first query after power ON and thus the device answer, but this variable not used to increase the connection timeout delay. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- Hi, V2 of previous patch [1] after Marek request to a add a CONFIG_. I think this patch solves a general issue because a 1s timeout for USB connection is too short on problematic USB keys / USB HUB. The issue was introduced by the commit c998da0d6709 ("usb: Change power-on / scanning timeout handling") Patching usb_hub allows to avoid to patch in each board/driver. For example, commit 0417169054cb ("imx: ventana: add usb_pgood_delay 2sec default") => use pgood_delay = 2s !? or ("ARM: stm32: Increase USB power-good delay on DHSOM") https://patchwork.ozlabs.org/project/uboot/patch/20211113022444.231801-1-ma… or commit 2bf352f0c1b7 ("usb: dwc2: Add delay to fix the USB detection problem on SoCFPGA") => patch in USB DWC2 driver to add a timeout in driver The commit 319418c01c95 ("usb: hub: allow pgood_delay to be specified via env") introduces an env variable for warm-up times managed by hub->query_delay. But it is not linked to the connect timeout after power on managed by hub->connect_timeout. This patch allow to increase the boot time for some board when USB device is not available; the default value = 1s of the config CONFIG_USB_HUB_DEBOUNCE_TIMEOUT allow to keep the current behavior. This issue appears with DWC2 and USB HUB used in STM32MP135F-DK board; pgood_delay=2 is not enough to solved all the USB key detection issues. [1] [2/2] usb: hub: increase HUB_DEBOUNCE_TIMEOUT http://patchwork.ozlabs.org/project/uboot/patch/20220704124540.2.I5eabf3f9f… Patrick Changes in v2: - allow defconfig configuration by CONFIG_USB_HUB_DEBOUNCE_TIMEOUT common/Kconfig | 12 ++++++++++++ common/usb_hub.c | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/common/Kconfig b/common/Kconfig index e7914ca750a..fedb643ea58 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -992,3 +992,15 @@ config FDT_SIMPLEFB These functions can be used by board to indicate to the OS the presence of the simple frame buffer with associated reserved memory + +config USB_HUB_DEBOUNCE_TIMEOUT + int "Timeout in milliseconds for USB HUB connection" + depends on USB + default 1000 + help + Value in milliseconds of the USB connection timeout, the max delay to + wait the hub port status to be connected steadily after being powered + off and powered on in the usb hub driver. + This define allows to increase the HUB_DEBOUNCE_TIMEOUT default + value = 1s because some usb device needs around 1.5s to be initialized + and a 2s value should solve detection issue on problematic USB keys. diff --git a/common/usb_hub.c b/common/usb_hub.c index d73638950b9..87fd93c55db 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -47,7 +47,7 @@ #define HUB_SHORT_RESET_TIME 20 #define HUB_LONG_RESET_TIME 200 -#define HUB_DEBOUNCE_TIMEOUT 1000 +#define HUB_DEBOUNCE_TIMEOUT CONFIG_USB_HUB_DEBOUNCE_TIMEOUT #define PORT_OVERCURRENT_MAX_SCAN_COUNT 3 -- 2.25.1

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[PATCH] arch: arm: mach-socfpga: To notify SDM when U-Boot pass control to Linux
by Jit Loon Lim 08 Dec '22

08 Dec '22

From: Chin Liang See <chin.liang.see(a)intel.com> Prior U-Boot pass control to Linux, U-Boot will send a mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on HPS SW transition. Signed-off-by: Chin Liang See <chin.liang.see(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/misc_soc64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 2acdfad07b..00852d27d9 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -89,3 +89,8 @@ void do_bridge_reset(int enable, unsigned int mask) socfpga_bridges_reset(enable); } + +void arch_preboot_os(void) +{ + mbox_hps_stage_notify(HPS_EXECUTION_STATE_OS); +} -- 2.26.2

2 1

[PATCH v5 0/3] Add riscv semihosting support in u-boot
by Kautuk Consul 07 Dec '22

07 Dec '22

Semihosting is a mechanism that enables code running on a target to communicate and use the Input/Output facilities on a host computer that is running a debugger. This patchset adds support for semihosting in u-boot for RISCV64 targets. CHANGES since v4: - Check arch dependencies for SEMIHOSTING as well as SPL_SEMIHOSTING config options as per Sean's comment. - arch/riscv/lib/interrupts.c: Check for post and pre instructions of the ebreak statement whether they are as per the RISCV semihosting specification. Only then do a disable_semihosting and epc += 4 and return. Compilation and test commands for SPL and S-mode configurations ================================================================= U-Boot S-mode on QEMU virt ---------------------------- // Compilation of S-mode u-boot ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_smode_defconfig make // Run riscv 64-bit u-boot with opensbi on qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\ u-boot/u-boot.bin U-Boot SPL on QEMU virt ------------------------ // Compilation of u-boot-spl ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_spl_defconfig make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin // Run 64-bit u-boot-spl in qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ u-boot/spl/u-boot-spl.bin -device\ loader,file=u-boot/u-boot.itb,addr=0x80200000 Kautuk Consul (3): lib: Add common semihosting library arch/riscv: add semihosting support for RISC-V board: qemu-riscv: enable semihosting arch/arm/Kconfig | 46 ------- arch/arm/lib/semihosting.c | 181 +------------------------- arch/riscv/include/asm/spl.h | 1 + arch/riscv/lib/Makefile | 2 + arch/riscv/lib/interrupts.c | 25 ++++ arch/riscv/lib/semihosting.c | 24 ++++ configs/qemu-riscv32_defconfig | 4 + configs/qemu-riscv32_smode_defconfig | 4 + configs/qemu-riscv32_spl_defconfig | 7 + configs/qemu-riscv64_defconfig | 4 + configs/qemu-riscv64_smode_defconfig | 4 + configs/qemu-riscv64_spl_defconfig | 7 + include/semihosting.h | 11 ++ lib/Kconfig | 47 +++++++ lib/Makefile | 2 + lib/semihosting.c | 186 +++++++++++++++++++++++++++ 16 files changed, 329 insertions(+), 226 deletions(-) create mode 100644 arch/riscv/lib/semihosting.c create mode 100644 lib/semihosting.c -- 2.34.1

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[PATCH] rockchip: jerry: Enable RESET driver
by Simon Glass 07 Dec '22

07 Dec '22

At present the display does not work since it needs the reset driver to operate. Fix this by enabling it. Signed-off-by: Simon Glass <sjg(a)chromium.org> Fixes: cd529f7ad62 ("rockchip: video: edp: Add missing reset support") Fixes: 9749d2ea29e ("rockchip: video: vop: Add reset support") --- configs/chromebook_jerry_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 35d546e6315..a60468eafa5 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -95,6 +95,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SERIAL=y CONFIG_SOUND=y -- 2.37.3.998.g577e59143f-goog

2 2

[PATCH v4 00/17] IPv6 support
by Viacheslav Mitrofanov 02 Dec '22

02 Dec '22

This patch set adds basic IPv6 support to U-boot. It is based on Chris's Packham patches (https://lists.denx.de/pipermail/u-boot/2017-January/279366.html) Chris's patches were taken as base. There were efforts to launch it on HiFive SiFive Unmatched board but the board didn't work well. The code was refactored, fixed some bugs as CRC for little-endian, some parts were implemented in our own way, something was taken from Linux. Finally we did manual tests and the board worked well. Testing was done on HiFive SiFive Unmatched board (RISC-V) Signed-off-by: Viacheslav Mitrofanov <v.v.mitrofanov(a)yadro.com> --- Changes in v2: - Split big patches into smaller - If an address in tftpboot is IPv6 than use IPv6 to boot - Add tests Changes in v3: - Added functions and structures description in whole patch-series - Removed memory allocation in on_ip6addr() - Some functions got return code from errno.h - Add to string_to_ip6() length parameter to avoid obligatory null termination - Add a lot of small decorative cnages Changes in v4: - Fixed funcs and structures style description - Added omitted tags Viacheslav Mitrofanov (17): net: ipv6: Add IPv6 basic primitives net: ipv6: Add IPv6 build options net: ipv6: Add callbacks declarations to get access to IPv6 variables net: ipv6: Add Neighbor Discovery Protocol (NDP) net: ipv6: Add string_to_ip6 converter net: ipv6: Enable IPv6 typeconversion specifier net: ipv6: Add ip6addr, gatewayip6, serverip6 variables callbacks net: ipv6: Add implementation of main IPv6 functions net: ipv6: Incorporate IPv6 support into u-boot net subsystem net: tftp: Add IPv6 support for tftpboot net: ping6: Add ping6 command test: dm: eth: Add string_to_ip6 test test: dm: eth: Add csum_ipv6_magic test test: dm: eth: Add ip6_addr_in_subnet test test: dm: eth: Add ip6_make_snma test test: dm: eth: Add ip6_make_lladdr test test/py: add a ping6 test cmd/Kconfig | 7 + cmd/net.c | 61 ++++++ include/env_callback.h | 10 + include/env_flags.h | 10 + include/ndisc.h | 102 +++++++++ include/net.h | 4 +- include/net6.h | 432 ++++++++++++++++++++++++++++++++++++ lib/net_utils.c | 109 ++++++++++ lib/vsprintf.c | 7 +- net/Kconfig | 10 + net/Makefile | 3 + net/ndisc.c | 289 +++++++++++++++++++++++++ net/net.c | 53 ++++- net/net6.c | 445 ++++++++++++++++++++++++++++++++++++++ net/ping6.c | 118 ++++++++++ net/tftp.c | 63 +++++- test/dm/eth.c | 146 +++++++++++++ test/py/tests/test_net.py | 15 ++ 18 files changed, 1865 insertions(+), 19 deletions(-) create mode 100644 include/ndisc.h create mode 100644 include/net6.h create mode 100644 net/ndisc.c create mode 100644 net/net6.c create mode 100644 net/ping6.c -- 2.25.1

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[PATCH] board_init: Convert CONFIG_MALLOC_F_ADDR to Kconfig
by Marek Vasut 30 Nov '22

30 Nov '22

Convert CONFIG_MALLOC_F_ADDR to Kconfig. The CL IoT gate board used MALLOC_F_ADDR 0x912000 on i.MX8M Mini unlike all the other platforms which use 0x930000 . This has been aligned with the other i.MX8M Mini platforms. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Kirill Kapranov <kirill.kapranov(a)compulab.co.il> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Peter Robinson <pbrobinson(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: Uri Mashiach <uri.mashiach(a)compulab.co.il> Cc: Valentin Raevsky <valentin(a)compulab.co.il> Cc: Ying-Chun Liu (PaulLiu) <paul.liu(a)linaro.org> --- Kconfig | 44 +++++++++++++++++++++ arch/sandbox/cpu/start.c | 4 +- common/init/board_init.c | 4 +- common/spl/spl.c | 4 +- include/configs/capricorn-common.h | 2 - include/configs/cgtqmx8.h | 1 - include/configs/imx8mm-cl-iot-gate.h | 7 ---- include/configs/imx8mm_beacon.h | 7 ---- include/configs/imx8mm_data_modul_edm_sbc.h | 7 ---- include/configs/imx8mm_evk.h | 7 ---- include/configs/imx8mm_icore_mx8mm.h | 6 --- include/configs/imx8mm_venice.h | 7 ---- include/configs/imx8mn_beacon.h | 8 ---- include/configs/imx8mp_rsb3720.h | 5 --- include/configs/imx8mq_cm.h | 5 --- include/configs/imx8mq_evk.h | 4 -- include/configs/imx8mq_phanbell.h | 4 -- include/configs/imx8qm_mek.h | 1 - include/configs/imx8qxp_mek.h | 1 - include/configs/imx8ulp_evk.h | 6 --- include/configs/kontron-sl-mx8mm.h | 5 --- include/configs/kontron_pitx_imx8m.h | 5 --- include/configs/kontron_sl28.h | 5 --- include/configs/phycore_imx8mm.h | 6 --- include/configs/pico-imx8mq.h | 4 -- include/configs/sandbox.h | 2 - include/configs/verdin-imx8mm.h | 6 --- include/configs/verdin-imx8mp.h | 6 --- scripts/config_whitelist.txt | 1 - 29 files changed, 47 insertions(+), 127 deletions(-) diff --git a/Kconfig b/Kconfig index 991b260182e..495a560d6bc 100644 --- a/Kconfig +++ b/Kconfig @@ -286,6 +286,23 @@ config SYS_MALLOC_F particular needs this to operate, so that it can allocate the initial serial device and any others that are needed. +config MALLOC_F_ADDR + hex "Address of malloc() pool before relocation" + depends on SYS_MALLOC_F + default 0x120000 if ARCH_IMX8 + default 0x182000 if ARCH_IMX8M && IMX8MQ + default 0x930000 if ARCH_IMX8M && IMX8MM + default 0x184000 if ARCH_IMX8M && IMX8MN + default 0x184000 if ARCH_IMX8M && IMX8MP + default 0x22040000 if ARCH_IMX8ULP + default 0x18000000 if ARCH_LS1028A + default 0x10000 if SANDBOX + default 0x0 + help + Before relocation, memory is very limited on many platforms. Still, + we can provide a small malloc() pool if needed. This option selects + placement of early malloc pool. + config SYS_MALLOC_F_LEN hex "Size of malloc() pool before relocation" depends on SYS_MALLOC_F @@ -320,6 +337,15 @@ config SYS_MALLOC_LEN This defines memory to be allocated for Dynamic allocation TODO: Use for other architectures +config SPL_MALLOC_F_ADDR + hex "Address of malloc() pool before relocation in SPL" + depends on SYS_MALLOC_F && SPL + default MALLOC_F_ADDR + help + Before relocation, memory is very limited on many platforms. Still, + we can provide a small malloc() pool if needed. This option selects + placement of early malloc pool in SPL. + config SPL_SYS_MALLOC_F_LEN hex "Size of malloc() pool in SPL" depends on SYS_MALLOC_F && SPL @@ -335,6 +361,15 @@ config SPL_SYS_MALLOC_F_LEN It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new malloc() region in SDRAM once it is inited. +config TPL_MALLOC_F_ADDR + hex "Address of malloc() pool before relocation in TPL" + depends on SYS_MALLOC_F && TPL + default SPL_MALLOC_F_ADDR + help + Before relocation, memory is very limited on many platforms. Still, + we can provide a small malloc() pool if needed. This option selects + placement of early malloc pool in TPL. + config TPL_SYS_MALLOC_F_LEN hex "Size of malloc() pool in TPL" depends on SYS_MALLOC_F && TPL @@ -360,6 +395,15 @@ config VALGRIND it can be handled accurately by Valgrind. If you aren't planning on using valgrind to debug U-Boot, say 'n'. +config VPL_MALLOC_F_ADDR + hex "Address of malloc() pool before relocation in VPL" + depends on SYS_MALLOC_F && VPL + default MALLOC_F_ADDR + help + Before relocation, memory is very limited on many platforms. Still, + we can provide a small malloc() pool if needed. This option selects + placement of early malloc pool in VPL. + config VPL_SYS_MALLOC_F_LEN hex "Size of malloc() pool in VPL before relocation" depends on SYS_MALLOC_F && VPL diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 90a84e93c79..aad983d7b78 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -506,9 +506,7 @@ int sandbox_main(int argc, char *argv[]) goto err; } -#if CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_base = CONFIG_MALLOC_F_ADDR; -#endif + gd->malloc_base = CONFIG_VAL(MALLOC_F_ADDR); #if CONFIG_IS_ENABLED(LOG) gd->default_log_level = state->default_log_level; #endif diff --git a/common/init/board_init.c b/common/init/board_init.c index 6a550261778..35506f2ed35 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -78,10 +78,8 @@ __weak void board_init_f_init_stack_protection(void) ulong board_init_f_alloc_reserve(ulong top) { /* Reserve early malloc arena */ -#ifndef CONFIG_MALLOC_F_ADDR -#if CONFIG_VAL(SYS_MALLOC_F_LEN) +#if CONFIG_VAL(MALLOC_F_ADDR) && CONFIG_VAL(SYS_MALLOC_F_LEN) top -= CONFIG_VAL(SYS_MALLOC_F_LEN); -#endif #endif /* LAST : reserve GD (rounded up to a multiple of 16 bytes) */ top = rounddown(top-sizeof(struct global_data), 16); diff --git a/common/spl/spl.c b/common/spl/spl.c index 29e0898f03d..2b0b6584924 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -503,9 +503,7 @@ static int spl_common_init(bool setup_malloc) #if CONFIG_VAL(SYS_MALLOC_F_LEN) if (setup_malloc) { -#ifdef CONFIG_MALLOC_F_ADDR - gd->malloc_base = CONFIG_MALLOC_F_ADDR; -#endif + gd->malloc_base = CONFIG_VAL(MALLOC_F_ADDR); gd->malloc_limit = CONFIG_VAL(SYS_MALLOC_F_LEN); gd->malloc_ptr = 0; } diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 6b1e82ad3b1..0de739c0013 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -17,8 +17,6 @@ #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_MALLOC_F_ADDR 0x00120000 - #endif /* CONFIG_SPL_BUILD */ /* ENET1 connects to base board and MUX with ESAI */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 6ac84878519..5dede78bc48 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -15,7 +15,6 @@ #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index c69f2fa19f3..58687bc311f 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -15,13 +15,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x912000 -/* For RAW image gives a error info not panic */ - -#endif - /* GUIDs for capsule updatable firmware images */ #define IMX8MM_CL_IOT_GATE_FIT_IMAGE_GUID \ EFI_GUID(0x7a32a939, 0xab92, 0x467b, 0x91, 0x52, \ diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 79ed3971225..71ca414bc01 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -13,13 +13,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 -/* For RAW image gives a error info not panic */ - -#endif - /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index fb05958bdc8..69efab257dc 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -12,13 +12,6 @@ #define CONFIG_SYS_MONITOR_LEN SZ_1M -#ifdef CONFIG_SPL_BUILD -#define CONFIG_MALLOC_F_ADDR 0x930000 - -/* For RAW image gives a error info not panic */ - -#endif - /* Link Definitions */ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 5e9e3e800d8..06d9837d39e 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -14,13 +14,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 -/* For RAW image gives a error info not panic */ - -#endif - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index 6b7f3af53a2..46971bdbf81 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -14,12 +14,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -# define CONFIG_MALLOC_F_ADDR 0x930000 -/* For RAW image gives a error info not panic */ -#endif /* CONFIG_SPL_BUILD */ - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 2) \ func(MMC, mmc, 0) diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 13015604509..e61bc304310 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -13,13 +13,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 -/* For RAW image gives a error info not panic */ - -#endif - #define MEM_LAYOUT_ENV_SETTINGS \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdt_addr_r=0x50200000\0" \ diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 6faecbde776..930b11b75e7 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -13,14 +13,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x184000 - -/* For RAW image gives a error info not panic */ - -#endif /* CONFIG_SPL_BUILD */ - /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 17e00f958b6..a7d5c85e856 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -25,11 +25,6 @@ 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9) #ifdef CONFIG_SPL_BUILD -#define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \ - * GD_FLG_FULL_MALLOC_INIT \ - * set \ - */ - #if defined(CONFIG_NAND_BOOT) #define CONFIG_SPL_NAND_MXS diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index ab74d5b26b6..e914cfc01a0 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -14,11 +14,6 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 -/* For RAW image gives a error info not panic */ - #endif /* ENET Config */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index ea4305667f2..48a50544040 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -16,10 +16,6 @@ /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 -/* For RAW image gives a error info not panic */ - #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 97bd5044501..28add2025b0 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -14,10 +14,6 @@ #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 -/* For RAW image gives a error info not panic */ #endif /* ENET Config */ diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 5f9d06e0f6f..100873de58b 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -14,7 +14,6 @@ #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index f8ec16ebb19..cb7c6fa6f5d 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -14,7 +14,6 @@ #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index ebfc166b4d4..a1eac5cad58 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -12,12 +12,6 @@ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_MALLOC_F_ADDR 0x22040000 - - -#endif - /* ENET Config */ #if defined(CONFIG_FEC_MXC) #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 622ab597624..3ae3e83a867 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -45,11 +45,6 @@ #undef BOOTENV_RUN_NET_USB_START #define BOOTENV_RUN_NET_USB_START -#ifdef CONFIG_SPL_BUILD -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 -#endif - #define ENV_MEM_LAYOUT_SETTINGS \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=0x42000000\0" \ diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index d77e4b4e100..c7ba1e90898 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -17,11 +17,6 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 -/* For RAW image gives a error info not panic */ - - #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 2373abf3e31..558774d9644 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -30,11 +30,6 @@ /* SMP */ #define CPU_RELEASE_ADDR secondary_boot_addr -/* generic timer */ - -/* early heap for SPL DM */ -#define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE - /* serial port */ #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 049d1d74345..94bb71355e0 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -15,12 +15,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 -/* For RAW image gives a error info not panic */ -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ "console=ttymxc2,115200\0" \ diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index d1cc1b9d63f..905d84066b8 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -14,10 +14,6 @@ #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 -/* For RAW image gives a error info not panic */ #endif /* ENET Config */ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 5168e2fa353..38c8337164f 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -8,8 +8,6 @@ #define CONFIG_IO_TRACE -#define CONFIG_MALLOC_F_ADDR 0x0010000 - /* GUIDs for capsule updatable firmware images */ #define SANDBOX_UBOOT_IMAGE_GUID \ EFI_GUID(0x09d7cf52, 0x0720, 0x4710, 0x91, 0xd1, \ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 5b5fce9bda1..f4289d2cf78 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -13,12 +13,6 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 -/* For RAW image gives a error info not panic */ -#endif - #define MEM_LAYOUT_ENV_SETTINGS \ "fdt_addr_r=0x44000000\0" \ "kernel_addr_r=0x42000000\0" \ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index fca40beba18..0aa61735284 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -14,12 +14,6 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x184000 -/* For RAW image gives a error info not panic */ - #define CONFIG_POWER_PCA9450 #define CONFIG_SYS_I2C diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 0a2b8179d49..f02f546d942 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -298,7 +298,6 @@ CONFIG_LPC32XX_NAND_SLC_WSETUP CONFIG_LPC32XX_NAND_SLC_WWIDTH CONFIG_LS102XA_STREAM_ID CONFIG_MACB_SEARCH_PHY -CONFIG_MALLOC_F_ADDR CONFIG_MALTA CONFIG_MAX_DSP_CPUS CONFIG_MAX_MEM_MAPPED -- 2.35.1

3 4

[PATCH v2] liteeth: LiteX Ethernet device
by Joel Stanley 28 Nov '22

28 Nov '22

LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic network device that is commonly used in LiteX designs. Signed-off-by: Joel Stanley <joel(a)jms.id.au> Reviewed-by: Ramon Fried <rfried.dev(a)gmail.com> --- v2: Fixed some return values Add asm/byteorder.h to fix building v1: https://lore.kernel.org/r/20220810042954.153280-1-joel@jms.id.au --- include/linux/litex.h | 84 +++++++++++++++++ drivers/net/liteeth.c | 214 ++++++++++++++++++++++++++++++++++++++++++ drivers/net/Kconfig | 5 + drivers/net/Makefile | 1 + 4 files changed, 304 insertions(+) create mode 100644 include/linux/litex.h create mode 100644 drivers/net/liteeth.c diff --git a/include/linux/litex.h b/include/linux/litex.h new file mode 100644 index 000000000000..5e91db41fdcb --- /dev/null +++ b/include/linux/litex.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Common LiteX header providing + * helper functions for accessing CSRs. + * + * Copyright (C) 2019-2020 Antmicro <www.antmicro.com> + */ + +#ifndef _LINUX_LITEX_H +#define _LINUX_LITEX_H + +#include <linux/io.h> +#include <asm/byteorder.h> + +static inline void _write_litex_subregister(u32 val, void __iomem *addr) +{ + writel((u32 __force)cpu_to_le32(val), addr); +} + +static inline u32 _read_litex_subregister(void __iomem *addr) +{ + return le32_to_cpu((__le32 __force)readl(addr)); +} + +/* + * LiteX SoC Generator, depending on the configuration, can split a single + * logical CSR (Control&Status Register) into a series of consecutive physical + * registers. + * + * For example, in the configuration with 8-bit CSR Bus, a 32-bit aligned, + * 32-bit wide logical CSR will be laid out as four 32-bit physical + * subregisters, each one containing one byte of meaningful data. + * + * For Linux support, upstream LiteX enforces a 32-bit wide CSR bus, which + * means that only larger-than-32-bit CSRs will be split across multiple + * subregisters (e.g., a 64-bit CSR will be spread across two consecutive + * 32-bit subregisters). + * + * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus + */ + +static inline void litex_write8(void __iomem *reg, u8 val) +{ + _write_litex_subregister(val, reg); +} + +static inline void litex_write16(void __iomem *reg, u16 val) +{ + _write_litex_subregister(val, reg); +} + +static inline void litex_write32(void __iomem *reg, u32 val) +{ + _write_litex_subregister(val, reg); +} + +static inline void litex_write64(void __iomem *reg, u64 val) +{ + _write_litex_subregister(val >> 32, reg); + _write_litex_subregister(val, reg + 4); +} + +static inline u8 litex_read8(void __iomem *reg) +{ + return _read_litex_subregister(reg); +} + +static inline u16 litex_read16(void __iomem *reg) +{ + return _read_litex_subregister(reg); +} + +static inline u32 litex_read32(void __iomem *reg) +{ + return _read_litex_subregister(reg); +} + +static inline u64 litex_read64(void __iomem *reg) +{ + return ((u64)_read_litex_subregister(reg) << 32) | + _read_litex_subregister(reg + 4); +} + +#endif /* _LINUX_LITEX_H */ diff --git a/drivers/net/liteeth.c b/drivers/net/liteeth.c new file mode 100644 index 000000000000..84d3852723e2 --- /dev/null +++ b/drivers/net/liteeth.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * LiteX Liteeth Ethernet + * + * Copyright 2021 Joel Stanley <joel(a)jms.id.au>, IBM Corp. + */ + +#include <linux/litex.h> + +#include <dm.h> +#include <dm/device_compat.h> +#include <net.h> + +#define LITEETH_WRITER_SLOT 0x00 +#define LITEETH_WRITER_LENGTH 0x04 +#define LITEETH_WRITER_ERRORS 0x08 +#define LITEETH_WRITER_EV_STATUS 0x0C +#define LITEETH_WRITER_EV_PENDING 0x10 +#define LITEETH_WRITER_EV_ENABLE 0x14 +#define LITEETH_READER_START 0x18 +#define LITEETH_READER_READY 0x1C +#define LITEETH_READER_LEVEL 0x20 +#define LITEETH_READER_SLOT 0x24 +#define LITEETH_READER_LENGTH 0x28 +#define LITEETH_READER_EV_STATUS 0x2C +#define LITEETH_READER_EV_PENDING 0x30 +#define LITEETH_READER_EV_ENABLE 0x34 +#define LITEETH_PREAMBLE_CRC 0x38 +#define LITEETH_PREAMBLE_ERRORS 0x3C +#define LITEETH_CRC_ERRORS 0x40 + +struct liteeth { + struct udevice *dev; + + void __iomem *base; + u32 slot_size; + + /* Tx */ + u32 tx_slot; + u32 num_tx_slots; + void __iomem *tx_base; + + /* Rx */ + u32 rx_slot; + u32 num_rx_slots; + void __iomem *rx_base; +}; + +static int liteeth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct liteeth *priv = dev_get_priv(dev); + u8 rx_slot; + int len; + + if (!litex_read8(priv->base + LITEETH_WRITER_EV_PENDING)) { + debug("liteeth: No packet ready\n"); + return -EAGAIN; + } + + rx_slot = litex_read8(priv->base + LITEETH_WRITER_SLOT); + len = litex_read32(priv->base + LITEETH_WRITER_LENGTH); + + debug("%s: slot %d len 0x%x\n", __func__, rx_slot, len); + + *packetp = priv->rx_base + rx_slot * priv->slot_size; + + return len; +} + +static int liteeth_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct liteeth *priv = dev_get_priv(dev); + + litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1); + + return 0; +} + +static int liteeth_start(struct udevice *dev) +{ + struct liteeth *priv = dev_get_priv(dev); + + /* Clear pending events */ + litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1); + litex_write8(priv->base + LITEETH_READER_EV_PENDING, 1); + + /* Enable events */ + litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 1); + litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 1); + + return 0; +} + +static void liteeth_stop(struct udevice *dev) +{ + struct liteeth *priv = dev_get_priv(dev); + + litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 0); + litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 0); +} + +static int liteeth_send(struct udevice *dev, void *packet, int len) +{ + struct liteeth *priv = dev_get_priv(dev); + void __iomem *txbuffer; + + if (!litex_read8(priv->base + LITEETH_READER_READY)) { + printf("liteeth: reader not ready\n"); + return -EAGAIN; + } + + /* Reject oversize packets */ + if (unlikely(len > priv->slot_size)) + return -EMSGSIZE; + + txbuffer = priv->tx_base + priv->tx_slot * priv->slot_size; + memcpy_toio(txbuffer, packet, len); + litex_write8(priv->base + LITEETH_READER_SLOT, priv->tx_slot); + litex_write16(priv->base + LITEETH_READER_LENGTH, len); + litex_write8(priv->base + LITEETH_READER_START, 1); + + priv->tx_slot = (priv->tx_slot + 1) % priv->num_tx_slots; + + return 0; +} + +static void liteeth_setup_slots(struct liteeth *priv) +{ + int err; + + err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,rx-slots", &priv->num_rx_slots); + if (err) { + dev_dbg(priv->dev, "unable to get litex,rx-slots, using 2\n"); + priv->num_rx_slots = 2; + } + + err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,tx-slots", &priv->num_tx_slots); + if (err) { + dev_dbg(priv->dev, "unable to get litex,tx-slots, using 2\n"); + priv->num_tx_slots = 2; + } + + err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,slot-size", &priv->slot_size); + if (err) { + dev_dbg(priv->dev, "unable to get litex,slot-size, using 0x800\n"); + priv->slot_size = 0x800; + } +} + +static int liteeth_remove(struct udevice *dev) +{ + liteeth_stop(dev); + + return 0; +} + +static const struct eth_ops liteeth_ops = { + .start = liteeth_start, + .stop = liteeth_stop, + .send = liteeth_send, + .recv = liteeth_recv, + .free_pkt = liteeth_free_pkt, +}; + +static int liteeth_of_to_plat(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct liteeth *priv = dev_get_priv(dev); + void __iomem *buf_base; + + pdata->iobase = dev_read_addr(dev); + + priv->dev = dev; + + priv->base = dev_remap_addr_name(dev, "mac"); + if (!priv->base) { + dev_err(dev, "failed to map registers\n"); + return -EINVAL; + } + + buf_base = dev_remap_addr_name(dev, "buffer"); + if (!buf_base) { + dev_err(dev, "failed to map buffer\n"); + return -EINVAL; + } + + liteeth_setup_slots(priv); + + /* Rx slots */ + priv->rx_base = buf_base; + priv->rx_slot = 0; + + /* Tx slots come after Rx slots */ + priv->tx_base = buf_base + priv->num_rx_slots * priv->slot_size; + priv->tx_slot = 0; + + return 0; +} + +static const struct udevice_id liteeth_ids[] = { + { .compatible = "litex,liteeth" }, + {} +}; + +U_BOOT_DRIVER(liteeth) = { + .name = "liteeth", + .id = UCLASS_ETH, + .of_match = liteeth_ids, + .of_to_plat = liteeth_of_to_plat, + .plat_auto = sizeof(struct eth_pdata), + .remove = liteeth_remove, + .ops = &liteeth_ops, + .priv_auto = sizeof(struct liteeth), +}; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 6bbbadc5eef3..961ae19ff335 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -438,6 +438,11 @@ config KSZ9477 This driver implements a DSA switch driver for the KSZ9477 family of GbE switches using the I2C interface. +config LITEETH + bool "LiteX LiteEth Ethernet MAC" + help + Driver for the LiteEth Ethernet MAC from LiteX. + config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 96b7678e9882..d3fc6b7d3ee4 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_KSZ9477) += ksz9477.o +obj-$(CONFIG_LITEETH) += liteeth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o -- 2.35.1

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[RESEND PATCH v2 0/3] net: fm: Add support for loading firmware from filesystem
by Sean Anderson 28 Nov '22

28 Nov '22

This adds support for loading Fman firmware from a filesystem using the firmware loader subsystem. It was originally part of [1], but has been split off because it is conceptually separate. [1] https://lore.kernel.org/u-boot/20220324182306.2037094-1-sean.anderson@seco.… Changes in v2: - Split series into two Sean Anderson (3): misc: fs_loader: Add function to get the chosen loader net: fm: Add firmware name parameter net: fm: Support loading firmware from a filesystem arch/arm/mach-k3/common.c | 2 +- arch/arm/mach-omap2/boot-common.c | 2 +- drivers/fpga/socfpga_arria10.c | 24 ++----------------- drivers/misc/fs_loader.c | 27 +++++++++++++++++++++ drivers/net/fm/fm.c | 40 +++++++++++++++++++++++++++---- drivers/net/fm/fm.h | 2 +- drivers/net/fm/init.c | 4 ++-- drivers/qe/Kconfig | 4 ++++ include/fs_loader.h | 12 ++++++++++ 9 files changed, 86 insertions(+), 31 deletions(-) -- 2.35.1.1320.gc452695387.dirty

3 11