August 2022 - U-Boot

[PATCH 00/17] patman: Convert camel case
by Simon Glass 01 Mar '23

01 Mar '23

Much of the Python code in U-Boot was written using the Chromium OS Python style. This series converts the patman class methods and functions from camel case to snake case. This fits with PEP8 and is one step along the way to making the code more compliant with that. Simon Glass (17): patman: Convert camel case in tools.py patman: Convert camel case in command.py patman: Convert camel case in checkpatch.py patman: Convert camel case in commit.py patman: Convert camel case in cros_subprocess.py patman: Convert camel case in func_test.py patman: Convert camel case in get_maintainer.py patman: Convert camel case in gitutil.py patman: Convert camel case in project.py patman: Convert camel case in test_checkpatch.py patman: Convert camel case in test_util.py patman: Convert camel case in tout.py patman: Rename Print() to Tprint() patman: Rename Color() method to build() patman: Convert camel case in terminal.py patman: Update with new pylint scores RFC: tools: Add a camel-case conversion script scripts/pylint.base | 26 +- scripts/style.py | 180 +++++++++++ tools/binman/bintool.py | 30 +- tools/binman/bintool_test.py | 34 +- tools/binman/btool/lz4.py | 8 +- tools/binman/btool/lzma_alone.py | 16 +- tools/binman/cbfs_util.py | 12 +- tools/binman/cbfs_util_test.py | 20 +- tools/binman/control.py | 74 ++--- tools/binman/elf.py | 20 +- tools/binman/elf_test.py | 20 +- tools/binman/entry.py | 42 +-- tools/binman/entry_test.py | 4 +- tools/binman/etype/atf_fip.py | 2 +- tools/binman/etype/blob.py | 4 +- tools/binman/etype/blob_ext_list.py | 2 +- tools/binman/etype/fdtmap.py | 2 +- tools/binman/etype/files.py | 2 +- tools/binman/etype/fill.py | 2 +- tools/binman/etype/fit.py | 20 +- tools/binman/etype/fmap.py | 6 +- tools/binman/etype/gbb.py | 10 +- tools/binman/etype/intel_ifwi.py | 12 +- tools/binman/etype/mkimage.py | 8 +- tools/binman/etype/section.py | 26 +- tools/binman/etype/text.py | 4 +- tools/binman/etype/u_boot_elf.py | 6 +- tools/binman/etype/u_boot_env.py | 4 +- tools/binman/etype/u_boot_spl_bss_pad.py | 4 +- tools/binman/etype/u_boot_spl_expanded.py | 2 +- tools/binman/etype/u_boot_tpl_bss_pad.py | 4 +- tools/binman/etype/u_boot_tpl_expanded.py | 2 +- tools/binman/etype/u_boot_ucode.py | 4 +- tools/binman/etype/u_boot_with_ucode_ptr.py | 2 +- tools/binman/etype/vblock.py | 10 +- tools/binman/fdt_test.py | 4 +- tools/binman/fip_util.py | 16 +- tools/binman/fip_util_test.py | 36 +-- tools/binman/fmap_util.py | 2 +- tools/binman/ftest.py | 324 ++++++++++---------- tools/binman/image.py | 16 +- tools/binman/main.py | 6 +- tools/binman/state.py | 34 +- tools/buildman/builder.py | 108 +++---- tools/buildman/builderthread.py | 12 +- tools/buildman/control.py | 46 +-- tools/buildman/func_test.py | 20 +- tools/buildman/test.py | 30 +- tools/buildman/toolchain.py | 26 +- tools/dtoc/fdt.py | 4 +- tools/dtoc/fdt_util.py | 12 +- tools/dtoc/main.py | 6 +- tools/dtoc/test_dtoc.py | 76 ++--- tools/dtoc/test_fdt.py | 34 +- tools/dtoc/test_src_scan.py | 12 +- tools/patman/checkpatch.py | 36 +-- tools/patman/command.py | 30 +- tools/patman/commit.py | 10 +- tools/patman/control.py | 20 +- tools/patman/cros_subprocess.py | 59 ++-- tools/patman/func_test.py | 74 ++--- tools/patman/get_maintainer.py | 8 +- tools/patman/gitutil.py | 176 +++++------ tools/patman/main.py | 8 +- tools/patman/patchstream.py | 12 +- tools/patman/project.py | 4 +- tools/patman/series.py | 32 +- tools/patman/settings.py | 4 +- tools/patman/status.py | 22 +- tools/patman/terminal.py | 56 ++-- tools/patman/test_checkpatch.py | 80 ++--- tools/patman/test_util.py | 8 +- tools/patman/tools.py | 86 +++--- tools/patman/tout.py | 58 ++-- tools/rmboard.py | 16 +- 75 files changed, 1214 insertions(+), 1033 deletions(-) create mode 100755 scripts/style.py -- 2.35.0.rc2.247.g8bbb082509-goog

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[PATCH v1 00/11] rockchip fixes and extend rk3568 support
by Peter Geis 27 Feb '23

27 Feb '23

to: Simon Glass <sjg(a)chromium.org> to: Philipp Tomsich <philipp.tomsich(a)vrull.eu> to: Kever Yang <kever.yang(a)rock-chips.com> to: Lukasz Majewski <lukma(a)denx.de> to: Sean Anderson <seanga2(a)gmail.com> to: Peng Fan <peng.fan(a)nxp.com> to: Jaehoon Chung <jh80.chung(a)samsung.com> to: Heiko Stübner <heiko(a)sntech.de> cc: u-boot(a)lists.denx.de Good Evening, The following is a few patches for rockchip mainline u-boot support. Patches 1-3 are fixes for the rk3568 reset handler, rockchip emmc dma to sram, and building the rockchip-sfc driver. Patch 4 adds a sanity check for the minimum sfc frequency. Patch 5 and 6 add adc support to spl and enable the rockchip recovery handler in spl, before attempting to load u-boot. Patch 7 enables rk3568 spl bootrom device detection. Patch 8 enables automatic clock gating and other power saving features on rk3568, which solves the chip running hotter compared to downstream. Patch 9 and 10 move the dwc3 platform data to the chip specific code and enable dwc3 otg support on rk3568. Patch 11 is an RFC patch for fixing ram detection on rk3568. Downstream goes about this a different way, where they implemented a special library to handle this. Please review and *especially test* patch 11. Very Respectfully, Peter Geis Peter Geis (11): clk: rockchip: rk3568: fix reset handler mmc: sdhci: allow disabling sdma in spl spi: rockchip-sfc: fix building rockchip-sfc spi: rockchip-sfc: sanity check minimum freq spl: support adc drivers in spl rockchip: handle bootrom recovery mode in spl rockchip: rk3568: add boot device detection rockchip: rk3568: enable automatic clock gating rockchip: move dwc3 config to chip specific handler rockchip: rk3568: add dwc3 otg support [RFC] rockchip: rk356x: attempt to fix ram detection arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/Makefile | 6 +- arch/arm/mach-rockchip/board.c | 24 ------ arch/arm/mach-rockchip/boot_mode.c | 4 +- arch/arm/mach-rockchip/rk3399/rk3399.c | 29 +++++++ arch/arm/mach-rockchip/rk3568/rk3568.c | 112 +++++++++++++++++++++++++ arch/arm/mach-rockchip/sdram.c | 19 +++-- common/board_f.c | 7 ++ common/spl/Kconfig | 5 ++ drivers/Makefile | 1 + drivers/clk/rockchip/clk_rk3568.c | 2 + drivers/mmc/Kconfig | 7 ++ drivers/mmc/sdhci.c | 6 +- drivers/spi/rockchip_sfc.c | 6 ++ include/configs/rk3568_common.h | 5 ++ 15 files changed, 197 insertions(+), 37 deletions(-) -- 2.25.1

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[RFC PATCH v1 0/9] Renesas RZ/N1 SoC initial support
by Ralph Siemsen 22 Feb '23

22 Feb '23

The RZ/N1 is a family of SoC devices from Renesas [1], featuring ARM Cortex-A7 and/or Cortex-M3 CPU, industrial ethernet protocols, integrated Ethernet switch, and numerous peripherals. This is a first step in upstreaming support for the RZ/N1 family. Currently it contains just enough to boot to the u-boot prompt. Additional patches will follow to support flash, SD, USB, Ethernet, etc. At this point, I am looking for general feedback about the overall direction and structure. I'm aware of several checkpatch warnings, and some TODO/FIXME items, which will be addressed. This work is based on a vendor-supplied u-boot 2017.01 tree [2], which supports several eval boards, none of which I have access to. Instead development has been done on a Schneider LCES2 board, which is fairly similar to the Renesas RZ/N1D-DB Demo board. The patches are currently against v2022.10-rc2. [1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-… [2] https://github.com/renesas-rz/rzn1_u-boot/tree/rzn1-stable Michel Pollet (1): tools: Add tool to create Renesas SPKG images Ralph Siemsen (8): ARM: armv7: add non-SPL enable for Cortex SMPEN clk: renesas: prepare for non-RCAR clock drivers clk: renesas: add R906G032 driver pinctrl: renesas: add R906G032 driver ram: cadence: add driver for Cadence EDAC dts: basic devicetree for Renesas RZ/N1 SoC ARM: rzn1: basic support for Renesas RZ/N1 SoC board: schneider: add LCES board support arch/arm/Kconfig | 17 + arch/arm/Makefile | 1 + arch/arm/cpu/armv7/Kconfig | 5 + arch/arm/dts/r9a06g032-rzn1d400-lces.dts | 50 ++ arch/arm/dts/r9a06g032.dtsi | 225 ++++++ arch/arm/mach-rzn1/Kconfig | 32 + arch/arm/mach-rzn1/Makefile | 3 + arch/arm/mach-rzn1/cpu_info.c | 20 + board/schneider/lces/Kconfig | 12 + board/schneider/lces/Makefile | 3 + board/schneider/lces/ddr_timing.c | 140 ++++ .../lces/jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++++++++++ board/schneider/lces/lces.c | 41 + configs/lces_defconfig | 26 + drivers/clk/renesas/Kconfig | 8 +- drivers/clk/renesas/Makefile | 6 +- drivers/clk/renesas/r9a06g032-clocks.c | 734 ++++++++++++++++++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/renesas/Kconfig | 7 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pinctrl-rzn1.c | 398 ++++++++++ drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 2 + drivers/ram/cadence/Kconfig | 24 + drivers/ram/cadence/Makefile | 1 + drivers/ram/cadence/ddr_async.c | 295 +++++++ drivers/ram/cadence/ddr_ctrl.c | 414 ++++++++++ drivers/ram/cadence/ddr_ctrl.h | 172 ++++ include/configs/lces.h | 22 + include/dt-bindings/clock/r9a06g032-sysctrl.h | 148 ++++ include/dt-bindings/pinctrl/rzn1-pinctrl.h | 141 ++++ tools/Makefile | 2 + tools/spkg_header.h | 49 ++ tools/spkg_utility.c | 306 ++++++++ 34 files changed, 3702 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/r9a06g032-rzn1d400-lces.dts create mode 100644 arch/arm/dts/r9a06g032.dtsi create mode 100644 arch/arm/mach-rzn1/Kconfig create mode 100644 arch/arm/mach-rzn1/Makefile create mode 100644 arch/arm/mach-rzn1/cpu_info.c create mode 100644 board/schneider/lces/Kconfig create mode 100644 board/schneider/lces/Makefile create mode 100644 board/schneider/lces/ddr_timing.c create mode 100644 board/schneider/lces/jedec_ddr3_2g_x16_1333h_500_cl8.h create mode 100644 board/schneider/lces/lces.c create mode 100644 configs/lces_defconfig create mode 100644 drivers/clk/renesas/r9a06g032-clocks.c create mode 100644 drivers/pinctrl/renesas/pinctrl-rzn1.c create mode 100644 drivers/ram/cadence/Kconfig create mode 100644 drivers/ram/cadence/Makefile create mode 100644 drivers/ram/cadence/ddr_async.c create mode 100644 drivers/ram/cadence/ddr_ctrl.c create mode 100644 drivers/ram/cadence/ddr_ctrl.h create mode 100644 include/configs/lces.h create mode 100644 include/dt-bindings/clock/r9a06g032-sysctrl.h create mode 100644 include/dt-bindings/pinctrl/rzn1-pinctrl.h create mode 100644 tools/spkg_header.h create mode 100644 tools/spkg_utility.c -- 2.25.1

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[PATCH 0/3] Introduce new sign binman's option
by Ivan Mikhaylov 18 Feb '23

18 Feb '23

From: Ivan Mikhaylov <ivan.mikhaylov(a)siemens.com> This patch introduces prototype of new sign binman's option. Enhancing the sign procedure, as example: mkimage -G privateky -r -o sha256,rsa4096 -F fit.fit binman replace -i flash.bin -f fit.fit fit into: binman sign -i flash.bin -k privatekey -a sha256,rsa4096 -f fit.fit fit It works with extracted FIT container and image, which provides key signing and replacing FIT container in directed image. Also, I'll add additional enhancement in future to this procedure with skipping on FIT container and providing extract->sign->replace in whole instead of sign->replace with documentation update and test as well. As example: binman sign -i flash.bin -k privatekey -a sha256,rsa4096 -f fit Ivan Mikhaylov (3): binman: add sign option for binman binman: add documentation for binman sign option binman: add test for sign option tools/binman/binman.rst | 10 +++++ tools/binman/cmdline.py | 13 ++++++ tools/binman/control.py | 26 +++++++++++- tools/binman/ftest.py | 42 +++++++++++++++++++ tools/binman/test/225_fit_sign.dts | 67 ++++++++++++++++++++++++++++++ 5 files changed, 157 insertions(+), 1 deletion(-) create mode 100644 tools/binman/test/225_fit_sign.dts -- 2.35.1

4 24

bind/unbind command not working for usb_ether
by Tim Harvey 15 Feb '23

15 Feb '23

Greetings, I'm trying to understand how to use the U-Boot bind command to bind the usb_ether driver to the usb class to register a USB ethernet gadget network device as referenced in: commit 02291d83fdaaf ("doc: add bind/unbind command documentation") commit 49c752c93a78 ("cmd: Add bind/unbind commands to bind a device to a driver from the command line") I have enabled: CONFIG_DM_USB=y CONFIG_USB_GADGET=y CONFIG_USB_ETHER=y However the 'usb_ether' driver is never registered and thus doesn't appear in a 'dm tree' list and can't be bound to the usb controller. With the help of Heiko I've found two ways to get the usb_ether driver to register: dt-way: - add of match in ether.c: diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 63d552bc8b..8e2a05a5af 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -2690,10 +2690,16 @@ int usb_ether_init(void) return 0; } +static const struct udevice_id usb_ether_ids[] = { + { .compatible = "gadget,usb_ether" }, + { } +}; + U_BOOT_DRIVER(eth_usb) = { .name = "usb_ether", .id = UCLASS_ETH, .probe = usb_eth_probe, + .of_match = usb_ether_ids, .ops = &usb_eth_ops, .priv_auto_alloc_size = sizeof(struct ether_priv), .platdata_auto_alloc_size = sizeof(struct eth_pdata), - then add it directly in your board u-boot.dts: +&usbotg1 { + usb_ether0 { + compatible = "gadget,usb_ether"; + status = "okay"; + }; +}; The non-dt way: - bind it manually in board code with: { struct udevice *dev; struct udevice *usb_dev; int ret; ret = uclass_first_device(UCLASS_USB, &usb_dev); if (!usb_dev || ret) printf("%s: No USB device found\n", __func__); ret = device_bind_driver(usb_dev, "usb_ether", "usb_ether", &dev); if (!dev || ret) printf("%s: usb - not able to bind usb_ether device\n", __func__); } - Note that this is the same code from usb_ether_init() but with UCLASS_USB instead of UCLASS_USB_GADGET_GENERIC What is the intended way to bind the usb_ether gadget device at runtime? Additionally Heiko found that once bound and usb_ether is registered as a network device using a network command like ping/tftpboot calls usb_setup_ehci_gadget() which removes the USB driver ... and so also the child usb ethernet gadget device then re-probes only the usb driver and not the gadget thus fails. I compared this to how the 'ums' command works and that also removes the usb driver and child nodes but because ums isn't a gadget driver it doesn't get removed and works. Best Regards, Tim

5 12

[PATCH v2] riscv: cancel the limitation that NR_CPUS is less than or equal to 32
by Xiang W 13 Feb '23

13 Feb '23

Various specifications of riscv allow the number of hart to be greater than 32. The limit of 32 is determined by gd->arch.available_harts. We can eliminate this limitation through bitmaps. Currently, the number of hart is limited to 4095, and 4095 is the limit of the RISC-V Advanced Core Local Interruptor Specification. Test on sifive unmatched. Signed-off-by: Xiang W <wxjstz(a)126.com> --- Changes since v1: * When NR_CPUS is very large, the value of GD_AVAILABLE_HARTS will overflow the immediate range of ld/lw. This patch fixes this problem arch/riscv/Kconfig | 4 ++-- arch/riscv/cpu/start.S | 21 ++++++++++++++++----- arch/riscv/include/asm/global_data.h | 4 +++- arch/riscv/lib/smp.c | 2 +- 4 files changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ba29e70acf..7b9c7f5bca 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -220,8 +220,8 @@ config SPL_SMP all, single processor machines. config NR_CPUS - int "Maximum number of CPUs (2-32)" - range 2 32 + int "Maximum number of CPUs (2-4095)" + range 2 4095 depends on SMP || SPL_SMP default 8 help diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 76850ec9be..92f3b78f29 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -166,11 +166,22 @@ wait_for_gd_init: mv gp, s0 /* register available harts in the available_harts mask */ - li t1, 1 - sll t1, t1, tp - LREG t2, GD_AVAILABLE_HARTS(gp) - or t2, t2, t1 - SREG t2, GD_AVAILABLE_HARTS(gp) + li t1, GD_AVAILABLE_HARTS + add t1, t1, gp + LREG t1, 0(t1) +#if defined(CONFIG_ARCH_RV64I) + srli t2, tp, 6 + slli t2, t2, 3 +#elif defined(CONFIG_ARCH_RV32I) + srli t2, tp, 5 + slli t2, t2, 2 +#endif + add t1, t1, t2 + LREG t2, 0(t1) + li t3, 1 + sll t3, t3, tp + or t2, t2, t3 + SREG t2, 0(t1) amoswap.w.rl zero, zero, 0(t0) diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 095484a635..6de2ee0b25 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -10,9 +10,11 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include <config.h> #include <asm/smp.h> #include <asm/u-boot.h> #include <compiler.h> +#include <linux/bitops.h> /* Architecture-specific global data */ struct arch_global_data { @@ -28,7 +30,7 @@ struct arch_global_data { struct ipi_data ipi[CONFIG_NR_CPUS]; #endif #ifndef CONFIG_XIP - ulong available_harts; + ulong available_harts[BITS_TO_LONGS(CONFIG_NR_CPUS)]; #endif }; diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ba992100ad..e8e391fd41 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -47,7 +47,7 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) #ifndef CONFIG_XIP /* skip if hart is not available */ - if (!(gd->arch.available_harts & (1 << reg))) + if (!test_bit(reg, gd->arch.available_harts)) continue; #endif -- 2.30.2

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[PATCH v2 0/5] Add ARMv8 CE sha1/sha256 support
by Loic Poulain 08 Feb '23

08 Feb '23

This series adds support for the SHA-1 and SHA-256 Secure Hash Algorithm for CPUs that have support of the ARM v8 Crypto Extensions. It Improves speed of integrity & signature checking procedures. V2: - Add cover letter & sha256 support. - Kconfig default 'y' only if SHA1 and SHA256 selected Loic Poulain (5): lib: sha1: Add support for hardware specific sha1_process sha1: Fix digest state size/type armv8 SHA-1 using ARMv8 Crypto Extensions: lib: sha256: Add support for hardware specific sha256_process armv8 SHA-256 using ARMv8 Crypto Extensions arch/arm/cpu/armv8/Kconfig | 15 ++++ arch/arm/cpu/armv8/Makefile | 2 + arch/arm/cpu/armv8/sha1_ce_core.S | 132 +++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/sha1_ce_glue.c | 21 ++++++ arch/arm/cpu/armv8/sha256_ce_core.S | 134 ++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/sha256_ce_glue.c | 21 ++++++ include/u-boot/sha1.h | 2 +- lib/sha1.c | 26 +++++-- lib/sha256.c | 26 +++++-- 9 files changed, 364 insertions(+), 15 deletions(-) create mode 100644 arch/arm/cpu/armv8/sha1_ce_core.S create mode 100644 arch/arm/cpu/armv8/sha1_ce_glue.c create mode 100644 arch/arm/cpu/armv8/sha256_ce_core.S create mode 100644 arch/arm/cpu/armv8/sha256_ce_glue.c -- 2.7.4

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[PATCH] RFC: nvedit: support doing one (extra) expansion of the value in "env set"
by Rasmus Villemoes 02 Feb '23

02 Feb '23

Currently, there's no way to fetch the value of an environment variable whose name is stored in some other variable, or generated from such - in non-working pseudo-code, ${${varname}} ${array${index}} This forces some scripts to needlessly duplicate logic and hardcode assumptions. For example, in an A/B scheme with three variables BOOT_ORDER # Either "A B" or "B A" depending on which slot was last updated BOOT_A_LEFT # 0..3 BOOT_B_LEFT # 0..3 when one needs to determine the slot to boot from, one does something like setenv found for slot in $BOOT_ORDER ; do if test "x$found" != "x" ; then # work around lack of break elif test "x$slot" = "xA" ; then if test $BOOT_A_LEFT -gt 0 ; then setexpr BOOT_A_LEFT $BOOT_A_LEFT - 1 setenv found A setenv bootargs ${bootargs_A} setenv ubivol ${ubivol_A} # more setup based on A fi elif test "x$slot" = "xB" ; then if test $BOOT_B_LEFT -gt 0 ; then # the same ... fi fi done This is already bad enough, but extending that to A/B/C is tedious and prone to copy-pastos. So this is an attempt at allowing one to do "env set -E var value1 value2" with the effect that, of course, normal variable expansion happens on the command line, the valueX are joined with spaces as usual, and then one more pass is done over that string replacing occurrences of ${foo}. The above would become setenv found for slot in $BOOT_ORDER ; do if test "x$found" != "x" ; then # work around lack of break else env set -E boot_left "\${BOOT_${slot}_LEFT}" if test $boot_left -gt 0 ; then setexpr BOOT_${slot}_LEFT $boot_left - 1 env set found $slot env set -E bootargs "\${bootargs_${slot}}" env set -E ubivol "\${ubivol_${slot}}" fi fi done I'm pleasantly surprised it was that easy to implement, but of course I'm cheating a bit (cli_simple_process_macros is only available if CONFIG_CMDLINE, though I think cli_simple.o could be unconditionally built and then link-time GC should get rid of the excess functions). This has been lightly tested in the sandbox. I'll add some proper unit tests, update the help texts and try to handle the Kconfig issue if this is something that might be accepted. Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- cmd/nvedit.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 81d94cd193..ff6ffcb674 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -224,7 +224,7 @@ DONE: */ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) { - int i, len; + int i, len, expand = 0; char *name, *value, *s; struct env_entry e, *ep; @@ -244,6 +244,9 @@ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) case 'f': /* force */ env_flag |= H_FORCE; break; + case 'E': + expand = 1; + break; default: return CMD_RET_USAGE; } @@ -287,6 +290,18 @@ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) if (s != value) *--s = '\0'; + if (expand) { + char *expanded = malloc(CONFIG_SYS_CBSIZE); + + if (expanded == NULL) { + printf("## Can't malloc %d bytes\n", CONFIG_SYS_CBSIZE); + free(value); + return 1; + } + cli_simple_process_macros(value, expanded); + free(value); + value = expanded; + } e.key = name; e.data = value; hsearch_r(e, ENV_ENTER, &ep, &env_htab, env_flag); -- 2.23.0

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[PATCH] arm: kirkwood: Add nas440 board, Marvell 88SE6121 AHCI
by Hajo Noerenberg 30 Jan '23

30 Jan '23

This adds support for the Seagate Blackarmor NAS440 (4-bay Kirkwood NAS box). Does it make sense to include support for a 10+ year old device? If yes, I would be willing to discuss and finalize this patch. If no, it will be archived here for the public, which is fine with me. For the NAS440 is the something special that hard disk drives 1 and 2 are connected to a 88SE6121 SATA-II controller, which is connected via PCIe. Hard disk drives 3 and 4 are directly connected to the 88F6281 SoC. - Add NAS440 dtb and associated files/configs * Includes support for HD44780 front LCD * Includes support for device LEDs (via 74AHC164 shift register) - Add Marvell 88SE6121 AHCI support. Thanks to Pali Rohár for recently adding the necessary Kirkwood PCIe driver. It works :) - Tested with my NAS440 hardware: ETH/USB/SATA/AHCI-SCSI/GPIO/LCD/LEDs ok As far as I can see this fully implements the support for this board within U-Boot. With the Linux kernel however there are problems, the kernel AHCI driver fails with "failed to IDENTIFY" messages for the 88SE6121 drive ports, which I could not solve yet despite comparison with the GPL sources from Seagate. Note: I am collecting various information and patches for the family of Blackarmor NAS boards at https://github.com/hn/seagate-blackarmor-nas Hajo --- arch/arm/dts/kirkwood-blackarmor-nas440.dts | 166 +++++++++ board/Seagate/nas440/Kconfig | 12 + board/Seagate/nas440/MAINTAINERS | 7 + board/Seagate/nas440/Makefile | 7 + board/Seagate/nas440/kwbimage.cfg | 156 ++++++++ board/Seagate/nas440/nas440.c | 378 ++++++++++++++++++++ configs/nas440_defconfig | 89 +++++ drivers/ata/ahci-pci.c | 1 + include/configs/nas440.h | 50 +++ 9 files changed, 866 insertions(+) create mode 100644 arch/arm/dts/kirkwood-blackarmor-nas440.dts create mode 100644 board/Seagate/nas440/Kconfig create mode 100644 board/Seagate/nas440/MAINTAINERS create mode 100644 board/Seagate/nas440/Makefile create mode 100644 board/Seagate/nas440/kwbimage.cfg create mode 100644 board/Seagate/nas440/nas440.c create mode 100644 configs/nas440_defconfig create mode 100644 include/configs/nas440.h diff --git a/arch/arm/dts/kirkwood-blackarmor-nas440.dts b/arch/arm/dts/kirkwood-blackarmor-nas440.dts new file mode 100644 index 0000000000..60e3fe6f0d --- /dev/null +++ b/arch/arm/dts/kirkwood-blackarmor-nas440.dts @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for Seagate Blackarmor NAS440 + * + * Copyright (C) 2021 Hajo Noerenberg <www.github.com/hn> + * Copyright (C) 2015 Andreas Fischer <af(a)bantuX.org> + * Copyright (C) 2014 Evgeni Dobrev <evgeni(a)studio-punkt.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Seagate Blackarmor NAS440"; + compatible = "seagate,blackarmor-nas440","marvell,kirkwood-88f6281", + "marvell,kirkwood"; + + memory { /* 256 MB */ + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO1-16 is MPP48 */ + }; + + gpio_keys { + compatible = "gpio-keys"; + + reset { + label = "Reset"; + linux,code = <KEY_POWER>; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + + button { + label = "Power"; + linux,code = <KEY_SLEEP>; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; /* GPIO1-17 is MPP49 */ + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_power_socsata>; + pinctrl-names = "default"; + + socsata_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SoC SATA Power"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* + * Serial port routed to connector CN4 + * + * pin 1 - TX (CPU's TX) + * pin 4 - RX (CPU's RX) + * pin 6 - GND + */ +&uart0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-0 = <&pmx_button_reset &pmx_button_power>; + pinctrl-names = "default"; + + pmx_act_sata0: pmx-act-sata0 { + marvell,pins = "mpp15"; + marvell,function = "sata0"; + }; + + pmx_act_sata1: pmx-act-sata1 { + marvell,pins = "mpp16"; + marvell,function = "sata1"; + }; + + pmx_power_socsata: pmx-power-socsata { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_button_power: pmx-button-power { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + adt7473: thermal@2e { + compatible = "adi,adt7473"; + reg = <0x2e>; + }; +}; + +&nand { + status = "okay"; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; + ethphy1: ethernet-phy@9 { + reg = <9>; + }; +}; + +&eth0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <&ethphy0>; + }; +}; + +&eth1 { + status = "okay"; + + ethernet1-port@0 { + phy-handle = <&ethphy1>; + }; +}; diff --git a/board/Seagate/nas440/Kconfig b/board/Seagate/nas440/Kconfig new file mode 100644 index 0000000000..3f93d75cd4 --- /dev/null +++ b/board/Seagate/nas440/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NAS440 + +config SYS_BOARD + default "nas440" + +config SYS_VENDOR + default "Seagate" + +config SYS_CONFIG_NAME + default "nas440" + +endif diff --git a/board/Seagate/nas440/MAINTAINERS b/board/Seagate/nas440/MAINTAINERS new file mode 100644 index 0000000000..dcea1316c5 --- /dev/null +++ b/board/Seagate/nas440/MAINTAINERS @@ -0,0 +1,7 @@ +NAS440 BOARD +M: Hajo Noerenberg <hajo-uboot(a)noerenberg.de> +S: Maintained +F: board/Seagate/nas440/ +F: include/configs/nas440.h +F: configs/nas440_defconfig +F: arch/arm/dts/kirkwood-blackarmor-nas440.dts diff --git a/board/Seagate/nas440/Makefile b/board/Seagate/nas440/Makefile new file mode 100644 index 0000000000..2a3ef746d3 --- /dev/null +++ b/board/Seagate/nas440/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Evgeni Dobrev <evgeni(a)studio-punkt.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := nas440.o diff --git a/board/Seagate/nas440/kwbimage.cfg b/board/Seagate/nas440/kwbimage.cfg new file mode 100644 index 0000000000..e71da11694 --- /dev/null +++ b/board/Seagate/nas440/kwbimage.cfg @@ -0,0 +1,156 @@ +# +# Copyright (C) 2021 Hajo Noerenberg <hajo-uboot(a)noerenberg.de> +# +# Based on nas220/kwbimage.cfg originally written by +# Evgeni Dobrev <evgeni(a)studio-punkt.com> +# +# Based on sheevaplug/kwbimage.cfg originally written by +# Prafulla Wadaskar <prafulla(a)marvell.com> +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.kwbimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0200 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100E0 0x1B1B1B9B + +DATA 0xFFD20134 0xBBBBBBBB +DATA 0xFFD20138 0x00BBBBBB + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000C30 # DDR Configuration register +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x39543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000833 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000000C # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000042 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 0 +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 +DATA 0xFFD0147C 0x00008552 + +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000F80F # CPU ODT Control + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 + diff --git a/board/Seagate/nas440/nas440.c b/board/Seagate/nas440/nas440.c new file mode 100644 index 0000000000..43a08e61bf --- /dev/null +++ b/board/Seagate/nas440/nas440.c @@ -0,0 +1,378 @@ +/* + * Copyright (C) 2022 Hajo Noerenberg <hajo-uboot(a)noerenberg.de> + * + * Based on nas220.c originally written by + * Evgeni Dobrev <evgeni(a)studio-punkt.com> + * + * Based on sheevaplug.c originally written by + * Prafulla Wadaskar <prafulla(a)marvell.com> + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <init.h> +#include <netdev.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include <asm/global_data.h> +#include <asm/mach-types.h> +#include <linux/bitops.h> +#include <bootstage.h> +#include <linux/delay.h> +#include <asm/arch/gpio.h> +#include <version.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * GPIO pin names, input/output direction and default values + * + * NAS440_GPIO_BUTTON_LCD_LOWER, NAS440_GPIO_BUTTON_LCD_UPPER + * Buttons next to LC display, LOW if pressed + * + * NAS440_GPIO_BUTTON_POWER + * Power button at front of case, LOW if pressed + * + * NAS440_GPIO_BUTTON_RESET + * Reset button at back of case, LOW if pressed + * + * NAS440_GPIO_LCD_HD44780_* + * HD44780-compatible LC display, control via 8bit parallel data transfer + * + * NAS440_GPIO_LED_74AHC164_* + * Control front panel LEDs via 74AHC164 8bit shift register + * + * NAS440_GPIO_SOCSATA_POWER + * 12V Power for SoC SATA ports (NAS drives 3 and 4) + * + * NAS440_GPIO_BOARD_POWER + * Shutdown board if LOW + * + */ + +#define NAS440_GPIO_LCD_HD44780_BACKLIGHT 7 +#define NAS440_GPIO_LED_74AHC164_DATA 12 +#define NAS440_GPIO_LED_74AHC164_CLK 13 +#define NAS440_GPIO_SOCSATA_POWER 28 +#define NAS440_GPIO_BUTTON_RESET 29 +#define NAS440_GPIO_BUTTON_LCD_LOWER 34 +#define NAS440_GPIO_LCD_HD44780_RS 35 +#define NAS440_GPIO_LCD_HD44780_D0 36 +#define NAS440_GPIO_LCD_HD44780_D1 37 +#define NAS440_GPIO_LCD_HD44780_D2 38 +#define NAS440_GPIO_LCD_HD44780_D3 39 +#define NAS440_GPIO_LCD_HD44780_D4 40 +#define NAS440_GPIO_LCD_HD44780_D5 41 +#define NAS440_GPIO_LCD_HD44780_D6 42 +#define NAS440_GPIO_LCD_HD44780_D7 43 +#define NAS440_GPIO_LCD_HD44780_RW 44 +#define NAS440_GPIO_LCD_HD44780_E 45 +#define NAS440_GPIO_BUTTON_LCD_UPPER 47 +#define NAS440_GPIO_BOARD_POWER 48 +#define NAS440_GPIO_BUTTON_POWER 49 + +/* + * GPIO output enable, pins 0-31 to LOW, pins 31-49 to HIGH config register + */ +#define NAS440_GE_OE_LOW (~(BIT(NAS440_GPIO_LCD_HD44780_BACKLIGHT) \ + | BIT(NAS440_GPIO_LED_74AHC164_DATA) \ + | BIT(NAS440_GPIO_LED_74AHC164_CLK) \ + | BIT(NAS440_GPIO_SOCSATA_POWER))) +#define NAS440_GE_OE_HIGH (~(BIT_MASK(NAS440_GPIO_BOARD_POWER) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_RS) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D0) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D1) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D2) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D3) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D4) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D5) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D6) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D7) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_RW) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_E))) + +/* + * GPIO output default values + */ +#define NAS440_GE_OE_VAL_LOW BIT(NAS440_GPIO_LCD_HD44780_BACKLIGHT) + +#define NAS440_GE_OE_VAL_HIGH BIT_MASK(NAS440_GPIO_BOARD_POWER) + +int board_early_init_f(void) +{ + /* + * default gpio configuration + */ + mvebu_config_gpio(NAS440_GE_OE_VAL_LOW, NAS440_GE_OE_VAL_HIGH, + NAS440_GE_OE_LOW, NAS440_GE_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* NAS440_GPIO_LCD_HD44780_BACKLIGHT */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, /* NAS440_GPIO_LED_74AHC164_DATA */ + MPP13_GPIO, /* NAS440_GPIO_LED_74AHC164_CLK */ + MPP14_SATA1_PRESENTn, + MPP15_SATA0_ACTn, + MPP16_SATA1_ACTn, + MPP17_SATA0_PRESENTn, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, /* GbE Port1, RGMII mode (12 pins GE1_0-7, GE1_10-13) */ + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, /* NAS440_GPIO_SOCSATA_POWER */ + MPP29_GPIO, /* NAS440_GPIO_BUTTON_RESET */ + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, /* NAS440_GPIO_BUTTON_LCD_LOWER */ + MPP35_GPIO, /* NAS440_GPIO_LCD_HD44780_RS */ + MPP36_GPIO, /* NAS440_GPIO_LCD_HD44780_D0 */ + MPP37_GPIO, /* NAS440_GPIO_LCD_HD44780_D1 */ + MPP38_GPIO, /* NAS440_GPIO_LCD_HD44780_D2 */ + MPP39_GPIO, /* NAS440_GPIO_LCD_HD44780_D3 */ + MPP40_GPIO, /* NAS440_GPIO_LCD_HD44780_D4 */ + MPP41_GPIO, /* NAS440_GPIO_LCD_HD44780_D5 */ + MPP42_GPIO, /* NAS440_GPIO_LCD_HD44780_D6 */ + MPP43_GPIO, /* NAS440_GPIO_LCD_HD44780_D7 */ + MPP44_GPIO, /* NAS440_GPIO_LCD_HD44780_RW */ + MPP45_GPIO, /* NAS440_GPIO_LCD_HD44780_E */ + MPP46_GPIO, + MPP47_GPIO, /* NAS440_GPIO_BUTTON_LCD_UPPER */ + MPP48_GPIO, /* NAS440_GPIO_BOARD_POWER */ + MPP49_GPIO, /* NAS440_GPIO_BUTTON_POWER */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +/* HD44780 pins, data bits first, backlight last */ +static int hd44780_pins[12] = { + NAS440_GPIO_LCD_HD44780_D0, + NAS440_GPIO_LCD_HD44780_D1, + NAS440_GPIO_LCD_HD44780_D2, + NAS440_GPIO_LCD_HD44780_D3, + NAS440_GPIO_LCD_HD44780_D4, + NAS440_GPIO_LCD_HD44780_D5, + NAS440_GPIO_LCD_HD44780_D6, + NAS440_GPIO_LCD_HD44780_D7, + NAS440_GPIO_LCD_HD44780_E, + NAS440_GPIO_LCD_HD44780_RW, + NAS440_GPIO_LCD_HD44780_RS, + NAS440_GPIO_LCD_HD44780_BACKLIGHT +}; + +#define HD44780_NUM_COL 16 +#define HD44780_BUF_COL 40 +#define HD44780_NUM_ROW 2 + +#define HD44780_PIN_NUM (sizeof(hd44780_pins)/sizeof(int)) + +/* + * HD44780 LCD display commands - adapted from hd44780.h by Joerg Wunsch + * + * ---------------------------------------------------------------------------- + * "THE BEER-WARE LICENSE" (Revision 42): + * <joerg(a)FreeBSD.ORG> wrote this file. As long as you retain this notice you + * can do whatever you want with this stuff. If we meet some day, and you think + * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch + * ---------------------------------------------------------------------------- + */ + +#define HD44780_CMD_CLR \ + 0x01 +#define HD44780_CMD_HOME \ + 0x02 +#define HD44780_CMD_ENTMODE(inc, shift) \ + (0x04 | ((inc)? 0x02: 0) | ((shift)? 1: 0)) +#define HD44780_CMD_DISPCTL(disp, cursor, blink) \ + (0x08 | ((disp)? 0x04: 0) | ((cursor)? 0x02: 0) | ((blink)? 1: 0)) +#define HD44780_CMD_SHIFT(shift, right) \ + (0x10 | ((shift)? 0x08: 0) | ((right)? 0x04: 0)) +#define HD44780_CMD_FNSET(if8bit, twoline, font5x10) \ + (0x20 | ((if8bit)? 0x10: 0) | ((twoline)? 0x08: 0) | \ + ((font5x10)? 0x04: 0)) +#define HD44780_CMD_CGADDR(addr) \ + (0x40 | ((addr) & 0x3f)) +#define HD44780_CMD_DDADDR(addr) \ + (0x80 | ((addr) & 0x7f)) + +static void lcd_send(unsigned int val, int mode) +{ + udelay(1); + kw_gpio_set_value(NAS440_GPIO_LCD_HD44780_RS, mode); + udelay(1); + + kw_gpio_set_value(NAS440_GPIO_LCD_HD44780_E, 0); + for (int i=0; i<8; i++) { + kw_gpio_set_value(hd44780_pins[i], (val&(1<<i))>>i ); + } + udelay(1); + kw_gpio_set_value(NAS440_GPIO_LCD_HD44780_E, 1); + udelay(1); + kw_gpio_set_value(NAS440_GPIO_LCD_HD44780_E, 0); + udelay(50); +} + +void lcd_init(void) +{ + for (int i=0; i<HD44780_PIN_NUM; i++) { + kw_gpio_set_valid(hd44780_pins[i], GPIO_OUTPUT_OK); + kw_gpio_direction_output(hd44780_pins[i], i == (HD44780_PIN_NUM-1)); + } + + lcd_send(HD44780_CMD_FNSET(1, 1, 0), 0); + udelay(50); + lcd_send(HD44780_CMD_FNSET(1, 1, 0), 0); + udelay(50); + lcd_send(HD44780_CMD_FNSET(1, 1, 0), 0); + udelay(50); + lcd_send(HD44780_CMD_DISPCTL(1, 0, 0), 0); + udelay(50); + lcd_send(HD44780_CMD_CLR, 0); + udelay(50); + lcd_send(HD44780_CMD_ENTMODE(1, 0), 0); + + udelay(2000); +} + +void lcd_row(int row, char *buf) +{ + int p = 0; + + if (row >= HD44780_NUM_ROW) { + return; + } + + lcd_send(HD44780_CMD_DDADDR(HD44780_BUF_COL * row + 0), 0); + for (int i=0; i<HD44780_NUM_COL; i++) { + if (buf[i] == 0) { + p++; + } + lcd_send(p ? 32 : buf[i], 1); + } +} + +enum led_disk { + LED_DSK_OFF, + LED_DSK_RED + /* LED_DSK_GREEN disk activity led is controlled directly by the hardware */ +}; + +enum led_system { + LED_SYS_OFF, + LED_SYS_BLUE, + LED_SYS_RED +}; + +void led_init(void) +{ + kw_gpio_set_valid(NAS440_GPIO_LED_74AHC164_DATA, GPIO_OUTPUT_OK); + kw_gpio_direction_output(NAS440_GPIO_LED_74AHC164_DATA, 0); + kw_gpio_set_valid(NAS440_GPIO_LED_74AHC164_CLK, GPIO_OUTPUT_OK); + kw_gpio_direction_output(NAS440_GPIO_LED_74AHC164_CLK, 0); +} + +void led_set(enum led_disk disk1, enum led_disk disk2, enum led_disk disk3, + enum led_disk disk4, enum led_system front1 ) +{ + int ledbits = (0x81 | ((front1==LED_SYS_RED)? 0x08 : 0) | ((front1==LED_SYS_BLUE)? 0x04 : 0) \ + | ((disk1==LED_DSK_RED)? 0 : 0x02) | ((disk2==LED_DSK_RED)? 0 : 0x40) \ + | ((disk3==LED_DSK_RED)? 0 : 0x20) | ((disk4==LED_DSK_RED)? 0 : 0x10)); + + for (int i=0; i<8; i++) { + kw_gpio_set_value(NAS440_GPIO_LED_74AHC164_DATA, (ledbits >> i) & 1); + udelay(1); + kw_gpio_set_value(NAS440_GPIO_LED_74AHC164_CLK, 1); + kw_gpio_set_value(NAS440_GPIO_LED_74AHC164_CLK, 0); + } +} + +/* factory firmware delays hard disk spinup, presumably to avoid power peaks */ +void delay_hdd_spinup(void) +{ + lcd_row(1, "Delay HDD spinup"); + + for (int i = 0; i<2500; i++) { + udelay(1000); + } + + kw_gpio_set_valid(NAS440_GPIO_SOCSATA_POWER, GPIO_OUTPUT_OK); + kw_gpio_direction_output(NAS440_GPIO_SOCSATA_POWER, 1); +} + +#if CONFIG_IS_ENABLED(BOOTSTAGE) +void show_boot_progress(int val) +{ + switch (val) { +/* 0123456789abcdef */ + case BOOTSTAGE_ID_BOARD_INIT_DONE: + lcd_row(1, "Board init done"); + break; + case BOOTSTAGE_ID_USB_START: + lcd_row(1, "Init USB"); + break; + case BOOTSTAGE_ID_ETH_START: + lcd_row(1, "Init ethernet"); + break; + case BOOTSTAGE_ID_MAIN_LOOP: + lcd_row(1, "Wait for input"); + break; + case BOOTSTAGE_ID_RUN_OS: + lcd_row(1, "Starting Linux"); + break; + default: + if (val < 0) /* error */ + lcd_row(1, "Error"); + break; + } +} +#endif + +int board_eth_init(struct bd_info *bis) +{ + return cpu_eth_init(bis); +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_DB88F6281_BP; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + led_init(); + led_set(LED_DSK_OFF, LED_DSK_OFF, LED_DSK_OFF, LED_DSK_OFF, LED_SYS_BLUE); + + lcd_init(); + lcd_row(0, U_BOOT_VERSION ""); + + delay_hdd_spinup(); + + return 0; +} diff --git a/configs/nas440_defconfig b/configs/nas440_defconfig new file mode 100644 index 0000000000..74faf1a24b --- /dev/null +++ b/configs/nas440_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_SYS_KWD_CONFIG="board/Seagate/nas440/kwbimage.cfg" +CONFIG_SYS_TEXT_BASE=0x600000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_NAS440=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xA0000 +CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas440" +CONFIG_IDENT_STRING="\nNAS 440" +# CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; " +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="nas440> " +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SATA=y +CONFIG_CMD_PCI=y +CONFIG_CMD_DM=y +CONFIG_CMD_SCSI=y +CONFIG_CMD_NAND=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xa0000@0x0(uboot),0x010000@0xa0000(env),0x500000@0xc0000(uimage),0x1a40000@0x5c0000(rootfs)" +CONFIG_CMD_UBI=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_PARTITION_UUIDS is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SYS_ATA_STRIDE=4 +CONFIG_SYS_ATA_DATA_OFFSET=0x100 +CONFIG_SYS_ATA_REG_OFFSET=0x100 +CONFIG_SYS_ATA_ALT_OFFSET=0x100 +CONFIG_KIRKWOOD_GPIO=y +CONFIG_MVEBU_GPIO=y +CONFIG_GPIO_EXTRA_HEADER=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_GPIO=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_PHY_MARVELL=y +CONFIG_DM_ETH=y +CONFIG_MVGBE=y +CONFIG_MII=y +CONFIG_SATA_MV=y +CONFIG_SYS_SATA_MAX_DEVICE=2 +CONFIG_DM_RTC=y +CONFIG_RTC_MV=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y + +CONFIG_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_MVEBU=y +CONFIG_AHCI_PCI=y + +CONFIG_SCSI=y +CONFIG_SCSI_AHCI=y +CONFIG_DM_SCSI=y diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c index b1d231e0f9..af7e97dc4a 100644 --- a/drivers/ata/ahci-pci.c +++ b/drivers/ata/ahci-pci.c @@ -38,6 +38,7 @@ U_BOOT_DRIVER(ahci_pci) = { static struct pci_device_id ahci_pci_supported[] = { { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) }, { PCI_DEVICE(0x1b21, 0x0611) }, + { PCI_DEVICE(0x11ab, 0x6121) }, {}, }; diff --git a/include/configs/nas440.h b/include/configs/nas440.h new file mode 100644 index 0000000000..58e6afb2c3 --- /dev/null +++ b/include/configs/nas440.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2022 Hajo Noerenberg <hajo-uboot(a)noerenberg.de> + * + * based on work from: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_NAS440_H +#define _CONFIG_NAS440_H + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ + +#include "mv-common.h" + +/* + * Default environment variables + */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0"\ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ + "autostart=no\0"\ + "autoload=no\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_MVGBE +#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ +#define CONFIG_PHY_BASE_ADR 8 +#ifdef CONFIG_RESET_PHY_R +#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */ +#endif +#endif /* CONFIG_MVGBE */ + +/* + * SATA driver configuration + */ +#define CONFIG_LBA48 +#define CONFIG_SYS_64BIT_LBA + +#endif /* _CONFIG_NAS440_H */ -- 2.20.1

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[PATCH] phy: add of_set_phy_supported() helper, call from phy_config()
by Rasmus Villemoes 30 Jan '23

30 Jan '23

Currently, U-Boot doesn't parse a "max-speed" DT property in a phy's DT node. That property is a standard binding which should be honoured, and in linux that is done by the core phy code via a call to an of_set_phy_supported() helper. (Some ethernet drivers support a max-speed property in their DT node, but that's orthogonal to what the phy supports.) Add a similar helper in U-Boot, and call it from phy_config(). Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- Resending, this time including the u-boot list in recipients. Sorry for the duplicate. drivers/net/phy/phy.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index e6e1755518..ec690361e6 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -599,6 +599,20 @@ int phy_register(struct phy_driver *drv) return 0; } +static int of_set_phy_supported(struct phy_device *phydev) +{ + ofnode node = phy_get_ofnode(phydev); + u32 max_speed; + + if (!ofnode_valid(node)) + return 0; + + if (!ofnode_read_u32(node, "max-speed", &max_speed)) + return phy_set_supported(phydev, max_speed); + + return 0; +} + int phy_set_supported(struct phy_device *phydev, u32 max_speed) { /* The default values for phydev->supported are provided by the PHY @@ -1070,6 +1084,12 @@ __weak int board_phy_config(struct phy_device *phydev) int phy_config(struct phy_device *phydev) { + int ret; + + ret = of_set_phy_supported(phydev); + if (ret) + return ret; + /* Invoke an optional board-specific helper */ return board_phy_config(phydev); } -- 2.31.1

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