July 2022 - U-Boot

dtboverlay to U-Boot runtime dtb
by Peng Fan (OSS) 04 Jul '22

04 Jul '22

Hi, I did a test to do overlay for U-Boot runtime dtb, but after overlay finish, U-Boot DM driver not work properly because the of_node pointer is changed in a device. So I am thinking whether this is valid to overlay to runtime U-Boot dtb or not. The reason I try this is that I wanna overlay the EFI capsule signature to U-Boot dtb, then capsule update with authentication could work, otherwise I need integrate the signature in dts and rebuild the image. I understand current U-Boot not support overlay U-Boot runtime dtb, just thinking whether this is valid or should we support it. Thanks, Peng.

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[PATCH 0/5] Add support for versal specific cadence ospi driver
by Ashok Reddy Soma 04 Jul '22

04 Jul '22

This patch series does the following: * Move macros from cadence driver to cadence header file * Add new versal specific cadence ospi driver * Reset qspi flash in when driver probed * Enable/Disable apb linear mode based on dma usage * Fix cadence qspi flash speed programming T Karthik Reddy (5): spi: cadence-qspi: move cadence qspi macros to header file arm64: versal: Add versal specific cadence ospi driver spi: cadence-qspi: reset qspi flash for versal platform spi: cadence_qspi: Enable apb linear mode for apb read & write operations spi: cadence-qspi: Fix programming ospi flash speed MAINTAINERS | 1 + arch/arm/mach-versal/include/mach/hardware.h | 15 ++ configs/xilinx_versal_virt_defconfig | 2 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/cadence_ospi_versal.c | 237 +++++++++++++++++++ drivers/spi/cadence_qspi.c | 40 +++- drivers/spi/cadence_qspi.h | 189 +++++++++++++++ drivers/spi/cadence_qspi_apb.c | 163 +------------ include/zynqmp_firmware.h | 9 + 10 files changed, 510 insertions(+), 155 deletions(-) create mode 100644 drivers/spi/cadence_ospi_versal.c -- 2.17.1

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[PATCH] mtd: spi-nor-ids: Add support for flashes tested by xilinx
by Ashok Reddy Soma 04 Jul '22

04 Jul '22

Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> --- drivers/mtd/spi/spi-nor-ids.c | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 7050ddc397..5d8bf05ff8 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -82,6 +82,7 @@ const struct flash_info spi_nor_ids[] = { /* EON -- en25xxx */ { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, + { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) }, { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, #endif @@ -127,11 +128,17 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, + { INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) }, { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) }, { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, @@ -140,6 +147,10 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, + { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128, @@ -151,6 +162,10 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_4B_OPCODES) }, { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ @@ -176,8 +191,11 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, @@ -208,8 +226,10 @@ const struct flash_info spi_nor_ids[] = { { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, #ifdef CONFIG_SPI_FLASH_MT35XU + { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, #endif /* CONFIG_SPI_FLASH_MT35XU */ + { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ @@ -225,6 +245,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, @@ -275,6 +296,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("sst26wf016b", 0xbf2641, 0, 64 * 1024, 32, SECT_4K) }, { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, @@ -311,11 +333,19 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) }, { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { + INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + }, { INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q16jv", 0xef7015, 0, 64 * 1024, 32, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + }, { INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -362,6 +392,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -370,6 +405,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25q32bv", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -378,6 +414,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_XMC /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ -- 2.17.1

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[ANN] U-Boot v2022.07-rc6 released
by Tom Rini 04 Jul '22

04 Jul '22

Hey all, So it should be final release day. However, given the large number of pull requests that came in at the end of last week, I think it's better to do one more -rc today and release next Monday, the 11th. The -next branch is open, so if you had been preparing a PR for once the release was out, please send it for -next instead. In terms of a changelog, git log --merges v2022.07-rc5..v2022.07-rc6 contains what I've pulled but as always, better PR messages and tags will provide better results here. -- Tom

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[PATCH] usb: host: ehci-generic: Fix error check
by Andre Przywara 04 Jul '22

04 Jul '22

Commit 81755b8c20fe ("usb: host: ehci-generic: Make resets and clocks optional") improved the error check to cover the reset property being optional. However this was using the wrong error variable for the check, so would now never fail. Use the correct error variable for checking the result of reset_get_bulk(), to actually report genuine errors. Fixes: 81755b8c20fe ("usb: host: ehci-generic: Make resets and clocks optional") Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- Hi, apologies for messing up this simple patch of mine last month. I got confused by the mixed usage of "ret" and "err" in this function. This might endorse some cleanup, but I don't dare to touch this file again, especially not that late in the cycle. Cheers, Andre drivers/usb/host/ehci-generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c index 15267e9a05a..75c73bfe4e8 100644 --- a/drivers/usb/host/ehci-generic.c +++ b/drivers/usb/host/ehci-generic.c @@ -81,7 +81,7 @@ static int ehci_usb_probe(struct udevice *dev) } err = reset_get_bulk(dev, &priv->resets); - if (ret && ret != -ENOENT) { + if (err && err != -ENOENT) { dev_err(dev, "Failed to get resets (err=%d)\n", err); goto clk_err; } -- 2.35.3

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Adding a zynq board
by Christopher Bowman 04 Jul '22

04 Jul '22

Greetings, I have a board (Diligent Arty-Z7) for which I have a working U-boot. I’m not sure I’ve done it right but it does work on my board. I’d like to contribute this back and get it in U-boot. I see there is a configuration configs/xilinx_zynq_virt_defconfig which includes several boards. It would be attractive to simply add the device tree for my board to this list and have a working U-boot. However, as I understand it, each Zynq board needs to have some initial configuration done and this is done in the ps7_init_gpl.c file which I think is unique to every board. I don’t understand how the boards in the xilinx_zynq_virt_defconfig configuration are able to share a single ps7_init_gpl.c? Maybe they don’t? How do I determine if my board is compatible with the other boards if they’re sharing a ps7_init_gpl.c? Is it permissible to add a new config for a single zynq board or should I be trying to add it to xilinx_zynq_virt_defconfig? If someone could provide some perspective here or some direction on adding a new Zynq board that would be great. Thanks Christopher

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[PATCH v3 1/3] drivers: tee: optee: remove unused probe local variable
by Etienne Carriere 04 Jul '22

04 Jul '22

Removes local variable child in optee_probe() that is not used. Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere(a)linaro.org> --- No change since v2. New change not in v1 series. --- drivers/tee/optee/core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index a89d62aaf0..c1f5fc4c7a 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -642,7 +642,6 @@ static int optee_probe(struct udevice *dev) { struct optee_pdata *pdata = dev_get_plat(dev); u32 sec_caps; - struct udevice *child; int ret; if (!is_optee_api(pdata->invoke_fn)) { @@ -673,7 +672,7 @@ static int optee_probe(struct udevice *dev) * only bind the drivers associated to the supported OP-TEE TA */ if (IS_ENABLED(CONFIG_RNG_OPTEE)) { - ret = device_bind_driver(dev, "optee-rng", "optee-rng", &child); + ret = device_bind_driver(dev, "optee-rng", "optee-rng", NULL); if (ret) return ret; } -- 2.25.1

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[PATCH 1/1] riscv: allow building w/o DHCP, SCSI, VIRTIO
by Heinrich Schuchardt 04 Jul '22

04 Jul '22

Consider which boot devices are enabled in the definition of the BOOT_TARGET_DEVICES() macro. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- include/configs/qemu-riscv.h | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index f462895fb5..427da69d3f 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -33,11 +33,30 @@ /* Environment options */ #ifndef CONFIG_SPL_BUILD + +#if defined(CONFIG_CMD_DHCP) +#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +#define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#if defined(CONFIG_SCSI) +# define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) +#else +# define BOOT_TARGET_DEVICES_SCSI(func) +#endif + +#if defined(CONFIG_CMD_VIRTIO) +# define BOOT_TARGET_DEVICES_VIRTIO(func) func(VIRTIO, virtio, 0) +#else +# define BOOT_TARGET_DEVICES_VIRTIO(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ func(QEMU, qemu, na) \ - func(VIRTIO, virtio, 0) \ - func(SCSI, scsi, 0) \ - func(DHCP, dhcp, na) + BOOT_TARGET_DEVICES_VIRTIO(func) \ + BOOT_TARGET_DEVICES_SCSI(func) \ + BOOT_TARGET_DEVICES_DHCP(func) #include <config_distro_bootcmd.h> -- 2.36.1

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[PATCH 1/3] ram: rk3399: Fix .set_rate_index() error handling
by Lee Jones 04 Jul '22

04 Jul '22

Functions pointed to by this op pointer can return non-zero values indicating an error. Ensure any error value is propagated back up the call-chain. Signed-off-by: Lee Jones <lee.jones(a)linaro.org> --- drivers/ram/rockchip/sdram_rk3399.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index c0a06dcaed..0af0fa9e7b 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -3005,7 +3005,9 @@ static int sdram_init(struct dram_info *dram, params->base.stride = calculate_stride(params); dram_all_config(dram, params); - dram->ops->set_rate_index(dram, params); + ret = dram->ops->set_rate_index(dram, params); + if (ret) + return ret; debug("Finish SDRAM initialization...\n"); return 0; -- 2.37.0.rc0.104.g0611611a94-goog

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[PATCH 0/2] Command for entering mask rom USB download mode
by Michal Suchanek 04 Jul '22

04 Jul '22

Hello, many ARM SoCs have a mask rom feature that provides interface for downloading firmware over USB. Downstream rockchip u-boot has 'brom' or 'rbrom' command for this purpose, and downstream sunxi u-boot provides 'efex' command. p-boot has code for entering FEL on A64 SoC. With this patch I am able to activate the USB downloader on a rk3399 but the rkflashtool fails to communicate with the device. On a H2+ I can get into the FEL mode and get flash parameters. YMMV I don't have any great idea how to structure this so that the command does not need platform-specific code. Is there an example of a command that has platform-specific implementations? Thanks Michal Andy Yan (1): cmd: boot: add brom cmd to reboot to brom dnl mode Michal Suchanek (1): cmd: boot: add brom cmd to reboot to FEL mode .../arm/include/asm/arch-rockchip/boot_mode.h | 1 + arch/arm/include/asm/arch-sunxi/cpu.h | 11 ++++++ arch/arm/mach-sunxi/Kconfig | 18 ++++++++++ arch/arm/mach-sunxi/board.c | 24 +++++++++++++ cmd/boot.c | 35 +++++++++++++++++++ 5 files changed, 89 insertions(+) -- 2.36.1

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