July 2022 - U-Boot

[PATCH 01/18] Convert CONFIG_E1000_NO_NVM to Kconfig
by Tom Rini 07 Jul '22

07 Jul '22

This converts the following to Kconfig: CONFIG_E1000_NO_NVM Signed-off-by: Tom Rini <trini(a)konsulko.com> --- configs/apalis-tk1_defconfig | 1 + configs/apalis_t30_defconfig | 1 + drivers/net/Kconfig | 4 ++++ include/configs/apalis-tk1.h | 3 --- include/configs/apalis_t30.h | 3 --- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 2d9c0ae18e37..0915bca64214 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -58,6 +58,7 @@ CONFIG_SYS_I2C_TEGRA=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y CONFIG_E1000=y +CONFIG_E1000_NO_NVM=y CONFIG_PCI=y CONFIG_PCI_TEGRA=y CONFIG_DM_PMIC=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index 2a8d3c6e0a35..f5d958646fa7 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -50,6 +50,7 @@ CONFIG_TFTP_TSIZE=y CONFIG_SPL_DM=y CONFIG_SYS_I2C_TEGRA=y CONFIG_E1000=y +CONFIG_E1000_NO_NVM=y CONFIG_PCI=y CONFIG_PCI_TEGRA=y CONFIG_SYS_NS16550=y diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 84d859c21eb8..56f9416a48db 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -239,6 +239,10 @@ config E1000 <http://support.intel.com/support/network/adapter/pro100/21397.htm> +config E1000_NO_NVM + bool "Intel PRO/1000 has no NVMEM / EEPROM" + depends on E1000 + config E1000_SPI_GENERIC bool "Allow access to the Intel 8257x SPI bus" depends on E1000 diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 19e6a1e04eeb..a362282a291e 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -22,9 +22,6 @@ /* PCI host support */ #undef CONFIG_PCI_SCAN_SHOW -/* PCI networking support */ -#define CONFIG_E1000_NO_NVM - /* * Custom Distro Boot configuration: * 1. 8bit SD port (MMC1) diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 104c4135e284..84bd88f835ae 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -23,9 +23,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* PCI networking support */ -#define CONFIG_E1000_NO_NVM - #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ "uboot_blk=0\0" \ -- 2.25.1

2 24

[PATCH v2 0/6] patman: Small fixes plus remove --no-tree from checkpatch for linux
by Douglas Anderson 07 Jul '22

07 Jul '22

The whole point of this series is really to make it so that when we're using patman for sending Linux patches that we don't pass "--no-tree" to checkpatch. While doing that, though, I found a number of bugs including an explanation about why recent version of patman have been yelling about "tags" when used with Linux even though Linux is supposed to have "process_tags" defaulted to False. Changes in v2: - Fix doc string for --ignore-bad-tags - Make comment about parsing three times less nonsensical. Douglas Anderson (6): patman: Fix updating argument defaults from settings patman: Fix implicit command inserting patman: Don't look at sys.argv when parsing settings patman: Make most bool arguments BooleanOptionalAction patman: By default don't pass "--no-tree" to checkpatch for linux patman: Take project defaults into account for --help tools/patman/checkpatch.py | 11 ++++-- tools/patman/control.py | 7 ++-- tools/patman/main.py | 77 ++++++++++++++++++++++---------------- tools/patman/settings.py | 46 ++++++++++++----------- 4 files changed, 80 insertions(+), 61 deletions(-) -- 2.37.0.rc0.161.g10f37bed90-goog

4 17

[PATCH] ARM: zynq: DT: Enable all FCLKs by default
by Michal Simek 07 Jul '22

07 Jul '22

From: Christian Kohn <christian.kohn(a)xilinx.com> The fclk-enable property is set to 0 which disables all FCLKs. Enable all FCLKs so they can be used as clock sources in the programmable logic. Signed-off-by: Christian Kohn <christian.kohn(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynq-7000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 37155df0fd42..9626a0714625 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -329,7 +329,7 @@ u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; - fclk-enable = <0>; + fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", -- 2.36.1

2 2

[PATCH v1] common: image-android: Add signature verification feature
by qianfanguijin＠163.com 07 Jul '22

07 Jul '22

From: qianfan Zhao <qianfanguijin(a)163.com> Not all Android tools use the id field for signing the image with sha1, so make this feature as optional and disabled default. Signed-off-by: qianfan Zhao <qianfanguijin(a)163.com> --- common/Kconfig.boot | 14 +++++++++++ common/image-android.c | 55 +++++++++++++++++++++++++++++++++++++----- 2 files changed, 63 insertions(+), 6 deletions(-) diff --git a/common/Kconfig.boot b/common/Kconfig.boot index a8d4be23a9..11fc8410a9 100644 --- a/common/Kconfig.boot +++ b/common/Kconfig.boot @@ -9,6 +9,20 @@ config ANDROID_BOOT_IMAGE This enables support for booting images which use the Android image format header. +if ANDROID_BOOT_IMAGE + +config ANDROID_BOOT_IMAGE_VERIFY + bool "Enable signature verification" + select SHA1 + default n + help + This option enables signature verification of Android Boot Images, + using a hash signed and verified using SHA1. + Not all Android tools use the id field for signing the image with + sha1, if you are unsure about this, Say N here. + +endif # ANDROID_BOOT_IMAGE + config FIT bool "Support Flattened Image Tree" select HASH diff --git a/common/image-android.c b/common/image-android.c index 1fbbbba1eb..011ef756a7 100644 --- a/common/image-android.c +++ b/common/image-android.c @@ -44,11 +44,54 @@ static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr) return hdr->kernel_addr; } +#if CONFIG_IS_ENABLED(ANDROID_BOOT_IMAGE_VERIFY) +/* + * Not all Android tools use the id field for signing the image with + * sha1 (or anything) so we make this as an optional. + */ +static void android_image_update_sha1(sha1_context *ctx, const void *buf, + u32 size) +{ + if (size > 0) { + sha1_update(ctx, buf, size); + size = cpu_to_le32(size); + sha1_update(ctx, (unsigned char *)&size, sizeof(size)); + } +} + +static int android_image_verify_sha1(const struct andr_img_hdr *hdr) +{ + unsigned char output[SHA1_SUM_LEN]; + sha1_context ctx; + const void *p; + + sha1_starts(&ctx); + + p = (void *)hdr + hdr->page_size; /* kernel */ + android_image_update_sha1(&ctx, p, hdr->kernel_size); + + p += ALIGN(hdr->kernel_size, hdr->page_size); /* ramdisk */ + android_image_update_sha1(&ctx, p, hdr->ramdisk_size); + + p += ALIGN(hdr->ramdisk_size, hdr->page_size); /* second */ + android_image_update_sha1(&ctx, p, hdr->second_size); + + sha1_finish(&ctx, output); + + return memcmp(output, (unsigned char *)hdr->id, sizeof(output)); +} +#else +static int android_image_verify_sha1(const struct andr_img_hdr *hdr) +{ + return 0; +} +#endif + /** * android_image_get_kernel() - processes kernel part of Android boot images * @hdr: Pointer to image header, which is at the start * of the image. - * @verify: Checksum verification flag. Currently unimplemented. + * @verify: Checksum verification flag. * @os_data: Pointer to a ulong variable, will hold os data start * address. * @os_len: Pointer to a ulong variable, will hold os data length. @@ -66,11 +109,11 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, const struct image_header *ihdr = (const struct image_header *) ((uintptr_t)hdr + hdr->page_size); - /* - * Not all Android tools use the id field for signing the image with - * sha1 (or anything) so we don't check it. It is not obvious that the - * string is null terminated so we take care of this. - */ + if (verify && android_image_verify_sha1(hdr)) { + puts("Bad Data Hash\n"); + return -EACCES; + } + strncpy(andr_tmp_str, hdr->name, ANDR_BOOT_NAME_SIZE); andr_tmp_str[ANDR_BOOT_NAME_SIZE] = '\0'; if (strlen(andr_tmp_str)) -- 2.25.1

1 0

[PATCH] xilinx: Remove the legacy property "#stream-id-cells"
by Michal Simek 07 Jul '22

07 Jul '22

From: Ayan Kumar Halder <ayankuma(a)amd.com> "#stream-id-cells" was being used with "mmu-masters" for Xen specific device trees. With Xen commit 2278d2cbb0b7c1b48b298c6c4c6a7de2271ac928 (Link below) Xen is able to support smmu bindings in both formats ie : 1. Using iommus (linux format) 2. Using mmu-masters (legacy format). Thus, "#stream-id-cells" which was used for the legacy format, can be removed as Xen can use smmu bindings in linux format. Link: https://www.mail-archive.com/xen-devel@lists.xenproject.org/msg101649.html Signed-off-by: Ayan Kumar Halder <ayankuma(a)amd.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/versal-mini-emmc0.dts | 1 - arch/arm/dts/versal-mini-emmc1.dts | 1 - arch/arm/dts/zynqmp.dtsi | 28 ---------------------------- 3 files changed, 30 deletions(-) diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts index 6a6e7467a233..7c81a82fb92d 100644 --- a/arch/arm/dts/versal-mini-emmc0.dts +++ b/arch/arm/dts/versal-mini-emmc0.dts @@ -47,7 +47,6 @@ xlnx,device_id = <0>; no-1-8-v; xlnx,mio-bank = <0>; - #stream-id-cells = <1>; }; }; diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts index c342e6bdf7ad..bf7569d4cca4 100644 --- a/arch/arm/dts/versal-mini-emmc1.dts +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -47,7 +47,6 @@ xlnx,device_id = <1>; no-1-8-v; xlnx,mio-bank = <0>; - #stream-id-cells = <1>; }; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index dae8f0669df8..fbc6e752da93 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -281,7 +281,6 @@ interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; @@ -295,7 +294,6 @@ interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; @@ -309,7 +307,6 @@ interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; @@ -323,7 +320,6 @@ interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; @@ -337,7 +333,6 @@ interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; @@ -351,7 +346,6 @@ interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; @@ -365,7 +359,6 @@ interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; @@ -379,7 +372,6 @@ interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; @@ -420,7 +412,6 @@ interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x868>; power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; @@ -434,7 +425,6 @@ interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x869>; power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; @@ -448,7 +438,6 @@ interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86a>; power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; @@ -462,7 +451,6 @@ interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86b>; power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; @@ -476,7 +464,6 @@ interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86c>; power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; @@ -490,7 +477,6 @@ interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86d>; power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; @@ -504,7 +490,6 @@ interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86e>; power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; @@ -518,7 +503,6 @@ interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86f>; power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; @@ -540,7 +524,6 @@ interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; @@ -554,7 +537,6 @@ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; @@ -569,7 +551,6 @@ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; @@ -584,7 +565,6 @@ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; @@ -599,7 +579,6 @@ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; @@ -676,7 +655,6 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - #stream-id-cells = <1>; iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { @@ -698,7 +676,6 @@ <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; @@ -730,7 +707,6 @@ interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; - #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; /* dma-coherent; */ @@ -745,7 +721,6 @@ reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x870>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; @@ -762,7 +737,6 @@ reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; - #stream-id-cells = <1>; iommus = <&smmu 0x871>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; @@ -892,7 +866,6 @@ interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; - #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; @@ -924,7 +897,6 @@ interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; - #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; -- 2.36.1

1 1

[PATCH] ARM: zynq: DT: List OCM memory
by Michal Simek 07 Jul '22

07 Jul '22

Description OCM with mmio-sram driver. In 99% use cases OCM is mapped high that's why it is placed on fixed location. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynq-7000.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 9626a0714625..c21c588bc711 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -192,6 +192,11 @@ reg = <0xf8006000 0x1000>; }; + ocmc: ocmc@f800c000 { + compatible = "mmio-sram"; + reg = <0xf800c000 0x1000>; + }; + uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; -- 2.36.1

1 0

[PATCH v2] doc: board: amlogic: add documentation on boot flow
by Neil Armstrong 07 Jul '22

07 Jul '22

This is a preliminary documentation introducing different boot sequences, and notably the recovery mode. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek(a)baylibre.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes since v1: - Christian Hewitt did an overall grammar correction of the text, meaning of the text hasn't changed, thus I kept the Reviewed-by tags doc/board/amlogic/boot-flow.rst | 134 ++++++++++++++++++++++++++++++++ doc/board/amlogic/index.rst | 1 + 2 files changed, 135 insertions(+) create mode 100644 doc/board/amlogic/boot-flow.rst diff --git a/doc/board/amlogic/boot-flow.rst b/doc/board/amlogic/boot-flow.rst new file mode 100644 index 0000000000..1ca81f3c89 --- /dev/null +++ b/doc/board/amlogic/boot-flow.rst @@ -0,0 +1,134 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Amlogic SoC Boot Flow +===================== + +The Amlogic SoCs have a pre-defined boot sequence in the SoC ROM code. Here are +the possible boot sources of different SoC families supported by U-Boot: + +GX* & AXG family +---------------- + ++----------+--------------------+-------+-------+---------------+---------------+ +| | 1 | 2 | 3 | 4 | 5 | ++==========+====================+=======+=======+===============+===============+ +| S905 | POC=0: SPI NOR | eMMC | NAND | SD Card | USB Device | +| S905X | | | | | | +| S905L | | | | | | +| S905W | | | | | | +| S912 | | | | | | ++----------+--------------------+-------+-------+---------------+---------------+ +| S805X | POC=0: SPI NOR | eMMC | NAND | USB Device | - | +| A113D | | | | | | +| A113X | | | | | | ++----------+--------------------+-------+-------+---------------+---------------+ + +POC pin: `NAND_CLE` + +Some boards provide a button to force USB BOOT which disables the eMMC clock signal +to bypass the eMMC stage. Others have removable eMMC modules; removing the eMMC and +SDCard will allow boot from USB. + +An exception is the lafrite board (aml-s805x-xx) which has no SDCard slot and boots +from SPI. The only ways to boot the lafrite board from USB are: + + - Erase the first sectors of SPI NOR flash + - Insert an HDMI boot plug forcing boot over USB + +The VIM1 and initial VIM2 boards provide a test point on the eMMC signals to block +the storage from answering and continue to the next boot step. + +The USB Device boot uses the first USB interface. On some boards this port is only +available on an USB-A type connector and needs an special Type-A to Type-A cable to +communicate with the BootROM. + +G12* & SM1 family +----------------- + ++-------+-------+-------+---------------+---------------+---------------+---------------+ +| POC0 | POC1 | POC2 | 1 | 2 | 3 | 4 | ++=======+=======+=======+===============+===============+===============+===============+ +| 0 | 0 | 0 | USB Device | SPI NOR | NAND/eMMC | SDCard | ++-------+-------+-------+---------------+---------------+---------------+---------------+ +| 0 | 0 | 1 | USB Device | NAND/eMMC | SDCard | - | ++-------+-------+-------+---------------+---------------+---------------+---------------+ +| 0 | 1 | 0 | SPI NOR | NAND/eMMC | SDCard | USB Device | ++-------+-------+-------+---------------+---------------+---------------+---------------+ +| 0 | 1 | 1 | SPI NAND | NAND/eMMC | USB Device | - | ++-------+-------+-------+---------------+---------------+---------------+---------------+ +| 1 | 0 | 0 | USB Device | SPI NOR | NAND/eMMC | SDCard | ++-------+-------+-------+---------------+---------------+---------------+---------------+ +| 1 | 0 | 1 | USB Device | NAND/eMMC | SDCard | - | ++-------+-------+-------+---------------+---------------+---------------+---------------+ +| 1 | 1 | 0 | SPI NOR | NAND/eMMC | SDCard | USB Device | ++-------+-------+-------+---------------+---------------+---------------+---------------+ +| 1 | 1 | 1 | NAND/eMMC | SDCard | USB Device | - | ++-------+-------+-------+---------------+---------------+---------------+---------------+ + +The last option (1/1/1) is the normal default seen on production devices. + + * POC0 pin: `BOOT_4` (0 and all other 1 means SPI NAND boot first) + * POC1 pin: `BOOT_5` (0 and all other 1 means USB Device boot first + * POC2 pin: `BOOT_6` (0 and all other 1 means SPI NOR boot first) + +Most boards provide a button to force USB BOOT which lowers `BOOT_5` to 0. Some boards +provide a test point on the eMMC or SPI NOR clock signals to block the storage from +answering and continue to the next boot step. + +The Khadas VIM3/3L boards embed a microcontroller which sets POC signals according +to its configuration or a specific key press sequence to either boot from SPI NOR +or eMMC then SDCard, or boot as an USB Device. + +The Odroid N2/N2+ has a hardware switch to select between SPI NOR or eMMC boot. + +Boot Modes +---------- + + * SDCard + +The BootROM fetches the first SDCard sectors in one sequence, then checks the content +of the data. The BootROM expects to find the FIP binary in sector 1, 512 bytes offset +from the start. + + * eMMC + +The BootROM fetches the first sectors in one sequence, first on the main partition, +and then on the Boot0 followed by Boot1 HW partitions. After each read, the BootROM +checks the data and looks to the next partition if it fails. The BootROM expects to +find the FIP binary in sector 1, 512 bytes offset from the start. + + * SPI NOR + +The BootROM fetches the first SPI NOR sectors in one sequence, then checks the content +of the data. The BootROM expects to find the FIP binary in sector 1, 512 bytes offset +from the start. + + * NAND & SPI NAND + +These modes are rarely used in open platforms and no details are available. + + * USB Device + +The BootROM sets the USB Gadget interface to serve a custom USB protocol with the +USB ID 1b8e:c003. The Amlogic `update` utility is designed to use this protocol. It +is also implemented in the Amlogic Vendor U-Boot. + +The open-source `pyamlboot` utility https://github.com/superna9999/pyamlboot also +implements this protocol and can load U-Boot in memory in order to start the SoC +without any attached storage or to recover from a failed/incorrect image flash. + +HDMI Recovery +------------- + +The BootROM also briefly reads 8 bytes at address I2C 0x52 offset 0xf8 (248) on the +HDMI DDC bus. If the content is `boot@USB` it will force USB boot mode. If the content +is `boot@SDC` it will force SDCard boot mode. + +If USB Device doesn't enumerate or SD Card boot step doesn't work, the BootROM will +continue with the normal boot sequence. + +Special boot dongles can be built by connecting a 256bytes EEPROM set to answer on +address 0x52, and program `boot@USB` or `boot@SDC` at offset 0xf8 (248). + +Note: If the SoC is booted with USB Device forced at first step, it will keep the boot +order on warm reboot. Only cold reboot (power removed) will reset the boot order. diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst index 9c7fadf2c0..8b9f1e2e1d 100644 --- a/doc/board/amlogic/index.rst +++ b/doc/board/amlogic/index.rst @@ -81,6 +81,7 @@ Boot Documentation :maxdepth: 1 pre-generated-fip + boot-flow Board Documentation ------------------- -- 2.25.1

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[PATCH] configs: sunxi: OrangePi Zero: enable Macronix flash support
by Michal Suchanek 07 Jul '22

07 Jul '22

The boards that come with a flash memory pre-soldered have a Macronix flash chip. Fixes: 280294c5df ("sunxi: boards: Enable SPI flash support in U-Boot proper") Signed-off-by: Michal Suchanek <msuchanek(a)suse.de> --- configs/orangepi_zero_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index 2dc69d2994..f7f3bfbcc4 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_CLK=624 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y CONFIG_SPI=y -- 2.36.1

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[PATCH v2] efi_loader: PE hashing for image with gap between sections
by Su, Bao Cheng 07 Jul '22

07 Jul '22

Some PE image has gap between sections. These gaps could be kernel symbol table that does not belong to any sections. For such kind of image, after the last section is added into the hashing, the bytes_hashed is less than the (PE file size - Size of AttributeCertificateTable). According to Step 14 of `Calculating the PE Image Hash` in the `Windows Authenticode Portable Executable Signature Format` Version 1.0 — March 21, 2008: " Create a value called FILE_SIZE, which is not part of the signature. Set this value to the image's file size, acquired from the underlying file system. If FILE_SIZE is greater than SUM_OF_BYTES_HASHED, the file contains extra data that must be added to the hash. This data begins at the SUM_OF_BYTES_HASHED file offset, and its length is: (File Size) - ((Size of AttributeCertificateTable) + SUM_OF_BYTES_HASHED) " Some overlapped data could be added into the hashing again. Some other tools such as sbgisn/pesign/EDK2 behave just as the Step 14 when dealing with such kind of PE image. However currently u-boot just ignores this overlapped data and refuses to hash them again. By toggling the `nocheck` of the efi_image_region_add to 1, the overlapping checking could be avoided. Signed-off-by: Baocheng Su <baocheng.su(a)siemens.com> --- Changes in v2: - Reword the commit message for better understanding. lib/efi_loader/efi_image_loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index 9611398885..d85fb6ba08 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -481,7 +481,7 @@ bool efi_image_parse(void *efi, size_t len, struct efi_image_regions **regp, EFI_PRINT("extra data for hash: %zu\n", len - (bytes_hashed + authsz)); efi_image_region_add(regs, efi + bytes_hashed, - efi + len - authsz, 0); + efi + len - authsz, 1); } /* Return Certificates Table */ -- 2.30.2

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[PATCH v2] misc: nuvoton: Add host interface configuartion driver
by Jim Liu 07 Jul '22

07 Jul '22

add nuvoton BMC npcm750 host configuartion driver Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- Changes for v2: - add kconfig and use depend for kconfig --- drivers/misc/Kconfig | 6 ++ drivers/misc/Makefile | 1 + drivers/misc/npcm_host_intf.c | 110 ++++++++++++++++++++++++++++++++++ 3 files changed, 117 insertions(+) create mode 100644 drivers/misc/npcm_host_intf.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 85ae7f62e9..265a7e510d 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -282,6 +282,12 @@ config MXC_OCOTP Programmable memory pages that are stored on the some Freescale i.MX processors. +config NPCM_HOST + bool "Enable support espi or LPC for Host" + depends on REGMAP && SYSCON + help + Enable NPCM BMC espi or LPC support for Host reading and writing. + config SPL_MXC_OCOTP bool "Enable MXC OCOTP driver in SPL" depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610) diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 7a6047f64f..51a534d535 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o +obj-$(CONFIG_NPCM_HOST) += npcm_host_intf.o obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o obj-$(CONFIG_P2SB) += p2sb-uclass.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o diff --git a/drivers/misc/npcm_host_intf.c b/drivers/misc/npcm_host_intf.c new file mode 100644 index 0000000000..0244e40457 --- /dev/null +++ b/drivers/misc/npcm_host_intf.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Host interface (LPC or eSPI) configuration on Nuvoton BMC + * Copyright (c) 2022 Nuvoton Technology Corp. + */ + +#include <common.h> +#include <dm.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> + +#define SMC_CTL_REG_ADDR 0xc0001001 +#define SMC_CTL_HOSTWAIT 0x80 + +/* GCR Register Offsets */ +#define HIFCR 0x50 +#define MFSEL1 0x260 +#define MFSEL4 0x26c + +/* ESPI Register offsets */ +#define ESPICFG 0x4 +#define ESPIHINDP 0x80 + +/* MFSEL bit fileds */ +#define MFSEL1_LPCSEL BIT(26) +#define MFSEL4_ESPISEL BIT(8) + +/* ESPICFG bit fileds */ +#define CHSUPP_MASK GENMASK(27, 24) +#define IOMODE_MASK GENMASK(9, 8) +#define IOMODE_SDQ FIELD_PREP(IOMODE_MASK, 3) +#define MAXFREQ_MASK GENMASK(12, 10) +#define MAXFREQ_33MHZ FIELD_PREP(MAXFREQ_MASK, 2) + +/* ESPIHINDP bit fileds */ +#define AUTO_SBLD BIT(4) +#define AUTO_HS1 BIT(8) +#define AUTO_HS2 BIT(12) +#define AUTO_HS3 BIT(16) + +static int npcm_host_intf_bind(struct udevice *dev) +{ + struct regmap *syscon; + void __iomem *base; + u32 ch_supp, val; + u32 ioaddr; + const char *type; + int ret; + + /* Release host wait */ + setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT); + + syscon = syscon_regmap_lookup_by_phandle(dev, "syscon"); + if (IS_ERR(syscon)) { + dev_err(dev, "%s: unable to get syscon, dev %s\n", __func__, dev->name); + return PTR_ERR(syscon); + } + + ioaddr = dev_read_u32_default(dev, "ioaddr", 0); + if (ioaddr) + regmap_write(syscon, HIFCR, ioaddr); + + type = dev_read_string(dev, "type"); + if (!type) + return -EINVAL; + + if (!strcmp(type, "espi")) { + base = dev_read_addr_ptr(dev); + if (!base) + return -EINVAL; + + ret = dev_read_u32(dev, "channel-support", &ch_supp); + if (ret) + return ret; + + /* Select eSPI pins function */ + regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, 0); + regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, MFSEL4_ESPISEL); + + val = AUTO_SBLD | AUTO_HS1 | AUTO_HS2 | AUTO_HS3 | ch_supp; + writel(val, base + ESPIHINDP); + + val = readl(base + ESPICFG); + val &= ~(CHSUPP_MASK | IOMODE_MASK | MAXFREQ_MASK); + val |= IOMODE_SDQ | MAXFREQ_33MHZ | FIELD_PREP(CHSUPP_MASK, ch_supp); + writel(val, base + ESPICFG); + } else if (!strcmp(type, "lpc")) { + /* Select LPC pin function */ + regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, 0); + regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, MFSEL1_LPCSEL); + } + + return 0; +} + +static const struct udevice_id npcm_hostintf_ids[] = { + { .compatible = "nuvoton,npcm750-host-intf" }, + { .compatible = "nuvoton,npcm845-host-intf" }, + { } +}; + +U_BOOT_DRIVER(npcm_host_intf) = { + .name = "npcm_host_intf", + .id = UCLASS_MISC, + .of_match = npcm_hostintf_ids, + .bind = npcm_host_intf_bind, +}; -- 2.17.1

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