July 2022 - U-Boot

[PATCH v2 02/11] rockchip: idb: add basic functions
by Johan Jonker 09 Jul '22

09 Jul '22

On Rockchip SoCs with a NAND as boot device the information data base (IDB) loaded by the boot ROM is stored at the beginning of several erase blocks. Add basic functions for reading and writing. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- Changed V2: remove CamelCases remove randomizer remove sector1 info remove stop and info cmd remove block driver --- arch/arm/mach-rockchip/Kconfig | 12 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rockchip_idb.c | 1074 +++++++++++++++++++++++++ 3 files changed, 1087 insertions(+) create mode 100644 arch/arm/mach-rockchip/rockchip_idb.c diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 18aff548..0f464f1b 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -425,6 +425,18 @@ config ROCKCHIP_SPI_IMAGE config LNX_KRNL_IMG_TEXT_OFFSET_BASE default SYS_TEXT_BASE +config ROCKCHIP_IDB + bool "Use Rockchip IDB block device" + depends on BLK + help + This option enables the Rockchip IDB block device + +config SPL_ROCKCHIP_IDB + bool "Use rockchip IDB block device in SPL" + depends on SPL_BLK + help + This option enables the Rockchip IDB block device in SPL + source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3066/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index ebe0afa2..36c33ba4 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o ifeq ($(CONFIG_TPL_BUILD),) obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o +obj-$(CONFIG_$(SPL_)ROCKCHIP_IDB) += rockchip_idb.o endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o diff --git a/arch/arm/mach-rockchip/rockchip_idb.c b/arch/arm/mach-rockchip/rockchip_idb.c new file mode 100644 index 00000000..6a2af329 --- /dev/null +++ b/arch/arm/mach-rockchip/rockchip_idb.c @@ -0,0 +1,1074 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Johan Jonker <jbx6244(a)gmail.com> + */ + +#include <clk.h> +#include <dm.h> +#include <memalign.h> +#include <linux/iopoll.h> + +#define NFC_DEF_TIMEOUT 20000 +#define NFC_ECC_MAX_MODES 4 +#define NFC_READ 0 +#define NFC_WRITE 1 + +#define NFC_FMCTL 0x00 +#define FMCTL_WP BIT(8) +#define FMCTRL_CE_SEL_M 0xFF +#define FMCTL_RDY BIT(9) + +#define NFC_FMWAIT 0x04 + +#define FLCTL_RST BIT(0) +#define FLCTL_WR 0x1 +#define FLCTL_XFER_ST BIT(2) +#define FLCTL_XFER_EN BIT(3) +#define FLCTL_ST_BUF_S 0x4 +#define FLCTL_XFER_COUNT BIT(5) +#define FLCTL_ACORRECT BIT(10) +#define FLCTL_XFER_READY BIT(20) + +#define BCHCTL_BANK_M (7 << 5) +#define BCHCTL_BANK (5) + +#define ECC_ERR_CNT(x, e) ((((x) >> (e).low) & (e).low_mask) | \ + (((x) >> (e).high) & (e).high_mask) << (e).low_bn) + +#define NFC_BANK 0x800 +#define NFC_BANK_STEP 0x100 +#define BANK_DATA 0x00 +#define BANK_ADDR 0x04 +#define BANK_CMD 0x08 + +#define NFC_SRAM0 0x1000 +#define NFC_SRAM_SIZE 0x400 + +#define NAND_CMD_READ0 0 +#define NAND_CMD_PAGEPROG 0x10 +#define NAND_CMD_READSTART 0x30 +#define NAND_CMD_ERASE1 0x60 +#define NAND_CMD_SEQIN 0x80 +#define NAND_CMD_READID 0x90 +#define NAND_CMD_ERASE2 0xd0 +#define NAND_CMD_RESET 0xff + +#define DATA_STEP 1024 +#define OOB_STEP 4 +#define LBA 64 + 512 + 33 + +#define DEFAULT_BLKS 8 +#define DEFAULT_STRENGTH 24 + +#define RK_MAGIC 0xFCDC8C3B + +struct sector0 { + u32 magic; + u8 reserved[4]; + u32 rc4_flag; + u16 boot_code1_offset; + u16 boot_code2_offset; + u8 reserved1[490]; + u16 flash_data_size; + u16 flash_boot_size; + u8 reserved2[2]; +} __packed; + +struct nand_para_info { + u8 id_bytes; + u8 nand_id[6]; + u8 vendor; + u8 die_per_chip; + u8 sec_per_page; + u16 page_per_blk; + u8 cell; + u8 plane_per_die; + u16 blk_per_plane; + u16 operation_opt; + u8 lsb_mode; + u8 read_retry_mode; + u8 ecc_bits; + u8 access_freq; + u8 opt_mode; + u8 die_gap; + u8 bad_block_mode; + u8 multi_plane_mode; + u8 slc_mode; + u8 reserved[5]; +}; + +struct idb { + int blk; + int ecc; + int sectors; +}; + +enum nfc_type { + NFC_V6, + NFC_V8, + NFC_V9, +}; + +struct ecc_cnt_status { + u8 err_flag_bit; + u8 low; + u8 low_mask; + u8 low_bn; + u8 high; + u8 high_mask; +}; + +struct nfc_cfg { + enum nfc_type type; + u8 ecc_strengths[NFC_ECC_MAX_MODES]; + u32 ecc_cfgs[NFC_ECC_MAX_MODES]; + u32 flctl_off; + u32 bchctl_off; + u32 dma_cfg_off; + u32 dma_data_buf_off; + u32 dma_oob_buf_off; + u32 dma_st_off; + u32 bch_st_off; + u32 randmz_off; + u32 int_en_off; + u32 int_clr_off; + u32 int_st_off; + u32 oob0_off; + u32 oob1_off; + struct ecc_cnt_status ecc0; + struct ecc_cnt_status ecc1; +}; + +struct rk_idb { + void __iomem *regs; + struct clk nfc_clk; + struct clk ahb_clk; + const struct nfc_cfg *cfg; + int selected_bank; + u32 bank_offset; + struct nand_para_info *info; + u32 boot_blks; + u32 boot_ecc; + u32 pages_per_blk; + struct idb idblock[5]; + u32 blk_counter; + u32 sectors; + u16 page_table[512]; + char *check; + char *idb; +}; + +struct nand_para_info nand_para_tbl[] = { + {6, {0x2c, 0x64, 0x44, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 2048, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x44, 0x44, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 1064, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x68, 0x04, 0x4a, 0xa9, 0x00}, 4, 1, 8, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x88, 0x04, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0xa8, 0x05, 0xcb, 0xa9, 0x00}, 4, 2, 16, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x68, 0x04, 0x46, 0x89, 0x00}, 4, 1, 8, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x48, 0x04, 0x4a, 0xa5, 0x00}, 4, 1, 8, 256, 2, 2, 1024, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x84, 0x64, 0x3c, 0xa5, 0x00}, 4, 1, 32, 512, 2, 2, 1024, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0x64, 0x54, 0xa9, 0x00}, 4, 1, 32, 512, 2, 2, 1024, 0x01df, 4, 18, 60, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0xd7, 0x94, 0x3e, 0x84, 0x00}, 4, 1, 8, 128, 2, 2, 4096, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x48, 0x04, 0x46, 0x85, 0x00}, 4, 1, 8, 256, 2, 2, 1024, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x88, 0x05, 0xc6, 0x89, 0x00}, 4, 2, 8, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x88, 0x24, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x68, 0x00, 0x27, 0xa9, 0x00}, 4, 1, 16, 128, 1, 2, 2048, 0x011f, 0, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x64, 0x64, 0x56, 0xa5, 0x00}, 4, 1, 24, 512, 2, 2, 700, 0x01df, 4, 18, 60, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x84, 0xc5, 0x4b, 0xa9, 0x00}, 4, 2, 16, 256, 2, 2, 2048, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0xd5, 0xd1, 0xa6, 0x68, 0x00}, 4, 2, 8, 64, 1, 2, 2048, 0x0117, 0, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0xdc, 0x90, 0xa6, 0x54, 0x00}, 4, 1, 8, 64, 1, 2, 1024, 0x0117, 0, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x64, 0x64, 0x54, 0xa4, 0x00}, 4, 1, 32, 512, 2, 1, 1024, 0x01df, 4, 18, 60, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0x44, 0x32, 0xaa, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 1, 0, 1, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x64, 0x44, 0x32, 0xa5, 0x00}, 4, 1, 32, 512, 2, 1, 1048, 0x05c7, 5, 19, 60, 32, 1, 0, 1, 0, 1, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x64, 0x64, 0x3c, 0xa5, 0x00}, 4, 1, 32, 512, 2, 1, 1044, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0x44, 0x32, 0xaa, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 4, 0, 1, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0x44, 0x34, 0xaa, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 4, 0, 1, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0xc4, 0x34, 0xaa, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 1, 0, 1, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0x44, 0x34, 0xa4, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 1, 0, 1, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0x64, 0x3c, 0xa9, 0x00}, 4, 1, 32, 512, 2, 2, 1024, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0xa4, 0x64, 0x32, 0xaa, 0x04}, 4, 1, 32, 1024, 2, 1, 2192, 0x05c7, 10, 19, 60, 32, 1, 0, 4, 0, 1, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xde, 0x94, 0xd2, 0x04, 0x43}, 2, 1, 16, 256, 2, 2, 2048, 0x01d9, 1, 1, 24, 32, 4, 0, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3}, 2, 1, 16, 256, 2, 2, 1024, 0x01d9, 1, 2, 40, 32, 4, 0, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xd7, 0x94, 0x91, 0x60, 0x44}, 2, 1, 16, 256, 2, 2, 1046, 0x01d9, 1, 3, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4}, 2, 1, 16, 256, 2, 2, 2090, 0x01d9, 1, 4, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xde, 0x94, 0xeb, 0x74, 0x44}, 2, 1, 32, 256, 2, 2, 1066, 0x01d9, 1, 7, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xd5, 0x94, 0xda, 0x74, 0xc4}, 2, 1, 16, 256, 2, 2, 530, 0x01d9, 1, 3, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xd7, 0x94, 0x9a, 0x74, 0x42}, 2, 1, 16, 256, 2, 2, 1024, 0x0119, 1, 0, 24, 32, 4, 0, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a}, 2, 1, 32, 256, 2, 2, 1060, 0x01d9, 2, 5, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xd7, 0x14, 0x9e, 0x34, 0x4a}, 2, 1, 16, 256, 2, 2, 1056, 0x01d9, 2, 5, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xde, 0x94, 0xa7, 0x42, 0x48}, 2, 1, 32, 256, 2, 2, 1060, 0x01d9, 2, 5, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xde, 0x14, 0xab, 0x42, 0x4a}, 2, 1, 32, 256, 2, 2, 1056, 0x01d9, 2, 6, 40, 32, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0x3a, 0x14, 0xab, 0x42, 0x4a}, 2, 1, 32, 256, 2, 2, 2092, 0x01d9, 2, 5, 40, 32, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xd5, 0x94, 0x9a, 0x74, 0x42}, 2, 1, 16, 256, 2, 1, 1024, 0x0111, 1, 0, 24, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0x3a, 0x14, 0x03, 0x08, 0x50}, 2, 1, 32, 388, 2, 2, 1362, 0x01d9, 9, 8, 40, 32, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x64, 0x44, 0x4b, 0xa9, 0x00}, 7, 1, 16, 256, 2, 2, 2048, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x88, 0x24, 0x4b, 0xa9, 0x84}, 7, 1, 16, 256, 2, 2, 2048, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x88, 0x24, 0x4b, 0xa9, 0x00}, 7, 1, 16, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x68, 0x24, 0x4a, 0xa9, 0x00}, 7, 1, 8, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x68, 0x04, 0x4a, 0xa9, 0x00}, 7, 1, 8, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0xd7, 0x94, 0x3e, 0x84, 0x00}, 7, 1, 8, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x68, 0x04, 0x46, 0xa9, 0x00}, 7, 1, 8, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x89, 0x64, 0x64, 0x3c, 0xa1, 0x00}, 7, 1, 32, 512, 2, 1, 1024, 0x01c7, 4, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x89, 0x84, 0x64, 0x3c, 0xa5, 0x00}, 7, 1, 32, 512, 2, 2, 1024, 0x01c7, 4, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x88, 0x24, 0x3b, 0xa9, 0x00}, 7, 1, 16, 192, 2, 2, 2048, 0x0117, 12, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xd7, 0x84, 0x93, 0x72, 0x57}, 1, 1, 32, 256, 2, 1, 1060, 0x05c1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xde, 0x84, 0x93, 0x72, 0x57}, 1, 1, 32, 256, 2, 1, 2092, 0x05c1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0x3a, 0x85, 0x93, 0x76, 0x57}, 1, 2, 32, 256, 2, 1, 2092, 0x05e1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xd5, 0x84, 0x32, 0x72, 0x56}, 1, 1, 16, 128, 2, 1, 2056, 0x05c1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xd7, 0x94, 0x32, 0x76, 0x56}, 1, 1, 16, 128, 2, 2, 2058, 0x05d1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xde, 0x94, 0x82, 0x76, 0x56}, 1, 1, 16, 256, 2, 2, 2062, 0x05d1, 1, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xde, 0x94, 0x93, 0x76, 0x50}, 1, 1, 32, 256, 2, 2, 1066, 0x05d9, 2, 34, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0x3a, 0x95, 0x93, 0x7a, 0x50}, 1, 2, 32, 256, 2, 2, 1066, 0x05d9, 2, 34, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xd7, 0x94, 0x32, 0x76, 0x55}, 1, 1, 16, 128, 2, 2, 2050, 0x0191, 2, 0, 24, 32, 1, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xde, 0x94, 0x93, 0x76, 0x57}, 1, 1, 32, 256, 2, 2, 1058, 0x05d9, 2, 33, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xd7, 0x84, 0x93, 0x72, 0x50}, 1, 1, 32, 256, 2, 1, 1060, 0x05c1, 2, 34, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xde, 0x94, 0x93, 0x76, 0x51}, 1, 1, 32, 256, 2, 2, 1074, 0x05d9, 2, 35, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0x3a, 0x94, 0x93, 0x76, 0x51}, 1, 1, 32, 256, 2, 2, 2106, 0x05d9, 2, 35, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xd7, 0x84, 0x93, 0x72, 0x51}, 1, 1, 32, 256, 2, 1, 1056, 0x05d9, 2, 35, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xde, 0x94, 0x93, 0x76, 0xd1}, 1, 1, 32, 256, 2, 2, 1074, 0x05d9, 2, 35, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0x94, 0x93, 0x76, 0x57}, 8, 1, 32, 256, 2, 2, 1058, 0x05d9, 2, 66, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xd7, 0x84, 0x93, 0x72, 0x57}, 8, 1, 32, 256, 2, 1, 1060, 0x05c1, 2, 66, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0xa4, 0x82, 0x76, 0x56}, 8, 1, 16, 256, 2, 2, 2082, 0x01d9, 1, 65, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0x94, 0x93, 0x76, 0x50}, 8, 1, 32, 256, 2, 2, 1066, 0x05d9, 2, 67, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xd7, 0x84, 0x93, 0x72, 0x50}, 8, 1, 32, 256, 2, 1, 1060, 0x05c1, 2, 67, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0xa4, 0x82, 0x76, 0xd7}, 8, 1, 16, 256, 2, 2, 2090, 0x04d9, 1, 66, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0x84, 0x93, 0x72, 0x57}, 8, 1, 32, 256, 2, 1, 2092, 0x05c1, 2, 66, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0x3a, 0x94, 0x93, 0x76, 0x51}, 8, 1, 32, 256, 2, 2, 2106, 0x01d9, 2, 68, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0x94, 0x93, 0x76, 0x51}, 8, 1, 32, 256, 2, 2, 1074, 0x01d9, 2, 68, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0x3a, 0xa4, 0x93, 0x7a, 0x50}, 8, 1, 32, 256, 2, 2, 2138, 0x05d9, 2, 0, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0x94, 0x82, 0x76, 0x56}, 8, 1, 16, 256, 2, 2, 2062, 0x01d9, 1, 0, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0x94, 0x93, 0x76, 0xd7}, 8, 1, 32, 256, 2, 2, 1058, 0x05d9, 2, 66, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0xec, 0xd7, 0x94, 0x7e, 0x64, 0x44}, 0, 1, 16, 128, 2, 2, 2048, 0x01d9, 2, 49, 60, 36, 3, 0, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xec, 0xde, 0xd5, 0x7e, 0x68, 0x44}, 0, 2, 16, 128, 2, 2, 2048, 0x01f9, 2, 49, 60, 36, 3, 0, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xec, 0xd7, 0x94, 0x7a, 0x54, 0x43}, 0, 1, 16, 128, 2, 2, 2076, 0x0199, 2, 0, 40, 36, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xec, 0xde, 0xd5, 0x7a, 0x58, 0x43}, 0, 2, 16, 128, 2, 2, 2076, 0x01b9, 2, 0, 40, 36, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xec, 0xd5, 0x94, 0x76, 0x54, 0x43}, 0, 1, 16, 128, 2, 2, 1038, 0x0119, 2, 0, 24, 36, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xec, 0xd7, 0x14, 0x76, 0x54, 0xc2}, 0, 1, 16, 128, 2, 2, 2076, 0x0491, 2, 0, 24, 40, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xec, 0xde, 0x94, 0xc3, 0xa4, 0xca}, 0, 1, 32, 792, 2, 1, 688, 0x04c1, 11, 50, 40, 32, 3, 1, 1, 0, 1, {0, 0, 0, 0, 0}}, +}; + +void rk_idb_build_page_table(struct rk_idb *plat, u32 lsb_mode) +{ + u32 counter; + u32 counter2; + + switch (lsb_mode) { + case 0: + counter = 0; + do { + u16 val = counter; + + plat->page_table[counter++] = val; + } while (counter != 512); + break; + case 1: + counter = 0; + do { + u16 val = counter; + + if (counter > 3) { + u16 offset; + + if (counter & 1) + offset = 3; + else + offset = 2; + val = 2 * counter - offset; + } + plat->page_table[counter++] = val; + } while (counter != 512); + break; + case 2: + counter = 0; + do { + u16 val = counter; + + if (counter > 1) + val = 2 * counter - 1; + plat->page_table[counter++] = val; + } while (counter != 512); + break; + case 3: + counter = 0; + do { + u16 val = counter; + + if (counter > 5) { + u16 offset; + + if (counter & 1) + offset = 5; + else + offset = 4; + val = 2 * counter - offset; + } + plat->page_table[counter++] = val; + } while (counter != 512); + break; + case 4: + counter = 8; + plat->page_table[0] = 0; + plat->page_table[1] = 1; + plat->page_table[2] = 2; + plat->page_table[3] = 3; + plat->page_table[4] = 4; + plat->page_table[5] = 5; + plat->page_table[6] = 7; + plat->page_table[7] = 8; + do { + u32 offset; + u32 val; + + if (counter & 1) + offset = 7; + else + offset = 6; + val = 2 * counter - offset; + plat->page_table[counter++] = val; + } while (counter != 512); + break; + case 5: + counter = 0; + counter2 = 16; + do { + u16 val = counter; + + plat->page_table[counter++] = val; + } while (counter != 16); + do { + plat->page_table[counter++] = counter2; + counter2 = counter2 + 2; + } while (counter != 512); + break; + case 6: + counter = 0; + counter2 = 0; + do { + u16 val = counter; + + if (counter > 5) { + u16 offset; + + if (counter & 1) + offset = 12; + else + offset = 10; + val = counter2 - offset; + } + plat->page_table[counter++] = val; + counter2 = counter2 + 3; + } while (counter != 512); + break; + case 9: + counter = 3; + counter2 = 3; + plat->page_table[0] = 0; + plat->page_table[1] = 1; + plat->page_table[2] = 2; + do { + plat->page_table[counter++] = counter2; + counter2 = counter2 + 2; + } while (counter != 512); + break; + case 10: + counter = 0; + counter2 = 63; + do { + u16 val = counter; + + plat->page_table[counter++] = val; + } while (counter != 63); + do { + plat->page_table[counter++] = counter2; + counter2 = counter2 + 2; + } while (counter != 512); + break; + case 11: + counter = 0; + do { + u16 val = counter; + + plat->page_table[counter++] = val; + } while (counter != 8); + do { + u32 offset; + u32 val; + + if (counter & 1) + offset = 7; + else + offset = 6; + val = 2 * counter - offset; + plat->page_table[counter++] = val; + } while (counter != 512); + break; + case 12: + counter = 4; + plat->page_table[0] = 0; + plat->page_table[1] = 1; + plat->page_table[2] = 2; + plat->page_table[3] = 3; + do { + u32 val = counter - 1 + (counter >> 1); + + plat->page_table[counter++] = val; + } while (counter != 512); + break; + } +} + +void rk_idb_rc4(u8 *buf, u32 len) +{ + u8 S[256], K[256], temp; + u32 i, j, t, x; + u8 key[16] = { 124, 78, 3, 4, 85, 5, 9, 7, 45, 44, 123, 56, 23, 13, 23, 17}; + + j = 0; + for (i = 0; i < 256; i++) { + S[i] = (u8)i; + j &= 0x0f; + K[i] = key[j]; + j++; + } + + j = 0; + for (i = 0; i < 256; i++) { + j = (j + S[i] + K[i]) % 256; + temp = S[i]; + S[i] = S[j]; + S[j] = temp; + } + + i = 0; + j = 0; + for (x = 0; x < len; x++) { + i = (i + 1) % 256; + j = (j + S[i]) % 256; + temp = S[i]; + S[i] = S[j]; + S[j] = temp; + t = (S[i] + (S[j] % 256)) % 256; + buf[x] = buf[x] ^ S[t]; + } +} + +void rk_idb_wait_dev_ready(struct rk_idb *plat) +{ + void __iomem *regs = plat->regs; + u32 reg; + + readl_poll_sleep_timeout(regs + NFC_FMCTL, + reg, + reg & FMCTL_RDY, + 1, + NFC_DEF_TIMEOUT); +} + +int rk_idb_wait_pio_xfer_done(struct rk_idb *plat) +{ + void __iomem *regs = plat->regs; + u32 reg; + + return readl_poll_sleep_timeout(regs + plat->cfg->flctl_off, + reg, + reg & FLCTL_XFER_READY, + 1, + NFC_DEF_TIMEOUT); +} + +int rk_idb_hw_ecc_setup(struct rk_idb *plat, u32 strength) +{ + void __iomem *regs = plat->regs; + u32 reg, i; + + for (i = 0; i < NFC_ECC_MAX_MODES; i++) { + if (strength == plat->cfg->ecc_strengths[i]) { + reg = plat->cfg->ecc_cfgs[i]; + break; + } + } + + if (i >= NFC_ECC_MAX_MODES) + return -EINVAL; + + writel(reg, regs + plat->cfg->bchctl_off); + + return 0; +} + +void rk_idb_select_chip(struct rk_idb *plat, int chipnr) +{ + void __iomem *regs = plat->regs; + u32 reg; + + if (chipnr < 0) { + plat->selected_bank = -1; + } else { + plat->selected_bank = chipnr; + plat->bank_offset = NFC_BANK + plat->selected_bank * NFC_BANK_STEP; + } + + reg = readl(regs + NFC_FMCTL); + reg &= ~FMCTRL_CE_SEL_M; + if (plat->selected_bank != -1) + reg |= 1 << plat->selected_bank; + writel(reg, regs + NFC_FMCTL); +} + +void rk_idb_pio_xfer_start(struct rk_idb *plat, u8 dir, u8 st_buf) +{ + void __iomem *regs = plat->regs; + u32 reg; + + if (plat->cfg->type == NFC_V6 || plat->cfg->type == NFC_V8) { + reg = readl(regs + plat->cfg->bchctl_off); + reg = (reg & (~(BCHCTL_BANK_M))) | + (plat->selected_bank << BCHCTL_BANK); + writel(reg, regs + plat->cfg->bchctl_off); + } + + reg = (dir << FLCTL_WR) | (st_buf << FLCTL_ST_BUF_S) | + FLCTL_XFER_EN | FLCTL_XFER_COUNT | + FLCTL_ACORRECT; + writel(reg, regs + plat->cfg->flctl_off); + + reg |= FLCTL_XFER_ST; + writel(reg, regs + plat->cfg->flctl_off); +} + +void rk_idb_init(struct rk_idb *plat) +{ + void __iomem *regs = plat->regs; + + writel(FMCTL_WP, regs + NFC_FMCTL); + /* Config default timing 40ns at 150 Mhz NFC clock. */ + writel(0x1081, regs + NFC_FMWAIT); + writel(0, regs + plat->cfg->randmz_off); + writel(0, regs + plat->cfg->dma_cfg_off); + writeb(NAND_CMD_RESET, regs + NFC_BANK + BANK_CMD); + rk_idb_wait_dev_ready(plat); +} + +void rk_idb_read_id(struct rk_idb *plat, u8 *id, int len) +{ + void __iomem *regs = plat->regs; + void __iomem *bank_base = regs + plat->bank_offset; + + writeb(NAND_CMD_READID, bank_base + BANK_CMD); + writeb(0x0, bank_base + BANK_ADDR); + udelay(1); + + debug("FLASH ID :"); + + for (int i = 0; i < len; i++) { + id[i] = readb(bank_base); + debug(" %x", id[i]); + } + + debug("\n"); +} + +void rk_idb_erase_op(struct rk_idb *plat, int page) +{ + void __iomem *regs = plat->regs; + void __iomem *bank_base = regs + plat->bank_offset; + + writeb(NAND_CMD_ERASE1, bank_base + BANK_CMD); + writeb(page, bank_base + BANK_ADDR); + writeb(page >> 8, bank_base + BANK_ADDR); + writeb(page >> 16, bank_base + BANK_ADDR); + writeb(NAND_CMD_ERASE2, bank_base + BANK_CMD); +} + +void rk_idb_read_page_op(struct rk_idb *plat, int page, int col) +{ + void __iomem *regs = plat->regs; + void __iomem *bank_base = regs + plat->bank_offset; + + writeb(NAND_CMD_READ0, bank_base + BANK_CMD); + writeb(col, bank_base + BANK_ADDR); + writeb(col >> 8, bank_base + BANK_ADDR); + writeb(page, bank_base + BANK_ADDR); + writeb(page >> 8, bank_base + BANK_ADDR); + writeb(page >> 16, bank_base + BANK_ADDR); + writeb(NAND_CMD_READSTART, bank_base + BANK_CMD); +} + +void rk_idb_write_page_op_begin(struct rk_idb *plat, int page, int col) +{ + void __iomem *regs = plat->regs; + void __iomem *bank_base = regs + plat->bank_offset; + + writeb(NAND_CMD_SEQIN, bank_base + BANK_CMD); + writeb(col, bank_base + BANK_ADDR); + writeb(col >> 8, bank_base + BANK_ADDR); + writeb(page, bank_base + BANK_ADDR); + writeb(page >> 8, bank_base + BANK_ADDR); + writeb(page >> 16, bank_base + BANK_ADDR); +} + +void rk_idb_write_page_op_end(struct rk_idb *plat) +{ + void __iomem *regs = plat->regs; + void __iomem *bank_base = regs + plat->bank_offset; + + writeb(NAND_CMD_PAGEPROG, bank_base + BANK_CMD); +} + +int rk_idb_read_page(struct rk_idb *plat, unsigned int page, u8 *buf, u8 *spare, u8 steps) +{ + void __iomem *regs = plat->regs; + void __iomem *sram_base = regs + NFC_SRAM0; + unsigned int max_bitflips = 0; + int bch_st; + int ret; + + rk_idb_read_page_op(plat, page, 0); + rk_idb_wait_dev_ready(plat); + rk_idb_pio_xfer_start(plat, NFC_READ, 0); + + for (int step = 0; step < steps / 2; step++) { + u8 *data = buf + step * DATA_STEP; + u8 *oob = spare + step * OOB_STEP; + + ret = rk_idb_wait_pio_xfer_done(plat); + if (ret) { + debug("read timeout\n"); + max_bitflips = -1; + break; + } + + bch_st = readl(regs + plat->cfg->bch_st_off); + + if (bch_st & BIT(plat->cfg->ecc0.err_flag_bit)) { + max_bitflips = -1; + break; + } else { + ret = ECC_ERR_CNT(bch_st, plat->cfg->ecc0); + max_bitflips = max_t(unsigned int, max_bitflips, ret); + } + + if ((step + 1) < steps / 2) + rk_idb_pio_xfer_start(plat, NFC_READ, (step + 1) & 0x1); + + memcpy_fromio(data, sram_base + NFC_SRAM_SIZE * (step & 0x1), DATA_STEP); + + if (step & 1) + memcpy_fromio(oob, regs + plat->cfg->oob1_off, OOB_STEP); + else + memcpy_fromio(oob, regs + plat->cfg->oob0_off, OOB_STEP); + } + + u32 *p_spare = (u32 *)spare; + + debug("read_page page_addr: %d spare[0]:%d\n", page, *p_spare); + + return max_bitflips; +} + +int rk_idb_write_page(struct rk_idb *plat, unsigned int page, u8 *buf, u8 *spare, u8 steps) +{ + void __iomem *regs = plat->regs; + void __iomem *sram_base = regs + NFC_SRAM0; + int ret = 0; + + u32 *p_spare = (u32 *)spare; + + debug("write_page page_addr: %d spare[0]:%d\n", page, *p_spare); + + rk_idb_write_page_op_begin(plat, page, 0); + + memcpy_toio(sram_base, buf, DATA_STEP); + memcpy_toio(regs + plat->cfg->oob0_off, spare, OOB_STEP); + + for (int step = 1; step <= steps / 2; step++) { + rk_idb_pio_xfer_start(plat, NFC_WRITE, (step - 1) & 0x1); + + u8 *data = buf + step * DATA_STEP; + u8 *oob = spare + step * OOB_STEP; + + if (step < steps / 2) { + memcpy_toio(sram_base + NFC_SRAM_SIZE * (step & 1), data, DATA_STEP); + + if (step & 1) + memcpy_fromio(regs + plat->cfg->oob1_off, oob, OOB_STEP); + else + memcpy_fromio(regs + plat->cfg->oob0_off, oob, OOB_STEP); + } + + ret = rk_idb_wait_pio_xfer_done(plat); + if (ret) { + debug("write timeout\n"); + ret = -1; + break; + } + } + + rk_idb_write_page_op_end(plat); + rk_idb_wait_dev_ready(plat); + + return ret; +} + +void rk_idb_scan_block(struct rk_idb *plat, u32 *data, u32 *spare) +{ + u32 blk; + u32 bch_counter; + int status; + + plat->blk_counter = 0; + + for (blk = 0; blk < plat->boot_blks; blk++) { + for (bch_counter = 0; bch_counter < NFC_ECC_MAX_MODES; bch_counter++) { + rk_idb_hw_ecc_setup(plat, plat->cfg->ecc_strengths[bch_counter]); + + status = rk_idb_read_page(plat, blk * plat->pages_per_blk, + (u8 *)data, (u8 *)spare, 4); + if (status != -1 && *data == RK_MAGIC) { + u32 boot_size; + + rk_idb_rc4((char *)data, 512); + + struct sector0 *sec0 = (struct sector0 *)data; + + if ((sec0->flash_boot_size - + sec0->flash_data_size) != 1024) { + boot_size = sec0->flash_boot_size - + sec0->flash_data_size; + } else { + boot_size = 0; + } + + int sectors = sec0->boot_code1_offset + + sec0->flash_data_size + + boot_size; + + plat->idblock[plat->blk_counter].blk = blk; + plat->idblock[plat->blk_counter].ecc = + plat->cfg->ecc_strengths[bch_counter]; + plat->idblock[plat->blk_counter].sectors = sectors; + + debug("\nblk : %d\n", plat->idblock[plat->blk_counter].blk); + debug("ecc : %d\n", plat->idblock[plat->blk_counter].ecc); + debug("sectors : %d\n", plat->idblock[plat->blk_counter].sectors); + + plat->blk_counter += 1; + + if (plat->blk_counter >= ARRAY_SIZE(plat->idblock)) + return; + break; + } + } + } +} + +void rk_idb_read_block(struct rk_idb *plat, u32 idb, u32 sectors, u32 *data, u32 *spare) +{ + int page = plat->idblock[idb].blk * plat->pages_per_blk; + int j; + + rk_idb_hw_ecc_setup(plat, plat->idblock[idb].ecc); + + for (j = 0; j < sectors / 4; j++) { + rk_idb_read_page(plat, page + plat->page_table[j], + (u8 *)data + j * 512 * 4, (u8 *)spare, 4); + } +} + +void rk_idb_write_block(struct rk_idb *plat, u32 idb, u32 sectors, u32 *data, u32 *spare) +{ + int page = plat->idblock[idb].blk * plat->pages_per_blk; + int j; + + plat->idblock[idb].sectors = sectors; + + rk_idb_hw_ecc_setup(plat, plat->idblock[idb].ecc); + rk_idb_erase_op(plat, page); + rk_idb_wait_dev_ready(plat); + + for (j = 0; j < sectors / 4; j++) { + spare[0] = (plat->page_table[j + 1] - 1) * 4; + spare[1] = 0xFFFFFFFF; + rk_idb_write_page(plat, page + plat->page_table[j], + (u8 *)data + j * 512 * 4, (u8 *)spare, 4); + } + + for (j = 0; j < sectors / 4; j++) { + rk_idb_read_page(plat, page + plat->page_table[j], + (u8 *)plat->check + j * 512 * 4, (u8 *)spare, 4); + } + + for (j = 0; j < (sectors * 512); j++) { + int w = *((u8 *)data + j); + int r = *((u8 *)plat->check + j); + + if (r != w) { + debug("write and check error:%d r=%x w=%x\n", j, r, w); + + memset((u8 *)plat->check, 0, 4 * 512); + spare[0] = 0xFFFFFFFF; + spare[1] = 0xFFFFFFFF; + rk_idb_write_page(plat, page, (u8 *)plat->check, (u8 *)spare, 4); + + plat->idblock[idb].sectors = 0; + break; + } + } +} + +void rk_idb_block_align(struct rk_idb *plat, u32 pages_per_blk) +{ + plat->pages_per_blk = pages_per_blk; + if (pages_per_blk > 512) + plat->pages_per_blk = 1024; + else if (pages_per_blk > 256) + plat->pages_per_blk = 512; + else if (pages_per_blk > 128) + plat->pages_per_blk = 256; +} + +int rk_idb_init_plat(struct udevice *dev) +{ + struct rk_idb *plat = dev_get_plat(dev); + + plat->idb = malloc_cache_aligned(512 * 512); + + if (!plat->idb) { + debug("idb malloc failed\n"); + return -1; + } + + plat->check = malloc_cache_aligned(512 * 512); + + if (!plat->check) { + debug("check malloc failed\n"); + return -1; + } + + return 0; +} + +int rk_idb_probe(struct udevice *dev) +{ + struct rk_idb *plat = dev_get_plat(dev); + const char *node_name; + ofnode subnode; + u8 id[8]; + int ret; + int i; + + plat->cfg = (void *)dev_get_driver_data(dev); + + plat->regs = (void *)dev_read_addr(dev); + + ofnode_for_each_subnode(subnode, dev_ofnode(dev)) { + node_name = ofnode_get_name(subnode); + + if (ofnode_read_bool(subnode, "nand-is-boot-medium")) + break; + } + + if (!ofnode_valid(subnode)) + return -ENODEV; + + plat->boot_blks = ofnode_read_u32_default(subnode, "rockchip,boot-blks", + DEFAULT_BLKS); + plat->boot_ecc = ofnode_read_u32_default(subnode, "rockchip,boot-ecc-strength", + DEFAULT_STRENGTH); + + ret = clk_get_by_index(dev, 0, &plat->ahb_clk); + if (ret < 0) { + debug("no ahb clk\n"); + return -ENODEV; + } + + ret = clk_prepare_enable(&plat->ahb_clk); + if (ret) { + debug("failed to enable ahb clk\n"); + return -ENODEV; + } + + ret = clk_get_by_index(dev, 1, &plat->nfc_clk); + if (ret < 0) { + debug("no nfc clk\n"); + /* Some earlier models, such as rk3066, have no nfc clk. */ + } else { + ret = clk_prepare_enable(&plat->nfc_clk); + if (ret) { + debug("failed to enable nfc clk\n"); + clk_disable_unprepare(&plat->ahb_clk); + return -ENODEV; + } + } + + rk_idb_init(plat); + + rk_idb_select_chip(plat, 0); + + rk_idb_read_id(plat, id, 8); + + int size = ARRAY_SIZE(nand_para_tbl); + + for (i = 0; i < size; i++) { + plat->info = (struct nand_para_info *)&nand_para_tbl[i]; + if (plat->info->nand_id[0] == id[0] && + plat->info->nand_id[1] == id[1] && + plat->info->nand_id[2] == id[2] && + plat->info->nand_id[3] == id[3] && + plat->info->nand_id[4] == id[4] && + plat->info->nand_id[5] == id[5]) + break; + } + + if (i == size) { + debug("no nand_para_info found\n"); + return -ENODEV; + } + + rk_idb_block_align(plat, plat->info->page_per_blk); + + rk_idb_build_page_table(plat, plat->info->lsb_mode); + + ret = rk_idb_init_plat(dev); + if (ret) { + debug("rk_idb_init_plat failed\n"); + return -ENOENT; + } + + return 0; +} + +static struct nfc_cfg nfc_v6_cfg = { + .type = NFC_V6, + .ecc_strengths = {60, 40, 24, 16}, + .ecc_cfgs = { + 0x00040011, 0x00040001, 0x00000011, 0x00000001, + }, + .flctl_off = 0x08, + .bchctl_off = 0x0C, + .dma_cfg_off = 0x10, + .dma_data_buf_off = 0x14, + .dma_oob_buf_off = 0x18, + .dma_st_off = 0x1C, + .bch_st_off = 0x20, + .randmz_off = 0x150, + .int_en_off = 0x16C, + .int_clr_off = 0x170, + .int_st_off = 0x174, + .oob0_off = 0x200, + .oob1_off = 0x230, + .ecc0 = { + .err_flag_bit = 2, + .low = 3, + .low_mask = 0x1F, + .low_bn = 5, + .high = 27, + .high_mask = 0x1, + }, + .ecc1 = { + .err_flag_bit = 15, + .low = 16, + .low_mask = 0x1F, + .low_bn = 5, + .high = 29, + .high_mask = 0x1, + }, +}; + +static struct nfc_cfg nfc_v8_cfg = { + .type = NFC_V8, + .ecc_strengths = {16, 16, 16, 16}, + .ecc_cfgs = { + 0x00000001, 0x00000001, 0x00000001, 0x00000001, + }, + .flctl_off = 0x08, + .bchctl_off = 0x0C, + .dma_cfg_off = 0x10, + .dma_data_buf_off = 0x14, + .dma_oob_buf_off = 0x18, + .dma_st_off = 0x1C, + .bch_st_off = 0x20, + .randmz_off = 0x150, + .int_en_off = 0x16C, + .int_clr_off = 0x170, + .int_st_off = 0x174, + .oob0_off = 0x200, + .oob1_off = 0x230, + .ecc0 = { + .err_flag_bit = 2, + .low = 3, + .low_mask = 0x1F, + .low_bn = 5, + .high = 27, + .high_mask = 0x1, + }, + .ecc1 = { + .err_flag_bit = 15, + .low = 16, + .low_mask = 0x1F, + .low_bn = 5, + .high = 29, + .high_mask = 0x1, + }, +}; + +static struct nfc_cfg nfc_v9_cfg = { + .type = NFC_V9, + .ecc_strengths = {70, 60, 40, 16}, + .ecc_cfgs = { + 0x00000001, 0x06000001, 0x04000001, 0x02000001, + }, + .flctl_off = 0x10, + .bchctl_off = 0x20, + .dma_cfg_off = 0x30, + .dma_data_buf_off = 0x34, + .dma_oob_buf_off = 0x38, + .dma_st_off = 0x3C, + .bch_st_off = 0x150, + .randmz_off = 0x208, + .int_en_off = 0x120, + .int_clr_off = 0x124, + .int_st_off = 0x128, + .oob0_off = 0x200, + .oob1_off = 0x204, + .ecc0 = { + .err_flag_bit = 2, + .low = 3, + .low_mask = 0x7F, + .low_bn = 7, + .high = 0, + .high_mask = 0x0, + }, + .ecc1 = { + .err_flag_bit = 18, + .low = 19, + .low_mask = 0x7F, + .low_bn = 7, + .high = 0, + .high_mask = 0x0, + }, +}; + +static const struct udevice_id rk_idb_ids[] = { + { + .compatible = "rockchip,px30-nfc", + .data = (unsigned long)&nfc_v9_cfg + }, + { + .compatible = "rockchip,rk2928-nfc", + .data = (unsigned long)&nfc_v6_cfg + }, + { + .compatible = "rockchip,rv1108-nfc", + .data = (unsigned long)&nfc_v8_cfg + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(rockchip_idb) = { + .name = "rockchip_idb", + .id = UCLASS_RK_IDB, + .of_match = rk_idb_ids, + .probe = rk_idb_probe, + .plat_auto = sizeof(struct rk_idb), +}; -- 2.20.1

1 0

[PATCH v2 01/11] rockchip: idb: prepare IDB block device
by Johan Jonker 09 Jul '22

09 Jul '22

Prepare for the IDB block device by adding some constants and function extentions. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- drivers/block/blk-uclass.c | 2 ++ include/blk.h | 1 + include/dm/uclass-id.h | 1 + include/efi_loader.h | 4 ++++ lib/efi_loader/efi_device_path.c | 30 ++++++++++++++++++++++++++++++ 5 files changed, 38 insertions(+) diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index 21c5209b..0b5f219d 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -32,6 +32,7 @@ static const char *if_typename_str[IF_TYPE_COUNT] = { [IF_TYPE_EFI_LOADER] = "efiloader", [IF_TYPE_VIRTIO] = "virtio", [IF_TYPE_PVBLOCK] = "pvblock", + [IF_TYPE_RK_IDB] = "idb", }; static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = { @@ -49,6 +50,7 @@ static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = { [IF_TYPE_EFI_LOADER] = UCLASS_EFI_LOADER, [IF_TYPE_VIRTIO] = UCLASS_VIRTIO, [IF_TYPE_PVBLOCK] = UCLASS_PVBLOCK, + [IF_TYPE_RK_IDB] = UCLASS_RK_IDB, }; static enum if_type if_typename_to_iftype(const char *if_typename) diff --git a/include/blk.h b/include/blk.h index 9503369d..a73cc577 100644 --- a/include/blk.h +++ b/include/blk.h @@ -38,6 +38,7 @@ enum if_type { IF_TYPE_PVBLOCK, IF_TYPE_VIRTIO, IF_TYPE_EFI_MEDIA, + IF_TYPE_RK_IDB, IF_TYPE_COUNT, /* Number of interface types */ }; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 3ba69ad9..38a227f0 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -104,6 +104,7 @@ enum uclass_id { UCLASS_REGULATOR, /* Regulator device */ UCLASS_REMOTEPROC, /* Remote Processor device */ UCLASS_RESET, /* Reset controller device */ + UCLASS_RK_IDB, /* Rockchip IDB device */ UCLASS_RNG, /* Random Number Generator */ UCLASS_RTC, /* Real time clock device */ UCLASS_SCMI_AGENT, /* Interface with an SCMI server */ diff --git a/include/efi_loader.h b/include/efi_loader.h index c1e00eba..44d42603 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -141,6 +141,10 @@ static inline efi_status_t efi_launch_capsules(void) #define U_BOOT_VIRTIO_DEV_GUID \ EFI_GUID(0x63293792, 0xadf5, 0x9325, \ 0xb9, 0x9f, 0x4e, 0x0e, 0x45, 0x5c, 0x1b, 0x1e) +/* GUID used as root for Rockchip IDB devices */ +#define U_BOOT_IDB_DEV_GUID \ + EFI_GUID(0xadc021df, 0x5f24, 0x464f, \ + 0x9a, 0x88, 0xdb, 0xee, 0x3f, 0x1d, 0x14, 0x0f) /* Use internal device tree when starting UEFI application */ #define EFI_FDT_USE_INTERNAL NULL diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index 171661b8..b7535373 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -28,6 +28,9 @@ const efi_guid_t efi_guid_host_dev = U_BOOT_HOST_DEV_GUID; #ifdef CONFIG_VIRTIO_BLK const efi_guid_t efi_guid_virtio_dev = U_BOOT_VIRTIO_DEV_GUID; #endif +#if CONFIG_IS_ENABLED(ROCKCHIP_IDB) +const efi_guid_t efi_guid_idb_dev = U_BOOT_IDB_DEV_GUID; +#endif /* template END node: */ static const struct efi_device_path END = { @@ -574,6 +577,16 @@ __maybe_unused static unsigned int dp_size(struct udevice *dev) */ return dp_size(dev->parent) + sizeof(struct efi_device_path_vendor) + 1; +#endif +#if CONFIG_IS_ENABLED(ROCKCHIP_IDB) + case UCLASS_RK_IDB: + /* + * Rockchip IDB device will be represented + * as vendor device with extra one byte for + * device number + */ + return dp_size(dev->parent) + + sizeof(struct efi_device_path_vendor) + 1; #endif default: return dp_size(dev->parent); @@ -667,6 +680,23 @@ __maybe_unused static void *dp_fill(void *buf, struct udevice *dev) return &dp->vendor_data[1]; } #endif +#if CONFIG_IS_ENABLED(ROCKCHIP_IDB) + case UCLASS_RK_IDB: { + struct efi_device_path_vendor *dp; + struct blk_desc *desc = dev_get_uclass_plat(dev); + + dp_fill(buf, dev->parent); + dp = buf; + ++dp; + dp->dp.type = DEVICE_PATH_TYPE_HARDWARE_DEVICE; + dp->dp.sub_type = DEVICE_PATH_SUB_TYPE_VENDOR; + dp->dp.length = sizeof(*dp) + 1; + memcpy(&dp->guid, &efi_guid_idb_dev, + sizeof(efi_guid_t)); + dp->vendor_data[0] = desc->devnum; + return &dp->vendor_data[1]; + } +#endif #ifdef CONFIG_IDE case UCLASS_IDE: { struct efi_device_path_atapi *dp = -- 2.20.1

1 0

[PATCH 1/6] Convert CONFIG_SYS_CACHE_STASHING to Kconfig
by Tom Rini 09 Jul '22

09 Jul '22

This converts the following to Kconfig: CONFIG_SYS_CACHE_STASHING Signed-off-by: Tom Rini <trini(a)konsulko.com> --- arch/powerpc/cpu/mpc85xx/Kconfig | 3 +++ configs/P2041RDB_NAND_defconfig | 1 + configs/P2041RDB_SDCARD_defconfig | 1 + configs/P2041RDB_SPIFLASH_defconfig | 1 + configs/P2041RDB_defconfig | 1 + configs/P3041DS_NAND_defconfig | 1 + configs/P3041DS_SDCARD_defconfig | 1 + configs/P3041DS_SPIFLASH_defconfig | 1 + configs/P3041DS_defconfig | 1 + configs/P4080DS_SDCARD_defconfig | 1 + configs/P4080DS_SPIFLASH_defconfig | 1 + configs/P4080DS_defconfig | 1 + configs/P5040DS_NAND_defconfig | 1 + configs/P5040DS_SDCARD_defconfig | 1 + configs/P5040DS_SPIFLASH_defconfig | 1 + configs/P5040DS_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 1 + configs/T1024RDB_SDCARD_defconfig | 1 + configs/T1024RDB_SPIFLASH_defconfig | 1 + configs/T1024RDB_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 1 + configs/T1042D4RDB_SDCARD_defconfig | 1 + configs/T1042D4RDB_SPIFLASH_defconfig | 1 + configs/T1042D4RDB_defconfig | 1 + configs/T2080QDS_NAND_defconfig | 1 + configs/T2080QDS_SDCARD_defconfig | 1 + configs/T2080QDS_SECURE_BOOT_defconfig | 1 + configs/T2080QDS_SPIFLASH_defconfig | 1 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/T2080QDS_defconfig | 1 + configs/T2080RDB_NAND_defconfig | 1 + configs/T2080RDB_SDCARD_defconfig | 1 + configs/T2080RDB_SPIFLASH_defconfig | 1 + configs/T2080RDB_defconfig | 1 + configs/T2080RDB_revD_NAND_defconfig | 1 + configs/T2080RDB_revD_SDCARD_defconfig | 1 + configs/T2080RDB_revD_SPIFLASH_defconfig | 1 + configs/T2080RDB_revD_defconfig | 1 + configs/T4240RDB_SDCARD_defconfig | 1 + configs/T4240RDB_defconfig | 1 + configs/kmcent2_defconfig | 1 + include/configs/P2041RDB.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/corenet_ds.h | 1 - include/configs/kmcent2.h | 1 - scripts/config_whitelist.txt | 1 - 50 files changed, 43 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 915e28e11088..b6881bf1ff39 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1230,6 +1230,9 @@ config SYS_CPC_REINIT_F config SYS_FSL_CPC bool "Corenet Platform Cache support" +config SYS_CACHE_STASHING + bool "Enable cache stashing" + config SYS_MPC85XX_NO_RESETVEC bool "Discard resetvec section and move bootpg section up" depends on MPC85xx diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 4c453a7cd943..30bf78be1e6e 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index b5f920b013e4..d5ad60981a2a 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index ecf63e59c6b3..97b01b498bf1 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index e609dfcbf216..c1eb08053299 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index 59fdc33ad47d..1df522a7449a 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index 17aa980518df..2380cfc7710c 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 2be600a58478..8a2464df91dd 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index f22719558fef..0abf6e1631da 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 2aba2228947a..66769e03c77d 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index 9bfb0a88f11b..8b5b81448a5d 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index 1d5f00d1c8b4..a0b12d049ef3 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 741adc516229..f48b0f92f72d 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index c10c94849e08..bf7287417e96 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 111ca1d4877e..c3a5f630a974 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index fd94afa762f6..9dac9e94c64b 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index a2648c4e526d..bffe4b332d6d 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -15,6 +15,7 @@ CONFIG_TARGET_T1024RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 5cf089d99009..e2ed674fc029 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -16,6 +16,7 @@ CONFIG_TARGET_T1024RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index c7b2def55345..8332f83f48ef 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -18,6 +18,7 @@ CONFIG_TARGET_T1024RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 9f1599fb6339..da28ef143f84 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 695d752dd5e0..e561277b35cb 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -14,6 +14,7 @@ CONFIG_TARGET_T1042D4RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 7e925643a376..5eec81619d27 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -15,6 +15,7 @@ CONFIG_TARGET_T1042D4RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index bfae94210dab..cdd99921cd25 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_T1042D4RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 3063157a7f66..1f3d6f6985fd 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 8392299c9d4b..324b325e23bb 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -14,6 +14,7 @@ CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index d043c8f793d9..140e1b599ceb 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -15,6 +15,7 @@ CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 2fc4e16cfe24..a18ea5651665 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -8,6 +8,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_NXP_ESBC=y CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000 CONFIG_PCIE1=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index daaccc62f3b9..e4c947aaf13c 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 2228c64d10f1..16563ea8afce 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -9,6 +9,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SRIO_PCIE_BOOT_SLAVE=y CONFIG_PCIE1=y CONFIG_PCIE2=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index fbfbab84a185..e7775dac0b80 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index c6a2b6214138..a3b087dab28a 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -14,6 +14,7 @@ CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index e161f9ec623f..5131b1537453 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -15,6 +15,7 @@ CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index b5ede3003959..8cd77fd60592 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 8df5b3db2904..6c6835eee316 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index 1035ae8980e4..003378d2c819 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -14,6 +14,7 @@ CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 1de3526028b1..7157fd88cd17 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -15,6 +15,7 @@ CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y CONFIG_PCIE1=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index af8888982bfc..b0a580b93e33 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y CONFIG_PCIE1=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index e4eaa75d3024..e599c4e640e8 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_T2080RDB_REV_D=y CONFIG_PCIE1=y CONFIG_PCIE2=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 583b2edc4c04..7dfe6f4b4891 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -15,6 +15,7 @@ CONFIG_TARGET_T4240RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index c3216474c312..5b7849ea6ba8 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index ee900f5d9cd3..a0c92441cea0 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -13,6 +13,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_FSL_CPC=y +CONFIG_SYS_CACHE_STASHING=y # CONFIG_DEEP_SLEEP is not set CONFIG_PCIE1=y CONFIG_KM_DEF_NETDEV="eth2" diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 64f4c244fa21..2d552835b776 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -45,7 +45,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 3df6ec6246a5..c90ffe048c6f 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -95,7 +95,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 8503fd108793..56486cf5c934 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -63,7 +63,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index e981f621c379..710254a8fb47 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -68,7 +68,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 48cdc75a08df..8ade2e3c8292 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -63,7 +63,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index c31b0b684156..653483cc99f0 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -44,7 +44,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f20f4e35e957..4eeca47c2534 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -38,7 +38,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 3f22ddc6dd8d..b389229b7546 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -146,7 +146,6 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E /* POST memory regions test */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 13ad0b09fc63..7cf3d83104e6 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -497,7 +497,6 @@ CONFIG_SYS_CACHE_ACR1 CONFIG_SYS_CACHE_ACR2 CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR -CONFIG_SYS_CACHE_STASHING CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_HIGH -- 2.25.1

2 7

[PATCH 0/4] Migrate some wiki pages to sphinx
by Tom Rini 09 Jul '22

09 Jul '22

Hey all, As you might have seen, the DENX wiki has undergone some updates in the last few months. As of now, most pages have been restored and are up to date. But it's also true that the wiki long predates our sphinx documentation and readthedocs site (which I am very happy the work has been put in on making and improving). So to that end, I'm trying to move everything that's on the wiki over to sphinx so that it will be easier to access and keep up to date. To that end, this small series includes 3 pages being moved. I don't know what to do about ReleaseCycle and the statics pages long term. I have a few ideas, but they're tricker so not what I want to tackle first. I'm thinking the next page to tackle is https://www.denx.de/wiki/U-Boot/Patches which might well end up being more than one page once moved. And there's still some outdated information in what I'm posting here, I'm not sure if a follow-up updating it is needed now, or just when someone has a chance. -- Tom

5 22

rk3399 after reboot mmc1 is inaceessible
by Michal Suchánek 09 Jul '22

09 Jul '22

Hello, after rebooting rk3399 Pinebook Pro mmc1 is no longer accessible from u-boot, and video is not working, only cold boot works. This is not a problem anymore when Linux is loaded from another device. Any idea how to debug this? Thanks Michal U-Boot TPL 2022.07-rc5 (May 16 2022 - 12:00:00) Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride lpddr4_set_rate: change freq to 400000000 mhz 0, 1 lpddr4_set_rate: change freq to 800000000 mhz 1, 0 Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2022.07-rc5 (May 16 2022 - 12:00:00 +0000) Trying to boot from MMC1 NOTICE: BL31: v2.6(debug): NOTICE: BL31: Built : 14:50:40, Jul 1 2022 INFO: GICv3 with legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: Maximum SPI INTID supported: 287 INFO: plat_rockchip_pmu_init(1624): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied WARNING: BL31: cortex_a53: CPU workaround for 1530924 was missing! INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9 U-Boot 2022.07-rc5 (May 16 2022 - 00:00:00 +0000) SoC: Rockchip rk3399 Reset cause: POR Model: Pine64 Pinebook Pro DRAM: 3.9 GiB PMIC: RK808 Core: 317 devices, 34 uclasses, devicetree: separate MMC: mmc@fe310000: 3, mmc@fe320000: 1, mmc@fe330000: 0 Loading Environment from SPIFlash... SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB *** Warning - bad CRC, using default environment In: serial Out: vidconsole Err: vidconsole Model: Pine64 Pinebook Pro Net: No ethernet found. starting USB... Bus usb@fe380000: ehci_generic usb@fe380000: Failed to get clocks (ret=-19) Port not available. Bus usb@fe3a0000: USB OHCI 1.0 Bus usb@fe3c0000: ehci_generic usb@fe3c0000: Failed to get clocks (ret=-19) Port not available. Bus usb@fe3e0000: USB OHCI 1.0 Bus usb@fe800000: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 Bus usb@fe900000: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 scanning bus usb@fe3a0000 for devices... 2 USB Device(s) found scanning bus usb@fe3e0000 for devices... 4 USB Device(s) found scanning bus usb@fe800000 for devices... 1 USB Device(s) found scanning bus usb@fe900000 for devices... 1 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc1 is current device ** Invalid partition 3 ** Couldn't find partition mmc 1:3 ** Invalid partition 4 ** Couldn't find partition mmc 1:4 Scanning mmc 1:1... BootOrder not defined EFI boot manager: Cannot load any image Found EFI removable media binary efi/boot/bootaa64.efi 857968 bytes read in 96 ms (8.5 MiB/s) Booting /efi\boot\bootaa64.efi U-Boot TPL 2022.07-rc5 (May 16 2022 - 12:00:00) Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride lpddr4_set_rate: change freq to 400000000 mhz 0, 1 lpddr4_set_rate: change freq to 800000000 mhz 1, 0 Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2022.07-rc5 (May 16 2022 - 12:00:00 +0000) Trying to boot from MMC1 NOTICE: BL31: v2.6(debug): NOTICE: BL31: Built : 14:50:40, Jul 1 2022 INFO: GICv3 with legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: Maximum SPI INTID supported: 287 INFO: plat_rockchip_pmu_init(1624): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied WARNING: BL31: cortex_a53: CPU workaround for 1530924 was missing! INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x200000 INFO: SPSR = 0x3c9 U-Boot 2022.07-rc5 (May 16 2022 - 00:00:00 +0000) SoC: Rockchip rk3399 Reset cause: RST Model: Pine64 Pinebook Pro DRAM: 3.9 GiB PMIC: RK808 Core: 317 devices, 34 uclasses, devicetree: separate MMC: mmc@fe310000: 3, mmc@fe320000: 1, mmc@fe330000: 0 Loading Environment from SPIFlash... SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB *** Warning - bad CRC, using default environment In: serial Out: vidconsole Err: vidconsole Model: Pine64 Pinebook Pro Net: No ethernet found. starting USB... Bus usb@fe380000: ehci_generic usb@fe380000: Failed to get clocks (ret=-19) Port not available. Bus usb@fe3a0000: USB OHCI 1.0 Bus usb@fe3c0000: ehci_generic usb@fe3c0000: Failed to get clocks (ret=-19) Port not available. Bus usb@fe3e0000: USB OHCI 1.0 Bus usb@fe800000: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 Bus usb@fe900000: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 scanning bus usb@fe3a0000 for devices... 2 USB Device(s) found scanning bus usb@fe3e0000 for devices... 4 USB Device(s) found scanning bus usb@fe800000 for devices... 1 USB Device(s) found scanning bus usb@fe900000 for devices... 1 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found Hit any key to stop autoboot: 0 *** ERROR: Can't read GPT Entries *** find_valid_gpt: *** ERROR: Invalid GPT *** *** ERROR: Can't read GPT header *** find_valid_gpt: *** ERROR: Invalid Backup GPT *** *** ERROR: Can't read GPT Entries *** find_valid_gpt: *** ERROR: Invalid GPT *** *** ERROR: Can't read GPT header *** find_valid_gpt: *** ERROR: Invalid Backup GPT *** *** ERROR: Can't read GPT Entries *** find_valid_gpt: *** ERROR: Invalid GPT *** *** ERROR: Can't read GPT header *** find_valid_gpt: *** ERROR: Invalid Backup GPT *** *** ERROR: Can't read GPT Entries *** find_valid_gpt: *** ERROR: Invalid GPT *** *** ERROR: Can't read GPT header *** find_valid_gpt: *** ERROR: Invalid Backup GPT *** *** ERROR: Can't read GPT Entries *** find_valid_gpt: *** ERROR: Invalid GPT *** *** ERROR: Can't read GPT header *** find_valid_gpt: *** ERROR: Invalid Backup GPT *** *** ERROR: Can't read GPT Entries *** find_valid_gpt: *** ERROR: Invalid GPT *** *** ERROR: Can't read GPT header *** find_valid_gpt: *** ERROR: Invalid Backup GPT *** *** ERROR: Can't read GPT Entries *** find_valid_gpt: *** ERROR: Invalid GPT *** *** ERROR: Can't read GPT header *** find_valid_gpt: *** ERROR: Invalid Backup GPT *** *** ERROR: Can't read GPT Entries *** find_valid_gpt: *** ERROR: Invalid GPT ***

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[PATCH v2] mtd: spi-nor-ids: add winbond w25q512nw family support
by Jae Hyun Yoo 09 Jul '22

09 Jul '22

Add Winbond w25q512nwq/n and w25q512nwm support. datasheet: https://www.winbond.com/resource-files/W25Q512NW%20RevB%2007192021.pdf Signed-off-by: Jae Hyun Yoo <quic_jaehyoo(a)quicinc.com> --- Changes in v2: * Changed name from w25q512nwiq and w25q512nwim to w25q512nwq and w25q512nwm respectively to make them sync with linux code. drivers/mtd/spi/spi-nor-ids.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 7050ddc39716..91a3f983a5fa 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -362,6 +362,16 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { + INFO("w25q512nwm", 0xef8020, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | -- 2.25.1

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[PATCH] board_init: Do not reserve MALLOC_F area on stack if non-zero MALLOC_F_ADDR
by Marek Vasut 09 Jul '22

09 Jul '22

In case the MALLOC_F_ADDR is set to non-zero value, the early malloc area is not going to be placed just below stack top, but elsewhere. Do not reserve MALLOC_F bytes in this case, as that wastes stack space and may even cause insufficient stack space in SPL. This functionality is particularly useful on i.MX8M, where the insufficient stack space can be triggered. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Thomas Chou <thomas(a)wytron.com.tw> Cc: Tom Rini <trini(a)konsulko.com> --- common/init/board_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/common/init/board_init.c b/common/init/board_init.c index eab5ee13953..6a550261778 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -78,8 +78,10 @@ __weak void board_init_f_init_stack_protection(void) ulong board_init_f_alloc_reserve(ulong top) { /* Reserve early malloc arena */ +#ifndef CONFIG_MALLOC_F_ADDR #if CONFIG_VAL(SYS_MALLOC_F_LEN) top -= CONFIG_VAL(SYS_MALLOC_F_LEN); +#endif #endif /* LAST : reserve GD (rounded up to a multiple of 16 bytes) */ top = rounddown(top-sizeof(struct global_data), 16); -- 2.35.1

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Please pull u-boot-dm/next
by Simon Glass 08 Jul '22

08 Jul '22

Hi Tom, This is for the -next branch. https://source.denx.de/u-boot/custodians/u-boot-dm/-/commit/e87da5704ffa6fc… The following changes since commit ea82ed8c2eaee0a0f7dee31016aaee4ce88e9ea7: Merge branch '2022-06-27-add-armv8-sha1-sha256-support' into next (2022-06-27 13:39:19 -0400) are available in the Git repository at: git://git.denx.de/u-boot-dm.git tags/dm-pull-28jun22 for you to fetch changes up to e87da5704ffa6fc782d93d137fa30a37a5df3566: armv8: u-boot-spl.lds: mark __image_copy_start as symbol (2022-06-28 03:09:52 +0100) ---------------------------------------------------------------- nman external-symbol improvements Driver model memory-usage reporting patman test-reporting improvements Add bloblist design goals ---------------------------------------------------------------- Alper Nebi Yasak (12): patman: test_util: Fix printing results for failed tests patman: test_util: Handle nonexistent tests while loading tests patman: test_util: Use unittest text runner to print test results patman: test_util: Customize unittest test results for more info patman: test_util: Print test stdout/stderr within test summaries spl: binman: Fix use of undeclared u_boot_any symbols spl: binman: Make TPL_BINMAN_SYMBOLS depend on TPL_FRAMEWORK spl: binman: Declare extern symbols for VPL as well spl: binman: Split binman symbols support from enabling binman spl: binman: Add config options for binman symbols in VPL spl: binman: Check at runtime if binman symbols were filled in spl: binman: Disable u_boot_any symbols for i.MX8M boards Heinrich Schuchardt (6): sandbox: add function os_printf() sandbox: show error if the device-tree cannot be loaded dm: fix formatting of uclass dump sandbox: raise SANDBOX_RAM_SIZE_MB default to 256 test: fix some pylint errors in test_bind.py sandbox: cast to pointer from integer of different size Peng Fan (1): armv8: u-boot-spl.lds: mark __image_copy_start as symbol Sean Anderson (4): sandbox: usb: Fix out-of-bounds read when fd=-1 dm: core: Provide fallbacks for ofnode_conf_read_... dm: core: Use device_foreach_child where possible patman: Fix defaults not propagating to subparsers Simon Glass (11): bloblist: Describe the design goals dtoc: Update fdt tests to use test_util dm: core: Rename dm_dump_all() dm: core: Sort dm subcommands dm: core: Fix addresses in the dm static command dm: core: Add documentation for the dm command dm: core: Switch the testbus driver to use a new struct dm: core: Support accessing core tags dm: core: Add a way to collect memory usage dm: core: Add a command to show driver model statistics dm: spl: Allow SPL to show memory usage arch/arm/cpu/armv8/u-boot-spl.lds | 2 +- arch/sandbox/Kconfig | 4 +- arch/sandbox/cpu/cpu.c | 8 +- arch/sandbox/cpu/os.c | 13 + cmd/dm.c | 72 ++-- common/spl/Kconfig | 23 +- common/spl/Kconfig.tpl | 27 +- common/spl/Kconfig.vpl | 25 ++ common/spl/spl.c | 25 +- common/spl/spl_ram.c | 2 +- doc/develop/bloblist.rst | 2 + doc/usage/cmd/dm.rst | 487 ++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + drivers/core/Kconfig | 21 ++ drivers/core/device-remove.c | 4 +- drivers/core/device.c | 86 ++++- drivers/core/devres.c | 2 +- drivers/core/dump.c | 83 ++++- drivers/core/root.c | 53 +++ drivers/core/tag.c | 29 ++ drivers/misc/qfw_sandbox.c | 2 +- drivers/misc/test_drv.c | 6 +- drivers/usb/emul/sandbox_flash.c | 5 +- include/binman_sym.h | 51 ++- include/bloblist.h | 62 +++- include/dm/device.h | 25 ++ include/dm/ofnode.h | 66 ++-- include/dm/root.h | 45 +++ include/dm/tag.h | 32 +- include/dm/test.h | 7 + include/dm/util.h | 11 +- include/os.h | 7 + include/spl.h | 2 + test/dm/core.c | 91 ++++++ test/py/tests/test_bind.py | 345 ++++++++++---------- tools/binman/elf.py | 12 +- tools/binman/elf_test.py | 12 +- tools/binman/ftest.py | 33 +- tools/binman/main.py | 8 +- tools/binman/test/021_image_pad.dts | 2 +- tools/binman/test/024_sorted.dts | 2 +- tools/binman/test/028_pack_4gb_outside.dts | 2 +- tools/binman/test/029_x86_rom.dts | 6 +- tools/binman/test/053_symbols.dts | 2 +- tools/binman/test/149_symbols_tpl.dts | 4 +- tools/binman/test/155_symbols_tpl_x86.dts | 4 +- tools/binman/test/187_symbols_sub.dts | 2 +- tools/binman/test/Makefile | 2 +- tools/binman/test/generated/autoconf.h | 3 + tools/binman/test/u_boot_binman_syms.c | 6 +- tools/binman/test/u_boot_binman_syms_size.c | 6 +- tools/buildman/main.py | 8 +- tools/concurrencytest/concurrencytest.py | 83 ++++- tools/dtoc/main.py | 9 +- tools/dtoc/test_dtoc.py | 6 +- tools/dtoc/test_fdt.py | 29 +- tools/patman/main.py | 8 +- tools/patman/settings.py | 7 +- tools/patman/test_util.py | 150 ++++++--- 59 files changed, 1723 insertions(+), 409 deletions(-) create mode 100644 doc/usage/cmd/dm.rst create mode 100644 tools/binman/test/generated/autoconf.h Regards, Simon

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[PATCH] requirements: Move to atomicwrites==1.4.1
by Tom Rini 08 Jul '22

08 Jul '22

As explained upstream: https://github.com/untitaker/python-atomicwrites/issues/61 there is no longer a 1.3.0 version but the API is unchanged. Move to 1.4.1. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- test/py/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/py/requirements.txt b/test/py/requirements.txt index 33c5c0bbc41b..2d0fcc965cf7 100644 --- a/test/py/requirements.txt +++ b/test/py/requirements.txt @@ -1,4 +1,4 @@ -atomicwrites==1.3.0 +atomicwrites==1.4.1 attrs==19.3.0 coverage==4.5.4 extras==1.0.0 -- 2.25.1

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[PATCH] imx8mq_phanbell: Remove custom CONFIG_SYS_MALLOC_F_LEN
by Fabio Estevam 08 Jul '22

08 Jul '22

From: Fabio Estevam <festevam(a)denx.de> Currently, the imx8mq_phanbell board fails to boot. Remove the custom CONFIG_SYS_MALLOC_F_LEN setting in favor of the generic one done via the main Kconfig. Since commit b598957206e5 ("Kconfig: Fix SYS_MALLOC_F_LEN for i.MX8MQ") the default SYS_MALLOC_F_LEN value for i.MX8MQ is 0x2000. With such default value, the board boots again. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- Hi Tom, Maybe you could pick this one directly for the 2022.07 release to fix the boot regression? Thanks configs/imx8mq_phanbell_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index 095e42e6ba18..1cf58937fe52 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SYS_MALLOC_LEN=0x600000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -- 2.25.1

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