June 2022 - U-Boot

[PATCH v10 00/13] fpga: zynqmp: Adding support of loading authenticated images
by Oleksandr Suvorov 18 Jun '22

18 Jun '22

This patchset introduces support for the authenticated and encrypted FPGA images on ZynqMP boards, besides that introducing common way to pass the compatible property to any fpga driver. It bases on the initial work by Jorge Ramirez-Ortiz <jorge(a)foundries.io> https://patchwork.ozlabs.org/project/uboot/patch/20211015091506.2602-1-jorg… https://patchwork.ozlabs.org/project/uboot/patch/20211005111324.19749-3-jor… Changes in v10: - move FPGA flags to macros; - initialize xilinx_desc structs directly, removing *_DESC macros; - initialize flags for mach-zynq; - fix mixed types of return value; - made the message about ignoring legacy compatibe option as debug - fix grammar; - Support DDR images only if FPGA_LOAD_SECURE enabled. - Support ENC images only if FPGA_LOAD_SECURE enabled. Changes in v9: - remove an alien commit from a patchset :) Changes in v8: - Michal Simek's suggestions addressed: -- introduce the compatible flags in xilinx_desc; -- pass a binary compatible flag instead of "compatible" property to an FPGA driver. - Optimize a zynqmp_load() function. Changes in v7: - apply Michal Simek's suggestions As I applied changes on Oleksandr's patches, I indicated it by specifying myself as co-author in the commits logs. I am not sure if that is the convention of marking it. Changes in v6: - add support for the encrypted bitfiles. Changes in v5: - replace ifdef with if() where it's possible. Changes in v4: - change interface to xilinx_desc->operations->open() callback. - fix a bug from previous version of the patchset in dereferencing of a parent fpga_desc structure. Changes in v3: - remove the patch which introduced CMD_SPL_FPGA_LOAD_SECURE. - fix mixing definitions/declarations. - replace strcmp() calls with more secure strncmp(). - document the "u-boot,zynqmp-fpga-ddrauth" compatible string. - fix code style by check-patch recommendations. Changes in v2: - add function fit_fpga_load() to simplify calls of fpga_load() from contexts without a compatible attribute. - move all ZynqMP-specific logic to drivers/fpga/zynqmppl.c - prepare for passing a "compatible" FDT property to any fpga driver. Adrian Fiergolski (1): fpga: zynqmp: support loading encrypted bitfiles Oleksandr Suvorov (12): fpga: add option for loading FPGA secure bitstreams fpga: xilinx: add missed identifier names fpga: xilinx: add bitstream flags to driver desc fpga: zynqmp: add str2flags call fpga: add fpga_compatible2flag fpga: xilinx: pass compatible flags to xilinx_load() fpga: pass compatible flags to fpga_load() spl: fit: pass real compatible flags to fpga_load() fpga: xilinx: pass compatible flags to load() callback fpga: zynqmp: optimize zynqmppl_load() code fpga: zynqmp: add bitstream compatible checking fpga: zynqmp: support loading authenticated images arch/arm/mach-zynq/cpu.c | 1 + board/xilinx/versal/board.c | 5 +- board/xilinx/zynqmp/zynqmp.c | 5 +- boot/Kconfig | 4 +- boot/image-board.c | 4 +- cmd/Kconfig | 3 +- cmd/fpga.c | 8 +-- common/spl/spl_fit.c | 16 +++-- doc/uImage.FIT/source_file_format.txt | 7 +- drivers/fpga/Kconfig | 14 ++++ drivers/fpga/fpga.c | 31 ++++++++- drivers/fpga/spartan2.c | 2 +- drivers/fpga/spartan3.c | 2 +- drivers/fpga/versalpl.c | 2 +- drivers/fpga/virtex2.c | 2 +- drivers/fpga/xilinx.c | 8 +-- drivers/fpga/zynqmppl.c | 96 ++++++++++++++++++++++----- drivers/fpga/zynqpl.c | 2 +- include/fpga.h | 4 +- include/versalpl.h | 3 - include/xilinx.h | 19 ++++-- include/zynqmppl.h | 9 ++- 22 files changed, 191 insertions(+), 56 deletions(-) -- 2.36.1

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[Rock Pi 4+] Mainline LPDDR4 RAM initialisation is not sufficient to boot successfully
by Lee Jones 17 Jun '22

17 Jun '22

Good afternoon, There appear to be a number of issues with the Rockchip rk3399 DDR RAM initialisation sequence in Mainline. Specifically, I'm seeing consistent failures on the Rock Pi 4+ during early boot. A typical failure looks something like this: U-Boot TPL 2022.07-rc3-00005-g1b04a961c6 (May 25 2022 - 11:09:19) Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB Channel 1: col error Cap error! 256B stride lpddr4_set_rate: change freq to 400000000 mhz 0, 1 lpddr4_set_rate: change freq to 800000000 mhz 1, 0 Trying to boot from BOOTROM Returning to boot ROM... Even when the system boots to a terminal, which happens very infrequently, the LPDDR4 RAM chip at Channel 1 can have conflicting discovery information printed during TPL. The following 3 lines were printed during successive reboots using the same SD card with no changes: # Boot 1: BW=32 Col=9 Bk=4 CS0 Row=16/15 CS=1 Die BW=16 Size=384MB # Boot 2: BW=32 Col=10 Bk=4 CS0 Row=16/15 CS=1 Die BW=16 Size=768MB # Boot 3: BW=32 Col=10 Bk=4 CS0 Row=15 CS=1 Die BW=16 Size=512MB The story changes when I build the idbloader.img image with Rockchip's TBL (?) binary blob [0]. With that built in, presumably in place of the upstream TBL, both RAM chips are successfully enumerated and boot succeeds with 100% success rate: tools/mkimage -n rk3399 -T rksd -d \ rk3399_ddr_933MHz_v1.25.bin:spl/u-boot-spl.bin idbloader.img Another thing that is very different between the 2 is the initial frequency the LPDDR4 chips are clocked at. Using the upstream TBL version, the default is 50Mhz, which seems very low. If using the Rockchip supplied binary blob file, this is increased to a respectable 416MHz: # Mainline Channel 0: LPDDR4, 50MHz # Rockchip TBL blob Channel 0: LPDDR4,416MHz One thing I did try was to load in the 400Mhz configuration settings from drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc as the default initial values, instead of the 50MHz default taken from arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi, but this failed in a number of ways: Setting clock: Freq: 400MHz (400000000) Calling SDRAM init: 2 Channels Starting SDRAM initialization... mr5:0 mr12:0 mr14:0 Training failed for rank 2, ch 0 (ret: -22) mr5:0 mr12:0 mr14:0 Training failed for rank 1, ch 0 (ret: -22) mr5:0 mr12:0 mr14:0 Training failed for rank 2, ch 1 (ret: -22) mr5:0 mr12:0 mr14:0 Training failed for rank 1, ch 1 (ret: -22) Rank for Channel 1 is 0x0 Rank for Channel 0 is 0x0 Rank for Channel 1 is 0x0 sdram_init: LPDDR4 - 400MHz failed! rk3399_dmc_init DRAM init failed -22 So my question is; does Rockchip, or anyone else for that matter, have any plans on updating Mainline U-Boot with the upgraded/working LPDDR4 initialisation sequence? As ever, any information / help would be gratefully received. NB: If I have missed any critical people out from this discussion, please feel free to loop as many of them in as you see fit. Kind regards, Lee [0] https://github.com/rockchip-linux/rkbin/blob/master/bin/rk33/rk3399_ddr_933… -- Lee Jones [李琼斯] Principal Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog

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[PATCH] tools: binman: install btool
by Peng Fan (OSS) 17 Jun '22

17 Jun '22

From: Peng Fan <peng.fan(a)nxp.com> btool is needed after install binman to system. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- Tom, Simon, Alper This is a bug fix, if possible, please pick it up. tools/binman/setup.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/binman/setup.py b/tools/binman/setup.py index 5ed94abdaf9..9a9206eb044 100644 --- a/tools/binman/setup.py +++ b/tools/binman/setup.py @@ -5,7 +5,7 @@ setup(name='binman', version='1.0', license='GPL-2.0+', scripts=['binman'], - packages=['binman', 'binman.etype'], + packages=['binman', 'binman.etype', 'binman.btool'], package_dir={'binman': ''}, package_data={'binman': ['README.rst', 'entries.rst']}, classifiers=['Environment :: Console', -- 2.36.0

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[PATCH] board: ti: am335x: eth_cpsw should depend on CONFIG_NET
by Corentin LABBE 17 Jun '22

17 Jun '22

The origin of this patch is the breaking of am335x-hs boot due to commit e41651fffda7 ("dm: Support parent devices with of-platdata") HS boards have less SRAM for SPL and so this commit increased memory usage beyond am335x limit. This commit added 10 driver binding pass and am335x boot only if one pass is done. SPL try to do more than one pass due to eth_cpsw failing. Since HS SPL does not need network (and NET is already disabled in config), the easiest fix is to "remove" eth_cpsw from SPL by testing if NET is enabled. Signed-off-by: Corentin LABBE <clabbe(a)baylibre.com> --- board/ti/am335x/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 7c0545892c..2cb5b1cb3f 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -902,7 +902,7 @@ int board_late_init(void) #endif /* CPSW plat */ -#if !CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(NET) && !CONFIG_IS_ENABLED(OF_CONTROL) struct cpsw_slave_data slave_data[] = { { .slave_reg_ofs = CPSW_SLAVE0_OFFSET, -- 2.25.1

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[PATCH v2] armv8: always use current exception level for TCR_ELx access
by Andre Przywara 17 Jun '22

17 Jun '22

Currently get_tcr() takes an "el" parameter, to select the proper version of the TCR_ELx system register. This is problematic in case of the Apple M1, since it runs with HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, and we get the wrong version. For U-Boot's purposes the only sensible choice here is the current exception level, and indeed most callers treat it like that, so let's remove that parameter and read the current EL inside the function. This allows us to check for the E2H bit, and pretend it's EL1 in this case. There are two callers which don't care about the EL, and they pass 0, which looks wrong, but is irrelevant in these two cases, since we don't use the return value there. So the change cannot affect those two. Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- Changelog v1 ... v2: - Give bit 34 a name, and also use that in start.S Mark, can you please test this? The A53s I have here for a quick test are igorant of this patch ... arch/arm/cpu/armv8/cache_v8.c | 28 +++++++++++++++++++++---- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 ++-- arch/arm/cpu/armv8/start.S | 2 +- arch/arm/include/asm/armv8/mmu.h | 4 +++- 4 files changed, 30 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 3de18c7675b..e4736e56436 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -39,8 +39,28 @@ DECLARE_GLOBAL_DATA_PTR; * off: FFF */ -u64 get_tcr(int el, u64 *pips, u64 *pva_bits) +static int get_effective_el(void) { + int el = current_el(); + + if (el == 2) { + u64 hcr_el2; + + /* + * If we are using the EL2&0 translation regime, the TCR_EL2 + * looks like the EL1 version, even though we are in EL2. + */ + __asm__ ("mrs %0, HCR_EL2\n" : "=r" (hcr_el2)); + if (hcr_el2 & BIT(HCR_EL2_E2H_BIT)) + return 1; + } + + return el; +} + +u64 get_tcr(u64 *pips, u64 *pva_bits) +{ + int el = get_effective_el(); u64 max_addr = 0; u64 ips, va_bits; u64 tcr; @@ -115,7 +135,7 @@ static u64 *find_pte(u64 addr, int level) debug("addr=%llx level=%d\n", addr, level); - get_tcr(0, NULL, &va_bits); + get_tcr(NULL, &va_bits); if (va_bits < 39) start_level = 1; @@ -343,7 +363,7 @@ __weak u64 get_page_table_size(void) u64 va_bits; int start_level = 0; - get_tcr(0, NULL, &va_bits); + get_tcr(NULL, &va_bits); if (va_bits < 39) start_level = 1; @@ -415,7 +435,7 @@ __weak void mmu_setup(void) setup_all_pgtables(); el = current_el(); - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL), MEMORY_ATTRIBUTES); /* enable the mmu */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 253008a9c13..c989a43cbeb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -454,7 +454,7 @@ static inline void early_mmu_setup(void) /* point TTBR to the new table */ set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - get_tcr(el, NULL, NULL) & + get_tcr(NULL, NULL) & ~(TCR_ORGN_MASK | TCR_IRGN_MASK), MEMORY_ATTRIBUTES); @@ -609,7 +609,7 @@ static inline void final_mmu_setup(void) invalidate_icache_all(); /* point TTBR to the new table */ - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL), MEMORY_ATTRIBUTES); set_sctlr(get_sctlr() | CR_M); diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index d328e8c08a1..28f0df13f0d 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -125,7 +125,7 @@ pie_fixup_done: msr cptr_el3, xzr /* Enable FP/SIMD */ b 0f 2: mrs x1, hcr_el2 - tbnz x1, #34, 1f /* HCR_EL2.E2H */ + tbnz x1, #HCR_EL2_E2H_BIT, 1f /* HCR_EL2.E2H */ orr x1, x1, #HCR_EL2_AMO_EL2 /* Route SErrors to EL2 */ msr hcr_el2, x1 set_vbar vbar_el2, x0 diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index c36b2cf5a58..9f58cedb650 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -103,6 +103,8 @@ #define TCR_EL2_RSVD (1U << 31 | 1 << 23) #define TCR_EL3_RSVD (1U << 31 | 1 << 23) +#define HCR_EL2_E2H_BIT 34 + #ifndef __ASSEMBLY__ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { @@ -134,7 +136,7 @@ struct mm_region { extern struct mm_region *mem_map; void setup_pgtables(void); -u64 get_tcr(int el, u64 *pips, u64 *pva_bits); +u64 get_tcr(u64 *pips, u64 *pva_bits); #endif #endif /* _ASM_ARMV8_MMU_H_ */ -- 2.35.3

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[PATCH] arm64: dts: imx8mq-kontron-pitx-imx8m-u-boot.dtsi: disable assigned clocks
by Heiko Thiery 17 Jun '22

17 Jun '22

With the move to use DM_CLK the boards uart stops working. The used properties are not supported by the imx8mq clock driver. Thus the correct baudrate cannot be selected. Remove this properties here and the board can start with working uart. Keep it in the main dts because linux handles these porperties fine. Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- .../arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi b/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi index 6f9c81462e..d361f3f559 100644 --- a/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi @@ -10,3 +10,18 @@ sd-uhs-sdr104; sd-uhs-ddr50; }; + +&uart1 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; +}; + +&uart2 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; +}; + +&uart3 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; +}; -- 2.30.2

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[PATCH v2] fs/squashfs: sqfs_read: Prevent arbitrary code execution
by Miquel Raynal 17 Jun '22

17 Jun '22

Following Jincheng's report, an out-of-band write leading to arbitrary code execution is possible because on one side the squashfs logic accepts directory names up to 65535 bytes (u16), while U-Boot fs logic accepts directory names up to 255 bytes long. Prevent such an exploit from happening by capping directory name sizes to 255. Use a define for this purpose so that developers can link the limitation to its source and eventually kill it some day by dynamically allocating this array (if ever desired). Link: https://lore.kernel.org/all/CALO=DHFB+yBoXxVr5KcsK0iFdg+e7ywko4-e+72kjbcS8J… Reported-by: Jincheng Wang <jc.w4ng(a)gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal(a)bootlin.com> --- Changes in v2: * Jincheng reported in private that there was a problem with small name sizes, the last byte was lost. The reason is, dirs->entry->name_size contains the length of the string minus one (and excluding the trailing '\0'). The previous implementation had this handled correctly but my initial fix did not kept the "+ 1" in place because it felt wrong but is actually necessary. This information is actually available in a comment a bit above in this file. fs/squashfs/sqfs.c | 8 +++++--- include/fs.h | 4 +++- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index b4484fa17f5..3f1030057c4 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -976,6 +976,7 @@ int sqfs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp) int i_number, offset = 0, ret; struct fs_dirent *dent; unsigned char *ipos; + u16 name_size; dirs = (struct squashfs_dir_stream *)fs_dirs; if (!dirs->size) { @@ -1058,9 +1059,10 @@ int sqfs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp) return -SQFS_STOP_READDIR; } - /* Set entry name */ - strncpy(dent->name, dirs->entry->name, dirs->entry->name_size + 1); - dent->name[dirs->entry->name_size + 1] = '\0'; + /* Set entry name (capped at FS_DIRENT_NAME_LEN which is a U-Boot limitation) */ + name_size = min_t(u16, dirs->entry->name_size + 1, FS_DIRENT_NAME_LEN - 1); + strncpy(dent->name, dirs->entry->name, name_size); + dent->name[name_size] = '\0'; offset = dirs->entry->name_size + 1 + SQFS_ENTRY_BASE_LENGTH; dirs->entry_count--; diff --git a/include/fs.h b/include/fs.h index b43f16a692f..2195dc172ec 100644 --- a/include/fs.h +++ b/include/fs.h @@ -174,6 +174,8 @@ int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len, #define FS_DT_REG 8 /* regular file */ #define FS_DT_LNK 10 /* symbolic link */ +#define FS_DIRENT_NAME_LEN 256 + /** * struct fs_dirent - directory entry * @@ -194,7 +196,7 @@ struct fs_dirent { /** change_time: time of last modification */ struct rtc_time change_time; /** name: file name */ - char name[256]; + char name[FS_DIRENT_NAME_LEN]; }; /* Note: fs_dir_stream should be treated as opaque to the user of fs layer */ -- 2.34.1

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[PATCH] usb: host: ehci-generic: Make resets and clocks optional
by Andre Przywara 17 Jun '22

17 Jun '22

The generic EHCI binding does not *require* resets and clocks properties, and indeed for instance the Allwinner A20 SoCs does not need or define any resets in its DT. Don't easily give up if clk_get_bulk() or reset_get_bulk() return an error, but check if that is due to the DT simply having no entries for either of them. This fixes USB operation on all boards with an Allwinner A10 or A20 SoC, which were reporting an error after commit ba96176ab70e2999: ======================= Bus usb@1c14000: ehci_generic usb@1c14000: Failed to get resets (err=-2) probe failed, error -2 ======================= Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- drivers/usb/host/ehci-generic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c index 4734af03962..15267e9a05a 100644 --- a/drivers/usb/host/ehci-generic.c +++ b/drivers/usb/host/ehci-generic.c @@ -69,7 +69,7 @@ static int ehci_usb_probe(struct udevice *dev) err = 0; ret = clk_get_bulk(dev, &priv->clocks); - if (ret) { + if (ret && ret != -ENOENT) { dev_err(dev, "Failed to get clocks (ret=%d)\n", ret); return ret; } @@ -81,7 +81,7 @@ static int ehci_usb_probe(struct udevice *dev) } err = reset_get_bulk(dev, &priv->resets); - if (err) { + if (ret && ret != -ENOENT) { dev_err(dev, "Failed to get resets (err=%d)\n", err); goto clk_err; } -- 2.35.3

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[PATCH] .gitignore: add files produced by b4
by Andrey Zhizhikin 17 Jun '22

17 Jun '22

b4 utility [1] is introduced by Linux Kernel developers and used to fetch patches and patch series from lore.kernel.org and is proven to be useful for U-Boot development. Detailed usage of the tool can be read under post from the original author [2]. This tool fetches files from the list and populates the source folder with additional files (*.cover and *.mbx) which are not ignored by git and shown as newly added files. Add those file patterns into .gitignore file, so they can be safely skipped during changes attestation. Link: [1]: https://pypi.org/project/b4/ Link: [2]: https://people.kernel.org/monsieuricon/introducing-b4-and-patch-attestation Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin(a)leica-geosystems.com> --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 28c439f09f..eb769f144c 100644 --- a/.gitignore +++ b/.gitignore @@ -10,6 +10,7 @@ *.asn1.[ch] *.bin *.cfgout +*.cover *.dtb *.dtbo *.dtb.S @@ -22,6 +23,7 @@ *.lex.c *.lst *.mod.c +*.mbx *.o *.o.* *.order base-commit: 8f527342db4160a1f030de6fe4a1591787cce65a -- 2.25.1

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[PATCH] Update email address and company name
by Christophe Leroy 17 Jun '22

17 Jun '22

This patch updates my email address and company name. Signed-off-by: Christophe Leroy <christophe.leroy(a)csgroup.eu> --- board/cssi/MAINTAINERS | 4 ++-- doc/git-mailrc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/cssi/MAINTAINERS b/board/cssi/MAINTAINERS index cbf1406a54..7d237b0b20 100644 --- a/board/cssi/MAINTAINERS +++ b/board/cssi/MAINTAINERS @@ -1,5 +1,5 @@ -BOARDS from CS Systemes d'Information -M: Christophe Leroy <christophe.leroy(a)c-s.fr> +BOARDS from CS GROUP France +M: Christophe Leroy <christophe.leroy(a)csgroup.eu> S: Maintained F: board/cssi/ F: include/configs/MCR3000.h diff --git a/doc/git-mailrc b/doc/git-mailrc index 410be387be..0580f56790 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -97,7 +97,7 @@ alias nios2 nios alias powerpc uboot, afleming, stroese, wd, priyankajain, mariosix alias ppc powerpc -alias mpc8xx uboot, wd, Christophe Leroy <christophe.leroy(a)c-s.fr> +alias mpc8xx uboot, wd, Christophe Leroy <christophe.leroy(a)csgroup.eu> alias mpc83xx uboot, mariosix alias mpc85xx uboot, afleming, priyankajain -- 2.35.1

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