June 2022 - U-Boot

[PATCH] mach-rockchip: make_fit_atf.py: support OP-TEE tee.bin v1 format
by Jerome Forissier 20 Jun '22

20 Jun '22

This commit adds support for the OP-TEE 'tee.bin' v1 format for Rockchip platforms. Since OP-TEE 3.8.0, tee.bin contains meta-data in a proprietary format in addition to the ELF data. They are essential information for proper initialization of the TEE core, such as the size of the memory region covered by the TEE or a compact representation of runtime relocation data when ASLR is enabled. With OP-TEE 3.8.0 onwards, 'tee.elf' MUST NOT be used and 'tee.bin' MUST be used instead. Ignoring this recommendation can lead to crashes as described in [3]. Link: [1] https://github.com/OP-TEE/optee_os/commit/5dd1570ac5b0f6563b1a9c074533a1910… Link: [2] https://github.com/OP-TEE/optee_os/blob/3.17.0/scripts/gen_tee_bin.py#L275-… Link: [3] https://github.com/OP-TEE/optee_os/issues/4542 Signed-off-by: Jerome Forissier <jerome.forissier(a)linaro.org> --- arch/arm/mach-rockchip/make_fit_atf.py | 43 +++++++++++++++++++++----- 1 file changed, 35 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index f3224d2555..fcea652388 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -137,7 +137,7 @@ def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, tee_file_name, dtbs_file num_segments = len(segments) if tee_file_name: - tee_segments = unpack_elf(tee_file_name) + tee_segments = unpack_tee_file(tee_file_name) for index, entry, paddr, data in tee_segments: append_tee_node(fit_file, num_segments + index + 1, paddr, entry) num_segments = num_segments + len(tee_segments) @@ -169,7 +169,7 @@ def generate_atf_binary(bl31_file_name): def generate_tee_binary(tee_file_name): if tee_file_name: - for index, entry, paddr, data in unpack_elf(tee_file_name): + for index, entry, paddr, data in unpack_tee_file(tee_file_name): file_name = 'tee_0x%08x.bin' % paddr with open(file_name, "wb") as atf: atf.write(data) @@ -194,6 +194,31 @@ def unpack_elf(filename): segments.append((index, e_entry, p_paddr, p_data)) return segments +def unpack_tee_file(filename): + if filename.endswith('.elf'): + return unpack_elf(filename) + with open(filename, 'rb') as file: + bin = file.read() + segments = [] + if bin[0:5] == b'OPTE\x01': + # OP-TEE v1 format (tee.bin) + init_sz, start_hi, start_lo, _, paged_sz = struct.unpack_from('<5I', + bin, + 0x8) + if paged_sz != 0: + raise ValueError("OP-TEE paged mode not supported") + e_entry = (start_hi << 32) + start_lo + p_addr = e_entry + p_data = bin[0x1c:] + if len(p_data) != init_sz: + raise ValueError("Invalid file '%s': size mismatch " + "(expected %d, have %d)" % (filename, init_sz, + len(p_data))) + segments.append((0, e_entry, p_addr, p_data)) + else: + raise ValueError("Unknown format for TEE file '%s'" % filename) + return segments + def main(): uboot_elf = "./u-boot" fit_its = sys.stdout @@ -210,11 +235,13 @@ def main(): logging.warning(' Please read Building section in doc/README.rockchip') if "TEE" in os.environ: - tee_elf = os.getenv("TEE") + tee_file = os.getenv("TEE") + elif os.path.isfile("./tee.bin"): + tee_file = "./tee.bin" elif os.path.isfile("./tee.elf"): - tee_elf = "./tee.elf" + tee_file = "./tee.elf" else: - tee_elf = "" + tee_file = "" opts, args = getopt.getopt(sys.argv[1:], "o:u:b:t:h") for opt, val in opts: @@ -225,16 +252,16 @@ def main(): elif opt == "-b": bl31_elf = val elif opt == "-t": - tee_elf = val + tee_file = val elif opt == "-h": print(__doc__) sys.exit(2) dtbs = args - generate_atf_fit_dts(fit_its, bl31_elf, tee_elf, uboot_elf, dtbs) + generate_atf_fit_dts(fit_its, bl31_elf, tee_file, uboot_elf, dtbs) generate_atf_binary(bl31_elf) - generate_tee_binary(tee_elf) + generate_tee_binary(tee_file) if __name__ == "__main__": main() -- 2.17.1

5 9

[PATCH 01/10] i2c: stm32: add support for the st,stm32mp13 SOC
by Patrick Delaunay 20 Jun '22

20 Jun '22

The stm32mp13 soc differs from the stm32mp15 in terms of clear register offset for controlling the FMP (Fast Mode Plus). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/i2c/stm32f7_i2c.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index c6ae65badb7..bf2a6c9b4bd 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -267,6 +267,10 @@ static const struct stm32_i2c_data stm32mp15_data = { .fmp_clr_offset = 0x40, }; +static const struct stm32_i2c_data stm32mp13_data = { + .fmp_clr_offset = 0x4, +}; + static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) { struct stm32_i2c_regs *regs = i2c_priv->regs; @@ -957,6 +961,7 @@ static const struct dm_i2c_ops stm32_i2c_ops = { static const struct udevice_id stm32_i2c_of_match[] = { { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_data }, { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_data }, + { .compatible = "st,stm32mp13-i2c", .data = (ulong)&stm32mp13_data }, {} }; -- 2.25.1

2 10

[PATCH] drivers: usb: dwc3: Add support for AM62 USB wrapper driver
by Aswath Govindraju 20 Jun '22

20 Jun '22

Add support for AM62 USB wrapper for DWC3 Controller in AM62 SoC. Signed-off-by: Aswath Govindraju <a-govindraju(a)ti.com> --- Link to corresponding kernel dt-bindings and driver patches, - https://patchwork.kernel.org/project/linux-usb/list/?series=629613 drivers/usb/dwc3/Kconfig | 7 + drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-am62.c | 284 +++++++++++++++++++++++++++++++++++ 3 files changed, 292 insertions(+) create mode 100644 drivers/usb/dwc3/dwc3-am62.c diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 62aa65bf0cd2..87e19720ab84 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -63,6 +63,13 @@ config USB_DWC3_LAYERSCAPE Host and Peripheral operation modes are supported. OTG is not supported. +config USB_DWC3_AM62 + tristate "Texas Instruments AM62 Platforms" + depends on ARCH_K3 || COMPILE_TEST + default USB_DWC3 + help + Support of USB2 functionality in TI's AM62 platforms + menu "PHY Subsystem" config USB_DWC3_PHY_OMAP diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 0dd1ba87cd94..26bc3a7379b7 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -7,6 +7,7 @@ dwc3-y := core.o obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o +obj-$(CONFIG_USB_DWC3_AM62) += dwc3-am62.o obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o diff --git a/drivers/usb/dwc3/dwc3-am62.c b/drivers/usb/dwc3/dwc3-am62.c new file mode 100644 index 000000000000..a3ad609036e2 --- /dev/null +++ b/drivers/usb/dwc3/dwc3-am62.c @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dwc3-am62.c - TI specific Glue layer for AM62 DWC3 USB Controller + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com + */ + +#include <common.h> +#include <asm-generic/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <syscon.h> +#include <malloc.h> +#include <usb.h> +#include <usb/xhci.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <regmap.h> +#include <linux/usb/otg.h> +#include <dm/lists.h> + +/* USB WRAPPER register offsets */ +#define USBSS_PID 0x0 +#define USBSS_OVERCURRENT_CTRL 0x4 +#define USBSS_PHY_CONFIG 0x8 +#define USBSS_PHY_TEST 0xc +#define USBSS_CORE_STAT 0x14 +#define USBSS_HOST_VBUS_CTRL 0x18 +#define USBSS_MODE_CONTROL 0x1c +#define USBSS_WAKEUP_CONFIG 0x30 +#define USBSS_WAKEUP_STAT 0x34 +#define USBSS_OVERRIDE_CONFIG 0x38 +#define USBSS_IRQ_MISC_STATUS_RAW 0x430 +#define USBSS_IRQ_MISC_STATUS 0x434 +#define USBSS_IRQ_MISC_ENABLE_SET 0x438 +#define USBSS_IRQ_MISC_ENABLE_CLR 0x43c +#define USBSS_IRQ_MISC_EOI 0x440 +#define USBSS_INTR_TEST 0x490 +#define USBSS_VBUS_FILTER 0x614 +#define USBSS_VBUS_STAT 0x618 +#define USBSS_DEBUG_CFG 0x708 +#define USBSS_DEBUG_DATA 0x70c +#define USBSS_HOST_HUB_CTRL 0x714 + +/* PHY CONFIG register bits */ +#define USBSS_PHY_VBUS_SEL_MASK GENMASK(2, 1) +#define USBSS_PHY_VBUS_SEL_SHIFT 1 +#define USBSS_PHY_LANE_REVERSE BIT(0) + +/* MODE CONTROL register bits */ +#define USBSS_MODE_VALID BIT(0) + +/* IRQ_MISC_STATUS_RAW register bits */ +#define USBSS_IRQ_MISC_RAW_VBUSVALID BIT(22) +#define USBSS_IRQ_MISC_RAW_SESSVALID BIT(20) + +/* IRQ_MISC_STATUS register bits */ +#define USBSS_IRQ_MISC_VBUSVALID BIT(22) +#define USBSS_IRQ_MISC_SESSVALID BIT(20) + +/* IRQ_MISC_ENABLE_SET register bits */ +#define USBSS_IRQ_MISC_ENABLE_SET_VBUSVALID BIT(22) +#define USBSS_IRQ_MISC_ENABLE_SET_SESSVALID BIT(20) + +/* IRQ_MISC_ENABLE_CLR register bits */ +#define USBSS_IRQ_MISC_ENABLE_CLR_VBUSVALID BIT(22) +#define USBSS_IRQ_MISC_ENABLE_CLR_SESSVALID BIT(20) + +/* VBUS_STAT register bits */ +#define USBSS_VBUS_STAT_SESSVALID BIT(2) +#define USBSS_VBUS_STAT_VBUSVALID BIT(0) + +/* Mask for PHY PLL REFCLK */ +#define PHY_PLL_REFCLK_MASK GENMASK(3, 0) + +struct dwc3_data { + struct udevice *dev; + void __iomem *usbss; + struct regmap *syscon; + unsigned int offset; + unsigned int vbus_divider; +}; + +static inline u32 dwc3_ti_readl(struct dwc3_data *data, u32 offset) +{ + return readl(data->usbss + offset); +} + +static inline void dwc3_ti_writel(struct dwc3_data *data, u32 offset, u32 value) +{ + writel(value, data->usbss + offset); +} + +static const int dwc3_ti_rate_table[] = { /* in KHZ */ + 9600, + 10000, + 12000, + 19200, + 20000, + 24000, + 25000, + 26000, + 38400, + 40000, + 58000, + 50000, + 52000, +}; + +static int phy_syscon_pll_refclk(struct dwc3_data *data, int rate_code) +{ + struct udevice *dev = data->dev; + struct ofnode_phandle_args args; + ofnode node = dev_ofnode(dev); + struct regmap *syscon; + int ret; + + syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-phy-pll-refclk"); + if (IS_ERR(syscon)) { + dev_err(dev, "unable to get ti,syscon-phy-pll-refclk regmap\n"); + return PTR_ERR(syscon); + } + + data->syscon = syscon; + + ret = ofnode_parse_phandle_with_args(node, "ti,syscon-phy-pll-refclk", NULL, 1, + 0, &args); + if (ret) + return ret; + + data->offset = args.args[0]; + + /* Program PHY PLL refclk by reading syscon property */ + ret = regmap_update_bits(data->syscon, data->offset, PHY_PLL_REFCLK_MASK, rate_code); + if (ret) { + dev_err(dev, "failed to set phy pll reference clock rate\n"); + return ret; + } + + return 0; +} + +static int dwc3_ti_bind(struct udevice *parent) +{ + ofnode node; + const char *name = ofnode_get_name(node); + enum usb_dr_mode dr_mode; + struct udevice *dev; + const char *driver = NULL; + int ret; + + node = ofnode_by_compatible(dev_ofnode(parent), "snps,dwc3"); + if (!ofnode_valid(node)) { + ret = -ENODEV; + return 0; + } + + name = ofnode_get_name(node); + dr_mode = usb_get_dr_mode(node); + debug("%s: subnode name: %s\n", __func__, name); + + switch (dr_mode) { + case USB_DR_MODE_PERIPHERAL: + case USB_DR_MODE_OTG: +#if CONFIG_IS_ENABLED(DM_USB_GADGET) + debug("%s: dr_mode: OTG or Peripheral\n", __func__); + driver = "dwc3-generic-peripheral"; +#endif + break; +#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD) + case USB_DR_MODE_HOST: + debug("%s: dr_mode: HOST\n", __func__); + driver = "dwc3-generic-host"; + break; +#endif + default: + debug("%s: unsupported dr_mode\n", __func__); + return -ENODEV; + }; + + if (!driver) + return 0; + + ret = device_bind_driver_to_node(parent, driver, name, + node, &dev); + if (ret) { + debug("%s: not able to bind usb device mode\n", + __func__); + return ret; + } + + return 0; +} + +static int dwc3_ti_probe(struct udevice *dev) +{ + struct dwc3_data *data = dev_get_plat(dev); + struct clk usb2_refclk; + int rate_code, i, ret; + unsigned long rate; + u32 reg; + + data->dev = dev; + + data->usbss = dev_remap_addr_index(dev, 0); + if (IS_ERR(data->usbss)) { + dev_err(dev, "can't map IOMEM resource\n"); + return PTR_ERR(data->usbss); + } + + ret = clk_get_by_name(dev, "ref", &usb2_refclk); + if (ret) { + dev_err(dev, "can't get usb2_refclk\n"); + return ret; + } + + /* Calcuate the rate code */ + rate = clk_get_rate(&usb2_refclk); + rate /= 1000; /* To KHz */ + for (i = 0; i < ARRAY_SIZE(dwc3_ti_rate_table); i++) { + if (dwc3_ti_rate_table[i] == rate) + break; + } + + if (i == ARRAY_SIZE(dwc3_ti_rate_table)) { + dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate); + return -EINVAL; + } + + rate_code = i; + + /* Read the syscon property */ + ret = phy_syscon_pll_refclk(data, rate_code); + if (ret) + return ret; + + /* VBUS divider select */ + reg = dwc3_ti_readl(data, USBSS_PHY_CONFIG); + data->vbus_divider = dev_read_bool(dev, "ti,vbus-divider"); + if (data->vbus_divider) + reg |= 1 << USBSS_PHY_VBUS_SEL_SHIFT; + + dwc3_ti_writel(data, USBSS_PHY_CONFIG, reg); + + /* Set mode valid */ + reg = dwc3_ti_readl(data, USBSS_MODE_CONTROL); + reg |= USBSS_MODE_VALID; + dwc3_ti_writel(data, USBSS_MODE_CONTROL, reg); + + return 0; +} + +/* work queue not required to cancel separately as auto cancel API was used*/ +static int dwc3_ti_remove(struct udevice *dev) +{ + struct dwc3_data *data = dev_get_plat(dev); + u32 reg; + + /* Clear mode valid */ + reg = dwc3_ti_readl(data, USBSS_MODE_CONTROL); + reg &= ~USBSS_MODE_VALID; + dwc3_ti_writel(data, USBSS_MODE_CONTROL, reg); + + return 0; +} + +static const struct udevice_id dwc3_ti_of_match[] = { + { .compatible = "ti,am62-usb", }, + {}, +}; + +U_BOOT_DRIVER(dwc3_ti) = { + .name = "dwc3-ti", + .id = UCLASS_NOP, + .of_match = dwc3_ti_of_match, + .bind = dwc3_ti_bind, + .probe = dwc3_ti_probe, + .remove = dwc3_ti_remove, + .plat_auto = sizeof(struct dwc3_data), + .flags = DM_FLAG_OS_PREPARE, +}; -- 2.17.1

2 1

[PULL] Pull request for u-boot next / v2022.10 = u-boot-stm32-20220620
by Patrick DELAUNAY 20 Jun '22

20 Jun '22

I Tom, Please pull the STM32 related fixes for u-boot/next, v2022.10: u-boot-stm32-20220620 - Add STM32MP13 SoCs support with associated board STM32M135F-DK - Correct livetree support in stm32mp1 boards - Activate livetree for stm32mp15 DHSOM boards CI status: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/12393 Thanks, Patrick git request-pull origin/nexthttps://source.denx.de/u-boot/custodians/u-boot-stm.git/ u-boot-stm32-20220620 The following changes since commit 98c4828740f4944462b7d9608b95d5b73850c7b0: Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next (2022-06-16 09:27:43 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-stm.git/ tags/u-boot-stm32-20220620 for you to fetch changes up to eae488b77906692627622abc61f5b7160b6eb2a4: stm32mp1: fix reference for STMicroelectronics (2022-06-17 14:12:27 +0200) ---------------------------------------------------------------- - Add STM32MP13 SoCs support with associated board STM32M135F-DK - Correct livetree support in stm32mp1 boards - Activate livetree for stm32mp15 DHSOM boards ---------------------------------------------------------------- Patrick Delaunay (27): ARM: dts: stm32: add STM32MP13 SoCs support configs: stm32mp1: move SUPPORT_SPL in STM32MP15x arm: stm32mp: move the get_otp helper function in bsec arm: stm32mp: move code for STM32MP15x arm: stm32mp: add choice for STM32MP SOC family arm: stm32mp: add sub config Kconfig.15x arm: stm32mp: add CONFIG_STM32MP15_PWR arm: stm32mp: add support of STM32MP13x arm: stm32mp: support 2 MAC address for STM32MP13 pinctrl: stm32: add support of STM32MP135 board: stm32pm1: add stm32mp13 board support ram: stm32mp1: add support of STM32MP13x mmc: stm32_sdmmc2: make reset property optional arm: dts: stm32mp: add stm32mp13 device tree for U-Boot configs: add stm32mp13 defconfig doc: st: stm32mp1: add STM32MP13x support stm32mp: fdt: update etzpc for STM32MP15x stm32mp: fdt: update etzpc for STM32MP13x clk: Add directory for STM32 clock drivers misc: stm32mp13: introduce STM32MP13 RCC driver board: stm32mp1: convert to livetree board: engicam: stm32mp1: convert to livetree board: dhelectronics: stm32mp1: convert to livetree ARM: stm32: activate OF_LIVE for DHSOM stm32mp: stpmic1: remove the debug unit request by debugger configs: stm32mp: cleanup the stm32mp15 file stm32mp1: fix reference for STMicroelectronics MAINTAINERS | 2 +- arch/arm/Kconfig | 3 +- arch/arm/cpu/armv7/stv0991/lowlevel.S | 2 +- arch/arm/dts/Makefile | 3 ++ arch/arm/dts/stm32mp13-pinctrl.dtsi | 123 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/stm32mp13-u-boot.dtsi | 91 ++++++++++++++++++++++++++++++++ arch/arm/dts/stm32mp131.dtsi | 358 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/stm32mp133.dtsi | 37 +++++++++++++ arch/arm/dts/stm32mp135.dtsi | 12 +++++ arch/arm/dts/stm32mp135f-dk-u-boot.dtsi | 30 +++++++++++ arch/arm/dts/stm32mp135f-dk.dts | 57 ++++++++++++++++++++ arch/arm/dts/stm32mp13xc.dtsi | 17 ++++++ arch/arm/dts/stm32mp13xf.dtsi | 17 ++++++ arch/arm/mach-sti/Kconfig | 2 +- arch/arm/mach-stm32mp/Kconfig | 146 +++++++++------------------------------------------ arch/arm/mach-stm32mp/Kconfig.13x | 57 ++++++++++++++++++++ arch/arm/mach-stm32mp/Kconfig.15x | 135 +++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-stm32mp/Makefile | 5 +- arch/arm/mach-stm32mp/bsec.c | 17 ++++++ arch/arm/mach-stm32mp/cpu.c | 392 ++++++++++++++++------------------------------------------------------------------------------------------------------------------------ arch/arm/mach-stm32mp/fdt.c | 277 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------- arch/arm/mach-stm32mp/include/mach/stm32.h | 27 +++++++++- arch/arm/mach-stm32mp/include/mach/sys_proto.h | 34 ++++++++++-- arch/arm/mach-stm32mp/spl.c | 1 + arch/arm/mach-stm32mp/stm32mp13x.c | 135 +++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-stm32mp/stm32mp15x.c | 350 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/dhelectronics/dh_stm32mp1/board.c | 38 ++++++-------- board/engicam/stm32mp1/stm32mp1.c | 6 +-- board/st/common/stpmic1.c | 14 ----- board/st/stm32mp1/Kconfig | 15 ++++++ board/st/stm32mp1/MAINTAINERS | 4 ++ board/st/stm32mp1/stm32mp1.c | 31 +++++------ configs/stm32mp13_defconfig | 55 +++++++++++++++++++ configs/stm32mp15_basic_defconfig | 6 +-- configs/stm32mp15_defconfig | 6 +-- configs/stm32mp15_dhcom_basic_defconfig | 1 + configs/stm32mp15_dhcor_basic_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 8 +-- doc/board/st/stm32mp1.rst | 183 ++++++++++++++++++++++++++++++++++++++++++++-------------------- doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt | 49 +++++++++++++---- drivers/clk/Kconfig | 17 +----- drivers/clk/Makefile | 5 +- drivers/clk/stm32/Kconfig | 23 ++++++++ drivers/clk/stm32/Makefile | 7 +++ drivers/clk/{clk_stm32f.c => stm32/clk-stm32f.c} | 0 drivers/clk/{clk_stm32h7.c => stm32/clk-stm32h7.c} | 0 drivers/clk/{clk_stm32mp1.c => stm32/clk-stm32mp1.c} | 0 drivers/i2c/designware_i2c.c | 2 +- drivers/i2c/designware_i2c.h | 2 +- drivers/i2c/designware_i2c_pci.c | 2 +- drivers/misc/stm32_rcc.c | 6 +++ drivers/mmc/stm32_sdmmc2.c | 14 ++--- drivers/mtd/nand/raw/fsmc_nand.c | 4 +- drivers/mtd/spi/spi-nor-ids.c | 2 +- drivers/net/designware.c | 2 +- drivers/net/designware.h | 2 +- drivers/pinctrl/Kconfig | 2 +- drivers/pinctrl/pinctrl_stm32.c | 1 + drivers/ram/stm32mp1/stm32mp1_ram.c | 28 ++++++---- drivers/spi/pl022_spi.c | 2 +- drivers/usb/gadget/designware_udc.c | 2 +- include/configs/stm32mp13_common.h | 100 +++++++++++++++++++++++++++++++++++ include/configs/stm32mp13_st_common.h | 17 ++++++ include/configs/stm32mp15_common.h | 13 +---- include/configs/stm32mp15_st_common.h | 2 +- include/elf.h | 4 +- include/linux/mtd/fsmc_nand.h | 2 +- include/power/stpmic1.h | 3 -- include/usb/designware_udc.h | 2 +- 69 files changed, 2274 insertions(+), 739 deletions(-) create mode 100644 arch/arm/dts/stm32mp13-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp13-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp131.dtsi create mode 100644 arch/arm/dts/stm32mp133.dtsi create mode 100644 arch/arm/dts/stm32mp135.dtsi create mode 100644 arch/arm/dts/stm32mp135f-dk-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp135f-dk.dts create mode 100644 arch/arm/dts/stm32mp13xc.dtsi create mode 100644 arch/arm/dts/stm32mp13xf.dtsi create mode 100644 arch/arm/mach-stm32mp/Kconfig.13x create mode 100644 arch/arm/mach-stm32mp/Kconfig.15x create mode 100644 arch/arm/mach-stm32mp/stm32mp13x.c create mode 100644 arch/arm/mach-stm32mp/stm32mp15x.c create mode 100644 configs/stm32mp13_defconfig create mode 100644 drivers/clk/stm32/Kconfig create mode 100644 drivers/clk/stm32/Makefile rename drivers/clk/{clk_stm32f.c => stm32/clk-stm32f.c} (100%) rename drivers/clk/{clk_stm32h7.c => stm32/clk-stm32h7.c} (100%) rename drivers/clk/{clk_stm32mp1.c => stm32/clk-stm32mp1.c} (100%) create mode 100644 include/configs/stm32mp13_common.h create mode 100644 include/configs/stm32mp13_st_common.h

2 1

Please pull u-boot-fsl-qoirq: next
by Peng Fan (OSS) 20 Jun '22

20 Jun '22

Hi Tom, Please pull u-boot-fsl-qoriq for next CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/12429 ---------------------------------------------- Layerscape: add sfp driver Kconfig cleanup sl28 board update support hdp firmware loading powerpc: dts update for p2020 p1_p2_rdb_pc board update fsl_esdhc fallback to 1-bit mode support ---------------------------------------------- Thanks, Peng. The following changes since commit 98c4828740f4944462b7d9608b95d5b73850c7b0: Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next (2022-06-16 09:27:43 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git tags/fsl-qoriq-2022-6-20-v2 for you to fetch changes up to 7bc683afda5ede82cfcace77cecab1891d6d93ff: board: sl28: rename include guard macro (2022-06-20 15:52:45 +0800) ---------------------------------------------------------------- Alison Wang (1): ls1028a: hdp: Add config support for HDP firmware loading Michael Walle (5): armv8: layerscape: add missing RCW source defines board: sl28: set CPO value board: sl28: remove unneeded ddr config parameter board: sl28: support 8 GiB memory board: sl28: rename include guard macro Pali Rohár (16): powerpc: dts: p2020: Define MPIC nodes powerpc: dts: p2020: Define crypto node powerpc: dts: p2020: Define DMA nodes powerpc: dts: p2020: Define ecm, memory and guts nodes powerpc: mpc85xx: Fix compilation with CONFIG_WDT board: freescale: p1_p2_rdb_pc: Enable TDM function only for P1010 board: freescale: p1_p2_rdb_pc: Implement board_reset() powerpc: fsl_law: Add definition for first PCIe target interface powerpc: mmu: Fix FSL_BOOKE_MAS2() macro mtd: rawnand: fsl_elbc: Fix DM support in DTS code path powerpc: mpc85xx: Set default SYS_IMMR value for P1/P2 CPUs mmc: fsl_esdhc: Set fallback mode to 1-bit mmc: fsl_esdhc: Add new config option for default fallback mode powerpc: dts: p2020: Define PMC node board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h powerpc: bootm: Fix sizes in memory adjusting warning Sean Anderson (4): arm: layerscape: Add sfp driver ARM: dts: ls1021a: update the clockgen node arch: layerscape: Add SFP binding ARM: layerscape: Use ARCH_LS104?A insead of TARGET_LS104?ARDB MAINTAINERS | 5 ++ arch/Kconfig | 3 ++ arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 10 ++-- arch/arm/dts/fsl-ls1012a.dtsi | 7 +++ arch/arm/dts/fsl-ls1043a.dtsi | 7 +++ arch/arm/dts/fsl-ls1046a.dtsi | 7 +++ arch/arm/dts/ls1021a.dtsi | 87 ++++++++++++------------------ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++ arch/powerpc/cpu/mpc85xx/cpu.c | 2 + arch/powerpc/dts/p2020-post.dtsi | 36 +++++++++++++ arch/powerpc/dts/pq3-dma-0.dtsi | 66 +++++++++++++++++++++++ arch/powerpc/dts/pq3-dma-1.dtsi | 66 +++++++++++++++++++++++ arch/powerpc/dts/pq3-mpic-timer-B.dtsi | 42 +++++++++++++++ arch/powerpc/dts/pq3-mpic.dtsi | 79 +++++++++++++++++++++++++++ arch/powerpc/dts/pq3-sec3.1-0.dtsi | 45 ++++++++++++++++ arch/powerpc/include/asm/fsl_law.h | 1 + arch/powerpc/include/asm/mmu.h | 2 +- arch/powerpc/lib/bootm.c | 3 +- board/freescale/ls1028a/ls1028a.c | 7 ++- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 8 +++ board/kontron/sl28/ddr.c | 12 ++++- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 + configs/ls1028aqds_tfa_defconfig | 2 + configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 + configs/ls1028ardb_tfa_defconfig | 2 + drivers/misc/Kconfig | 14 +++++ drivers/misc/Makefile | 1 + drivers/misc/ls2_sfp.c | 350 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/mmc/Kconfig | 5 ++ drivers/mmc/fsl_esdhc.c | 6 +-- drivers/mtd/nand/raw/fsl_elbc_nand.c | 9 ++-- include/configs/kontron_sl28.h | 6 +-- include/configs/p1_p2_bootsrc.h | 59 ++++++++++++++++++++ include/configs/p1_p2_rdb_pc.h | 41 ++++---------- 34 files changed, 894 insertions(+), 104 deletions(-) create mode 100644 arch/powerpc/dts/pq3-dma-0.dtsi create mode 100644 arch/powerpc/dts/pq3-dma-1.dtsi create mode 100644 arch/powerpc/dts/pq3-mpic-timer-B.dtsi create mode 100644 arch/powerpc/dts/pq3-mpic.dtsi create mode 100644 arch/powerpc/dts/pq3-sec3.1-0.dtsi create mode 100644 drivers/misc/ls2_sfp.c create mode 100644 include/configs/p1_p2_bootsrc.h

2 1

[PATCH 00/10] xilinx: zynqmp: Support foreign vendor boards
by Stefan Herbrechtsmeier 20 Jun '22

20 Jun '22

From: Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> At the moment the xilinx zynqmp soc is only supported by xilinx vendor boards. Rework the xilinx zynqmp board code to support reuse by foreign vendor boards. Stefan Herbrechtsmeier (10): firmware: firmware-zynqmp: Check if rx channel dev pointer is valid firmware: firmware-zynqmp: Probe driver before use soc: xilinx: zynqmp: Add machine identification support xilinx: zynqmp: Use soc machine function to get silicon idcode name xilinx: cpuinfo: Print soc machine xilinx: common: Separate display cpu info function xilinx: zynqmp: make spi flash support optional tools: zynqmp_psu_init_minimize: Remove low level uart settings tools: zynqmp_psu_init_minimize: Add serdes_illcalib forward declaration xilinx: zynqmp: Support vendor specific board_init board/xilinx/common/Makefile | 3 + board/xilinx/common/board.c | 30 +-- board/xilinx/common/board.h | 2 + board/xilinx/common/cpu-info.c | 35 ++++ board/xilinx/zynqmp/zynqmp.c | 291 ++--------------------------- drivers/firmware/firmware-zynqmp.c | 20 +- drivers/soc/soc_xilinx_zynqmp.c | 289 +++++++++++++++++++++++++++- tools/zynqmp_psu_init_minimize.sh | 22 +++ 8 files changed, 390 insertions(+), 302 deletions(-) create mode 100644 board/xilinx/common/cpu-info.c -- 2.30.2

2 27

[PATCH v4] ARM: imx: Switch Data Modul i.MX8M Mini eDM SBC to USB251x Hub driver
by Marek Vasut 20 Jun '22

20 Jun '22

Replace the ad-hoc I2C register programming scripted in board environment with U-Boot DM driver. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- V2: Use uclass_get_device_by_name() V3: Reinstate the device-internal.h, needed for device_probe() V4: Drop the device_probe() too --- .../imx8mm_data_modul_edm_sbc.c | 9 +++++++++ configs/imx8mm_data_modul_edm_sbc_defconfig | 1 + include/configs/imx8mm_data_modul_edm_sbc.h | 20 ------------------- 3 files changed, 10 insertions(+), 20 deletions(-) diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index 46cb6f77b59..6dc4e6a9a2b 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -9,6 +9,7 @@ #include <asm/io.h> #include <asm/mach-imx/boot_mode.h> #include <dm.h> +#include <dm/device-internal.h> #include <i2c_eeprom.h> #include <malloc.h> #include <net.h> @@ -104,7 +105,15 @@ int board_init(void) int board_late_init(void) { + struct udevice *dev; + int ret; + setup_boot_device(); setup_mac_address(); + + ret = uclass_get_device_by_name(UCLASS_MISC, "usb-hub@2c", &dev); + if (ret) + printf("Error bringing up USB hub (%d)\n", ret); + return 0; } diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index d55efa6d00e..99a1f862200 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -156,6 +156,7 @@ CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y # CONFIG_INPUT is not set CONFIG_MISC=y +CONFIG_USB_HUB_USB251XB=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 67667dd523d..419258f949a 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -71,7 +71,6 @@ "mtd nor0=sf raw 0x0 0x1000000\0" \ "dmo_preboot=" \ "sf probe ; " /* Scan for SPI NOR, needed by DFU */ \ - "run dmo_usb_start_hub ; " \ /* Attempt to start USB and Network console */ \ "run dmo_usb_cdc_acm_start ; " \ "run dmo_netconsole_start\0" \ @@ -91,25 +90,6 @@ "setenv stdin ${stdin},usbacm ; " \ "fi ; " \ "fi\0" \ - "dmo_usb_start_hub=" \ - "i2c dev 1 ; " \ - /* Reset the USB USB */ \ - "gpio clear GPIO5_2 ; sleep 0.01 ; " /* t1 > 1us */ \ - "gpio set GPIO5_2 ; sleep 0.01 ; " /* t5 > 3us */ \ - /* Write chunks of descriptor into the USB HUB */ \ - "mw.l 0x7e1000 0x14042417 ; mw.l 0x7e1004 0x9b0bb325 ; "\ - "mw.l 0x7e1008 0x00000220 ; mw.l 0x7e100c 0x01320100 ; "\ - "mw.l 0x7e1010 0x00003232 ; mw.l 0x7e1014 0x4d000909 ; "\ - "i2c write 0x7e1000 0x2c 0x00 0x18 -s ; " \ - "mw.l 0x7e1000 0x6300690f ; mw.l 0x7e1004 0x6f007200 ; "\ - "mw.l 0x7e1008 0x68006300 ; mw.l 0x7e100c 0x70006900 ; "\ - "i2c write 0x7e1000 0x2c 0x18 0x10 -s ; " \ - "mw.l 0x7e1000 0x53005511 ; mw.l 0x7e1004 0x32004200 ; "\ - "mw.l 0x7e1008 0x31003500 ; mw.l 0x7e100c 0x42003400 ; "\ - "mw.l 0x7e1010 0x00006900 ; " \ - "i2c write 0x7e1000 0x2c 0x54 0x12 -s ; " \ - "mw.l 0x7e1000 0x00000101 ; " \ - "i2c write 0x7e1000 0x2c 0xff 0x2 -s\0" \ "dmo_netconsole_start=" \ "if test \"${dmo_netconsole_enabled}\" = \"true\" ; then "\ "setenv autoload false && " \ -- 2.35.1

2 1

[PATCH] mtd: rawnand: fsl_elbc: Fix detection when nand_scan_ident() has not selected ecc.mode
by Pali Rohár 20 Jun '22

20 Jun '22

ecc.mode is set to 0 (aliased to NAND_ECC_NONE) either when function nand_scan_ident() has not selected ecc.mode or when it selected it to none ecc mode. Distinguish between these two states by checking of node property "nand-ecc-mode" which function nand_scan_ident() uses for filling ecc.mode. This change fixes usage of none ecc mode if it is specified in DTS file. Fixes: c9ea9019c5aa ("mtd: rawnand: fsl_elbc: Use ECC configuration from device tree") Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/mtd/nand/raw/fsl_elbc_nand.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index b0e3eb607ed4..8e14739b3ee9 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -745,7 +745,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev) return ret; /* If nand_scan_ident() has not selected ecc.mode, do it now */ - if (nand->ecc.mode == NAND_ECC_NONE) { + if (nand->ecc.mode == 0 && + !ofnode_read_string(nand->flash_node, "nand-ecc-mode")) { /* If CS Base Register selects full hardware ECC then use it */ if ((br & BR_DECC) == BR_DECC_CHK_GEN) { nand->ecc.mode = NAND_ECC_HW; -- 2.20.1

2 3

Extend binman to generate boot headers
by Peng Fan 20 Jun '22

20 Jun '22

Hi all, I am thinking to extend binman to generate i.MX container header and IVT header, that means to replace mkimage to generate header. There is an NXP downstream imx-mkimage that diverge from upstream that double effort. There are still require quite effort to migrate downstream imx-mkimage to upstream. But the good news is that we are trying binman in imx-mkimage to pack images. So if we could support binman to generate container/IVT headers, NXP downstream and upstream will align the effort to focus on binman, not a diverge imx-mkimage. How do you think? Thanks, Peng.

3 2

[PATCH] led: pwm: Use NOP uclass driver for top-level node
by Stefan Herbrechtsmeier 20 Jun '22

20 Jun '22

From: Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> The top level DT node of pwm-leds is not a LED itself, bind NOP uclass driver to it, and bind different LED uclass driver to its subnodes which represent the actual LEDs. This change removes the top-level node from the 'led list' command output and is based on the commit 01074697801b ("led: gpio: Use NOP uclass driver for top-level node"). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> --- drivers/led/led_pwm.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/led/led_pwm.c b/drivers/led/led_pwm.c index 10bd1636c3..7d2f7686be 100644 --- a/drivers/led/led_pwm.c +++ b/drivers/led/led_pwm.c @@ -97,10 +97,6 @@ static int led_pwm_probe(struct udevice *dev) struct led_pwm_priv *priv = dev_get_priv(dev); struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev); - /* Ignore the top-level LED node */ - if (!uc_plat->label) - return 0; - return led_pwm_set_state(dev, (priv->enabled) ? LEDST_ON : LEDST_OFF); } @@ -112,10 +108,6 @@ static int led_pwm_of_to_plat(struct udevice *dev) uint def_brightness, max_brightness; int ret; - /* Ignore the top-level LED node */ - if (!uc_plat->label) - return 0; - ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0, &args); if (ret) return ret; @@ -173,10 +165,15 @@ static const struct udevice_id led_pwm_ids[] = { U_BOOT_DRIVER(led_pwm) = { .name = LEDS_PWM_DRIVER_NAME, .id = UCLASS_LED, - .of_match = led_pwm_ids, .ops = &led_pwm_ops, .priv_auto = sizeof(struct led_pwm_priv), - .bind = led_pwm_bind, .probe = led_pwm_probe, .of_to_plat = led_pwm_of_to_plat, }; + +U_BOOT_DRIVER(led_pwm_wrap) = { + .name = LEDS_PWM_DRIVER_NAME "_wrap", + .id = UCLASS_NOP, + .of_match = led_pwm_ids, + .bind = led_pwm_bind, +}; -- 2.30.2

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