May 2022 - U-Boot

[PATCH] RFC: nvedit: support doing one (extra) expansion of the value in "env set"
by Rasmus Villemoes 02 Feb '23

02 Feb '23

Currently, there's no way to fetch the value of an environment variable whose name is stored in some other variable, or generated from such - in non-working pseudo-code, ${${varname}} ${array${index}} This forces some scripts to needlessly duplicate logic and hardcode assumptions. For example, in an A/B scheme with three variables BOOT_ORDER # Either "A B" or "B A" depending on which slot was last updated BOOT_A_LEFT # 0..3 BOOT_B_LEFT # 0..3 when one needs to determine the slot to boot from, one does something like setenv found for slot in $BOOT_ORDER ; do if test "x$found" != "x" ; then # work around lack of break elif test "x$slot" = "xA" ; then if test $BOOT_A_LEFT -gt 0 ; then setexpr BOOT_A_LEFT $BOOT_A_LEFT - 1 setenv found A setenv bootargs ${bootargs_A} setenv ubivol ${ubivol_A} # more setup based on A fi elif test "x$slot" = "xB" ; then if test $BOOT_B_LEFT -gt 0 ; then # the same ... fi fi done This is already bad enough, but extending that to A/B/C is tedious and prone to copy-pastos. So this is an attempt at allowing one to do "env set -E var value1 value2" with the effect that, of course, normal variable expansion happens on the command line, the valueX are joined with spaces as usual, and then one more pass is done over that string replacing occurrences of ${foo}. The above would become setenv found for slot in $BOOT_ORDER ; do if test "x$found" != "x" ; then # work around lack of break else env set -E boot_left "\${BOOT_${slot}_LEFT}" if test $boot_left -gt 0 ; then setexpr BOOT_${slot}_LEFT $boot_left - 1 env set found $slot env set -E bootargs "\${bootargs_${slot}}" env set -E ubivol "\${ubivol_${slot}}" fi fi done I'm pleasantly surprised it was that easy to implement, but of course I'm cheating a bit (cli_simple_process_macros is only available if CONFIG_CMDLINE, though I think cli_simple.o could be unconditionally built and then link-time GC should get rid of the excess functions). This has been lightly tested in the sandbox. I'll add some proper unit tests, update the help texts and try to handle the Kconfig issue if this is something that might be accepted. Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- cmd/nvedit.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 81d94cd193..ff6ffcb674 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -224,7 +224,7 @@ DONE: */ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) { - int i, len; + int i, len, expand = 0; char *name, *value, *s; struct env_entry e, *ep; @@ -244,6 +244,9 @@ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) case 'f': /* force */ env_flag |= H_FORCE; break; + case 'E': + expand = 1; + break; default: return CMD_RET_USAGE; } @@ -287,6 +290,18 @@ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) if (s != value) *--s = '\0'; + if (expand) { + char *expanded = malloc(CONFIG_SYS_CBSIZE); + + if (expanded == NULL) { + printf("## Can't malloc %d bytes\n", CONFIG_SYS_CBSIZE); + free(value); + return 1; + } + cli_simple_process_macros(value, expanded); + free(value); + value = expanded; + } e.key = name; e.data = value; hsearch_r(e, ENV_ENTER, &ep, &env_htab, env_flag); -- 2.23.0

5 20

[PATCH] arm: kirkwood: Add nas440 board, Marvell 88SE6121 AHCI
by Hajo Noerenberg 30 Jan '23

30 Jan '23

This adds support for the Seagate Blackarmor NAS440 (4-bay Kirkwood NAS box). Does it make sense to include support for a 10+ year old device? If yes, I would be willing to discuss and finalize this patch. If no, it will be archived here for the public, which is fine with me. For the NAS440 is the something special that hard disk drives 1 and 2 are connected to a 88SE6121 SATA-II controller, which is connected via PCIe. Hard disk drives 3 and 4 are directly connected to the 88F6281 SoC. - Add NAS440 dtb and associated files/configs * Includes support for HD44780 front LCD * Includes support for device LEDs (via 74AHC164 shift register) - Add Marvell 88SE6121 AHCI support. Thanks to Pali Rohár for recently adding the necessary Kirkwood PCIe driver. It works :) - Tested with my NAS440 hardware: ETH/USB/SATA/AHCI-SCSI/GPIO/LCD/LEDs ok As far as I can see this fully implements the support for this board within U-Boot. With the Linux kernel however there are problems, the kernel AHCI driver fails with "failed to IDENTIFY" messages for the 88SE6121 drive ports, which I could not solve yet despite comparison with the GPL sources from Seagate. Note: I am collecting various information and patches for the family of Blackarmor NAS boards at https://github.com/hn/seagate-blackarmor-nas Hajo --- arch/arm/dts/kirkwood-blackarmor-nas440.dts | 166 +++++++++ board/Seagate/nas440/Kconfig | 12 + board/Seagate/nas440/MAINTAINERS | 7 + board/Seagate/nas440/Makefile | 7 + board/Seagate/nas440/kwbimage.cfg | 156 ++++++++ board/Seagate/nas440/nas440.c | 378 ++++++++++++++++++++ configs/nas440_defconfig | 89 +++++ drivers/ata/ahci-pci.c | 1 + include/configs/nas440.h | 50 +++ 9 files changed, 866 insertions(+) create mode 100644 arch/arm/dts/kirkwood-blackarmor-nas440.dts create mode 100644 board/Seagate/nas440/Kconfig create mode 100644 board/Seagate/nas440/MAINTAINERS create mode 100644 board/Seagate/nas440/Makefile create mode 100644 board/Seagate/nas440/kwbimage.cfg create mode 100644 board/Seagate/nas440/nas440.c create mode 100644 configs/nas440_defconfig create mode 100644 include/configs/nas440.h diff --git a/arch/arm/dts/kirkwood-blackarmor-nas440.dts b/arch/arm/dts/kirkwood-blackarmor-nas440.dts new file mode 100644 index 0000000000..60e3fe6f0d --- /dev/null +++ b/arch/arm/dts/kirkwood-blackarmor-nas440.dts @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for Seagate Blackarmor NAS440 + * + * Copyright (C) 2021 Hajo Noerenberg <www.github.com/hn> + * Copyright (C) 2015 Andreas Fischer <af(a)bantuX.org> + * Copyright (C) 2014 Evgeni Dobrev <evgeni(a)studio-punkt.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Seagate Blackarmor NAS440"; + compatible = "seagate,blackarmor-nas440","marvell,kirkwood-88f6281", + "marvell,kirkwood"; + + memory { /* 256 MB */ + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO1-16 is MPP48 */ + }; + + gpio_keys { + compatible = "gpio-keys"; + + reset { + label = "Reset"; + linux,code = <KEY_POWER>; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + + button { + label = "Power"; + linux,code = <KEY_SLEEP>; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; /* GPIO1-17 is MPP49 */ + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_power_socsata>; + pinctrl-names = "default"; + + socsata_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SoC SATA Power"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* + * Serial port routed to connector CN4 + * + * pin 1 - TX (CPU's TX) + * pin 4 - RX (CPU's RX) + * pin 6 - GND + */ +&uart0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-0 = <&pmx_button_reset &pmx_button_power>; + pinctrl-names = "default"; + + pmx_act_sata0: pmx-act-sata0 { + marvell,pins = "mpp15"; + marvell,function = "sata0"; + }; + + pmx_act_sata1: pmx-act-sata1 { + marvell,pins = "mpp16"; + marvell,function = "sata1"; + }; + + pmx_power_socsata: pmx-power-socsata { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_button_power: pmx-button-power { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + adt7473: thermal@2e { + compatible = "adi,adt7473"; + reg = <0x2e>; + }; +}; + +&nand { + status = "okay"; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@8 { + reg = <8>; + }; + ethphy1: ethernet-phy@9 { + reg = <9>; + }; +}; + +&eth0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <&ethphy0>; + }; +}; + +&eth1 { + status = "okay"; + + ethernet1-port@0 { + phy-handle = <&ethphy1>; + }; +}; diff --git a/board/Seagate/nas440/Kconfig b/board/Seagate/nas440/Kconfig new file mode 100644 index 0000000000..3f93d75cd4 --- /dev/null +++ b/board/Seagate/nas440/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NAS440 + +config SYS_BOARD + default "nas440" + +config SYS_VENDOR + default "Seagate" + +config SYS_CONFIG_NAME + default "nas440" + +endif diff --git a/board/Seagate/nas440/MAINTAINERS b/board/Seagate/nas440/MAINTAINERS new file mode 100644 index 0000000000..dcea1316c5 --- /dev/null +++ b/board/Seagate/nas440/MAINTAINERS @@ -0,0 +1,7 @@ +NAS440 BOARD +M: Hajo Noerenberg <hajo-uboot(a)noerenberg.de> +S: Maintained +F: board/Seagate/nas440/ +F: include/configs/nas440.h +F: configs/nas440_defconfig +F: arch/arm/dts/kirkwood-blackarmor-nas440.dts diff --git a/board/Seagate/nas440/Makefile b/board/Seagate/nas440/Makefile new file mode 100644 index 0000000000..2a3ef746d3 --- /dev/null +++ b/board/Seagate/nas440/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Evgeni Dobrev <evgeni(a)studio-punkt.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := nas440.o diff --git a/board/Seagate/nas440/kwbimage.cfg b/board/Seagate/nas440/kwbimage.cfg new file mode 100644 index 0000000000..e71da11694 --- /dev/null +++ b/board/Seagate/nas440/kwbimage.cfg @@ -0,0 +1,156 @@ +# +# Copyright (C) 2021 Hajo Noerenberg <hajo-uboot(a)noerenberg.de> +# +# Based on nas220/kwbimage.cfg originally written by +# Evgeni Dobrev <evgeni(a)studio-punkt.com> +# +# Based on sheevaplug/kwbimage.cfg originally written by +# Prafulla Wadaskar <prafulla(a)marvell.com> +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.kwbimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0200 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100E0 0x1B1B1B9B + +DATA 0xFFD20134 0xBBBBBBBB +DATA 0xFFD20138 0x00BBBBBB + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000C30 # DDR Configuration register +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x39543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000833 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000000C # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000042 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 0 +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 +DATA 0xFFD0147C 0x00008552 + +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000F80F # CPU ODT Control + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 + diff --git a/board/Seagate/nas440/nas440.c b/board/Seagate/nas440/nas440.c new file mode 100644 index 0000000000..43a08e61bf --- /dev/null +++ b/board/Seagate/nas440/nas440.c @@ -0,0 +1,378 @@ +/* + * Copyright (C) 2022 Hajo Noerenberg <hajo-uboot(a)noerenberg.de> + * + * Based on nas220.c originally written by + * Evgeni Dobrev <evgeni(a)studio-punkt.com> + * + * Based on sheevaplug.c originally written by + * Prafulla Wadaskar <prafulla(a)marvell.com> + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <init.h> +#include <netdev.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include <asm/global_data.h> +#include <asm/mach-types.h> +#include <linux/bitops.h> +#include <bootstage.h> +#include <linux/delay.h> +#include <asm/arch/gpio.h> +#include <version.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * GPIO pin names, input/output direction and default values + * + * NAS440_GPIO_BUTTON_LCD_LOWER, NAS440_GPIO_BUTTON_LCD_UPPER + * Buttons next to LC display, LOW if pressed + * + * NAS440_GPIO_BUTTON_POWER + * Power button at front of case, LOW if pressed + * + * NAS440_GPIO_BUTTON_RESET + * Reset button at back of case, LOW if pressed + * + * NAS440_GPIO_LCD_HD44780_* + * HD44780-compatible LC display, control via 8bit parallel data transfer + * + * NAS440_GPIO_LED_74AHC164_* + * Control front panel LEDs via 74AHC164 8bit shift register + * + * NAS440_GPIO_SOCSATA_POWER + * 12V Power for SoC SATA ports (NAS drives 3 and 4) + * + * NAS440_GPIO_BOARD_POWER + * Shutdown board if LOW + * + */ + +#define NAS440_GPIO_LCD_HD44780_BACKLIGHT 7 +#define NAS440_GPIO_LED_74AHC164_DATA 12 +#define NAS440_GPIO_LED_74AHC164_CLK 13 +#define NAS440_GPIO_SOCSATA_POWER 28 +#define NAS440_GPIO_BUTTON_RESET 29 +#define NAS440_GPIO_BUTTON_LCD_LOWER 34 +#define NAS440_GPIO_LCD_HD44780_RS 35 +#define NAS440_GPIO_LCD_HD44780_D0 36 +#define NAS440_GPIO_LCD_HD44780_D1 37 +#define NAS440_GPIO_LCD_HD44780_D2 38 +#define NAS440_GPIO_LCD_HD44780_D3 39 +#define NAS440_GPIO_LCD_HD44780_D4 40 +#define NAS440_GPIO_LCD_HD44780_D5 41 +#define NAS440_GPIO_LCD_HD44780_D6 42 +#define NAS440_GPIO_LCD_HD44780_D7 43 +#define NAS440_GPIO_LCD_HD44780_RW 44 +#define NAS440_GPIO_LCD_HD44780_E 45 +#define NAS440_GPIO_BUTTON_LCD_UPPER 47 +#define NAS440_GPIO_BOARD_POWER 48 +#define NAS440_GPIO_BUTTON_POWER 49 + +/* + * GPIO output enable, pins 0-31 to LOW, pins 31-49 to HIGH config register + */ +#define NAS440_GE_OE_LOW (~(BIT(NAS440_GPIO_LCD_HD44780_BACKLIGHT) \ + | BIT(NAS440_GPIO_LED_74AHC164_DATA) \ + | BIT(NAS440_GPIO_LED_74AHC164_CLK) \ + | BIT(NAS440_GPIO_SOCSATA_POWER))) +#define NAS440_GE_OE_HIGH (~(BIT_MASK(NAS440_GPIO_BOARD_POWER) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_RS) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D0) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D1) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D2) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D3) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D4) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D5) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D6) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_D7) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_RW) \ + | BIT_MASK(NAS440_GPIO_LCD_HD44780_E))) + +/* + * GPIO output default values + */ +#define NAS440_GE_OE_VAL_LOW BIT(NAS440_GPIO_LCD_HD44780_BACKLIGHT) + +#define NAS440_GE_OE_VAL_HIGH BIT_MASK(NAS440_GPIO_BOARD_POWER) + +int board_early_init_f(void) +{ + /* + * default gpio configuration + */ + mvebu_config_gpio(NAS440_GE_OE_VAL_LOW, NAS440_GE_OE_VAL_HIGH, + NAS440_GE_OE_LOW, NAS440_GE_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* NAS440_GPIO_LCD_HD44780_BACKLIGHT */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, /* NAS440_GPIO_LED_74AHC164_DATA */ + MPP13_GPIO, /* NAS440_GPIO_LED_74AHC164_CLK */ + MPP14_SATA1_PRESENTn, + MPP15_SATA0_ACTn, + MPP16_SATA1_ACTn, + MPP17_SATA0_PRESENTn, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, /* GbE Port1, RGMII mode (12 pins GE1_0-7, GE1_10-13) */ + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, /* NAS440_GPIO_SOCSATA_POWER */ + MPP29_GPIO, /* NAS440_GPIO_BUTTON_RESET */ + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, /* NAS440_GPIO_BUTTON_LCD_LOWER */ + MPP35_GPIO, /* NAS440_GPIO_LCD_HD44780_RS */ + MPP36_GPIO, /* NAS440_GPIO_LCD_HD44780_D0 */ + MPP37_GPIO, /* NAS440_GPIO_LCD_HD44780_D1 */ + MPP38_GPIO, /* NAS440_GPIO_LCD_HD44780_D2 */ + MPP39_GPIO, /* NAS440_GPIO_LCD_HD44780_D3 */ + MPP40_GPIO, /* NAS440_GPIO_LCD_HD44780_D4 */ + MPP41_GPIO, /* NAS440_GPIO_LCD_HD44780_D5 */ + MPP42_GPIO, /* NAS440_GPIO_LCD_HD44780_D6 */ + MPP43_GPIO, /* NAS440_GPIO_LCD_HD44780_D7 */ + MPP44_GPIO, /* NAS440_GPIO_LCD_HD44780_RW */ + MPP45_GPIO, /* NAS440_GPIO_LCD_HD44780_E */ + MPP46_GPIO, + MPP47_GPIO, /* NAS440_GPIO_BUTTON_LCD_UPPER */ + MPP48_GPIO, /* NAS440_GPIO_BOARD_POWER */ + MPP49_GPIO, /* NAS440_GPIO_BUTTON_POWER */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +/* HD44780 pins, data bits first, backlight last */ +static int hd44780_pins[12] = { + NAS440_GPIO_LCD_HD44780_D0, + NAS440_GPIO_LCD_HD44780_D1, + NAS440_GPIO_LCD_HD44780_D2, + NAS440_GPIO_LCD_HD44780_D3, + NAS440_GPIO_LCD_HD44780_D4, + NAS440_GPIO_LCD_HD44780_D5, + NAS440_GPIO_LCD_HD44780_D6, + NAS440_GPIO_LCD_HD44780_D7, + NAS440_GPIO_LCD_HD44780_E, + NAS440_GPIO_LCD_HD44780_RW, + NAS440_GPIO_LCD_HD44780_RS, + NAS440_GPIO_LCD_HD44780_BACKLIGHT +}; + +#define HD44780_NUM_COL 16 +#define HD44780_BUF_COL 40 +#define HD44780_NUM_ROW 2 + +#define HD44780_PIN_NUM (sizeof(hd44780_pins)/sizeof(int)) + +/* + * HD44780 LCD display commands - adapted from hd44780.h by Joerg Wunsch + * + * ---------------------------------------------------------------------------- + * "THE BEER-WARE LICENSE" (Revision 42): + * <joerg(a)FreeBSD.ORG> wrote this file. As long as you retain this notice you + * can do whatever you want with this stuff. If we meet some day, and you think + * this stuff is worth it, you can buy me a beer in return. Joerg Wunsch + * ---------------------------------------------------------------------------- + */ + +#define HD44780_CMD_CLR \ + 0x01 +#define HD44780_CMD_HOME \ + 0x02 +#define HD44780_CMD_ENTMODE(inc, shift) \ + (0x04 | ((inc)? 0x02: 0) | ((shift)? 1: 0)) +#define HD44780_CMD_DISPCTL(disp, cursor, blink) \ + (0x08 | ((disp)? 0x04: 0) | ((cursor)? 0x02: 0) | ((blink)? 1: 0)) +#define HD44780_CMD_SHIFT(shift, right) \ + (0x10 | ((shift)? 0x08: 0) | ((right)? 0x04: 0)) +#define HD44780_CMD_FNSET(if8bit, twoline, font5x10) \ + (0x20 | ((if8bit)? 0x10: 0) | ((twoline)? 0x08: 0) | \ + ((font5x10)? 0x04: 0)) +#define HD44780_CMD_CGADDR(addr) \ + (0x40 | ((addr) & 0x3f)) +#define HD44780_CMD_DDADDR(addr) \ + (0x80 | ((addr) & 0x7f)) + +static void lcd_send(unsigned int val, int mode) +{ + udelay(1); + kw_gpio_set_value(NAS440_GPIO_LCD_HD44780_RS, mode); + udelay(1); + + kw_gpio_set_value(NAS440_GPIO_LCD_HD44780_E, 0); + for (int i=0; i<8; i++) { + kw_gpio_set_value(hd44780_pins[i], (val&(1<<i))>>i ); + } + udelay(1); + kw_gpio_set_value(NAS440_GPIO_LCD_HD44780_E, 1); + udelay(1); + kw_gpio_set_value(NAS440_GPIO_LCD_HD44780_E, 0); + udelay(50); +} + +void lcd_init(void) +{ + for (int i=0; i<HD44780_PIN_NUM; i++) { + kw_gpio_set_valid(hd44780_pins[i], GPIO_OUTPUT_OK); + kw_gpio_direction_output(hd44780_pins[i], i == (HD44780_PIN_NUM-1)); + } + + lcd_send(HD44780_CMD_FNSET(1, 1, 0), 0); + udelay(50); + lcd_send(HD44780_CMD_FNSET(1, 1, 0), 0); + udelay(50); + lcd_send(HD44780_CMD_FNSET(1, 1, 0), 0); + udelay(50); + lcd_send(HD44780_CMD_DISPCTL(1, 0, 0), 0); + udelay(50); + lcd_send(HD44780_CMD_CLR, 0); + udelay(50); + lcd_send(HD44780_CMD_ENTMODE(1, 0), 0); + + udelay(2000); +} + +void lcd_row(int row, char *buf) +{ + int p = 0; + + if (row >= HD44780_NUM_ROW) { + return; + } + + lcd_send(HD44780_CMD_DDADDR(HD44780_BUF_COL * row + 0), 0); + for (int i=0; i<HD44780_NUM_COL; i++) { + if (buf[i] == 0) { + p++; + } + lcd_send(p ? 32 : buf[i], 1); + } +} + +enum led_disk { + LED_DSK_OFF, + LED_DSK_RED + /* LED_DSK_GREEN disk activity led is controlled directly by the hardware */ +}; + +enum led_system { + LED_SYS_OFF, + LED_SYS_BLUE, + LED_SYS_RED +}; + +void led_init(void) +{ + kw_gpio_set_valid(NAS440_GPIO_LED_74AHC164_DATA, GPIO_OUTPUT_OK); + kw_gpio_direction_output(NAS440_GPIO_LED_74AHC164_DATA, 0); + kw_gpio_set_valid(NAS440_GPIO_LED_74AHC164_CLK, GPIO_OUTPUT_OK); + kw_gpio_direction_output(NAS440_GPIO_LED_74AHC164_CLK, 0); +} + +void led_set(enum led_disk disk1, enum led_disk disk2, enum led_disk disk3, + enum led_disk disk4, enum led_system front1 ) +{ + int ledbits = (0x81 | ((front1==LED_SYS_RED)? 0x08 : 0) | ((front1==LED_SYS_BLUE)? 0x04 : 0) \ + | ((disk1==LED_DSK_RED)? 0 : 0x02) | ((disk2==LED_DSK_RED)? 0 : 0x40) \ + | ((disk3==LED_DSK_RED)? 0 : 0x20) | ((disk4==LED_DSK_RED)? 0 : 0x10)); + + for (int i=0; i<8; i++) { + kw_gpio_set_value(NAS440_GPIO_LED_74AHC164_DATA, (ledbits >> i) & 1); + udelay(1); + kw_gpio_set_value(NAS440_GPIO_LED_74AHC164_CLK, 1); + kw_gpio_set_value(NAS440_GPIO_LED_74AHC164_CLK, 0); + } +} + +/* factory firmware delays hard disk spinup, presumably to avoid power peaks */ +void delay_hdd_spinup(void) +{ + lcd_row(1, "Delay HDD spinup"); + + for (int i = 0; i<2500; i++) { + udelay(1000); + } + + kw_gpio_set_valid(NAS440_GPIO_SOCSATA_POWER, GPIO_OUTPUT_OK); + kw_gpio_direction_output(NAS440_GPIO_SOCSATA_POWER, 1); +} + +#if CONFIG_IS_ENABLED(BOOTSTAGE) +void show_boot_progress(int val) +{ + switch (val) { +/* 0123456789abcdef */ + case BOOTSTAGE_ID_BOARD_INIT_DONE: + lcd_row(1, "Board init done"); + break; + case BOOTSTAGE_ID_USB_START: + lcd_row(1, "Init USB"); + break; + case BOOTSTAGE_ID_ETH_START: + lcd_row(1, "Init ethernet"); + break; + case BOOTSTAGE_ID_MAIN_LOOP: + lcd_row(1, "Wait for input"); + break; + case BOOTSTAGE_ID_RUN_OS: + lcd_row(1, "Starting Linux"); + break; + default: + if (val < 0) /* error */ + lcd_row(1, "Error"); + break; + } +} +#endif + +int board_eth_init(struct bd_info *bis) +{ + return cpu_eth_init(bis); +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_DB88F6281_BP; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + led_init(); + led_set(LED_DSK_OFF, LED_DSK_OFF, LED_DSK_OFF, LED_DSK_OFF, LED_SYS_BLUE); + + lcd_init(); + lcd_row(0, U_BOOT_VERSION ""); + + delay_hdd_spinup(); + + return 0; +} diff --git a/configs/nas440_defconfig b/configs/nas440_defconfig new file mode 100644 index 0000000000..74faf1a24b --- /dev/null +++ b/configs/nas440_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_SYS_KWD_CONFIG="board/Seagate/nas440/kwbimage.cfg" +CONFIG_SYS_TEXT_BASE=0x600000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_NAS440=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xA0000 +CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas440" +CONFIG_IDENT_STRING="\nNAS 440" +# CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="pci enum; " +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="nas440> " +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SATA=y +CONFIG_CMD_PCI=y +CONFIG_CMD_DM=y +CONFIG_CMD_SCSI=y +CONFIG_CMD_NAND=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xa0000@0x0(uboot),0x010000@0xa0000(env),0x500000@0xc0000(uimage),0x1a40000@0x5c0000(rootfs)" +CONFIG_CMD_UBI=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_PARTITION_UUIDS is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SYS_ATA_STRIDE=4 +CONFIG_SYS_ATA_DATA_OFFSET=0x100 +CONFIG_SYS_ATA_REG_OFFSET=0x100 +CONFIG_SYS_ATA_ALT_OFFSET=0x100 +CONFIG_KIRKWOOD_GPIO=y +CONFIG_MVEBU_GPIO=y +CONFIG_GPIO_EXTRA_HEADER=y +CONFIG_DM_GPIO=y +CONFIG_CMD_GPIO=y +CONFIG_GPIO=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_PHY_MARVELL=y +CONFIG_DM_ETH=y +CONFIG_MVGBE=y +CONFIG_MII=y +CONFIG_SATA_MV=y +CONFIG_SYS_SATA_MAX_DEVICE=2 +CONFIG_DM_RTC=y +CONFIG_RTC_MV=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y + +CONFIG_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_MVEBU=y +CONFIG_AHCI_PCI=y + +CONFIG_SCSI=y +CONFIG_SCSI_AHCI=y +CONFIG_DM_SCSI=y diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c index b1d231e0f9..af7e97dc4a 100644 --- a/drivers/ata/ahci-pci.c +++ b/drivers/ata/ahci-pci.c @@ -38,6 +38,7 @@ U_BOOT_DRIVER(ahci_pci) = { static struct pci_device_id ahci_pci_supported[] = { { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) }, { PCI_DEVICE(0x1b21, 0x0611) }, + { PCI_DEVICE(0x11ab, 0x6121) }, {}, }; diff --git a/include/configs/nas440.h b/include/configs/nas440.h new file mode 100644 index 0000000000..58e6afb2c3 --- /dev/null +++ b/include/configs/nas440.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2022 Hajo Noerenberg <hajo-uboot(a)noerenberg.de> + * + * based on work from: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_NAS440_H +#define _CONFIG_NAS440_H + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ + +#include "mv-common.h" + +/* + * Default environment variables + */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0"\ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ + "autostart=no\0"\ + "autoload=no\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_MVGBE +#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ +#define CONFIG_PHY_BASE_ADR 8 +#ifdef CONFIG_RESET_PHY_R +#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */ +#endif +#endif /* CONFIG_MVGBE */ + +/* + * SATA driver configuration + */ +#define CONFIG_LBA48 +#define CONFIG_SYS_64BIT_LBA + +#endif /* _CONFIG_NAS440_H */ -- 2.20.1

3 11

linksys wrt1900acs v2 boot problem
by Dilyan Lazarov 07 Jan '23

07 Jan '23

Hi, I have a problem with my linksys wrt1900acs. My main question is this a hardware problem or software problem? Is it possible to address? I have started researching and have tried with "kwboot" under Windows VM - Ubuntu 20 - Linux but I have a problem with usb serial connection. I have tried several things but I understand that it isn't possible to start USB to Serial on a Windows VM. I will expect your response. Thank you in advance. All the best Dilyan I see the following Log from U-Boot with PuTTy under Windows 10: BootROM - 1.73 Booting from NAND flash General initialization - Version: 1.0.0 Detected Device ID 6820 High speed PHY - Version: 2.0 Init RD NAS topology Serdes Lane 3 is USB3 Serdes Lane 4 is SGMII board SerDes lanes topology details: | Lane # | Speed | Type | -------------------------------- | 0 | 06 | SATA0 | | 1 | 05 | PCIe0 | | 2 | 06 | SATA1 | | 3 | 05 | USB3 HOST1 | | 4 | 05 | PCIe1 | | 5 | 00 | SGMII2 | -------------------------------- :** Link is Gen1, check the EP capability PCIe, Idx 0: Link upgraded to Gen2 based on client cpabilities :** Link is Gen1, check the EP capability PCIe, Idx 1: remains Gen1 High speed PHY - Ended Successfully DDR3 Training Sequence - Ver TIP-1.26.0 mvSysEnvGetTopologyUpdateInfo: TWSI Read failed WL Supp: IF 0 busId 1 Failed ! WL Supp: IF 0 failed ddr3TipDynamicWriteLevelingSupp failure ******** DRAM initialization Failed (res 0x1) ******** DDR3 run algorithm - FAILED 0x1 DDR3 Training Sequence - FAILED ********** DRAM initialization failed! ******** -- Dilyan

3 2

kwboot : bug when board stops acking
by SC 06 Jan '23

06 Jan '23

Hi list, I think there's a bug in kwboot. I have a faulty board that stops acking xmodem frames after a certain number of packets and kwboot instead of exiting continues to send frames up to 100%. With the one second retry timer it's very long! More than 2 hours :-( The bug is in the kwboot_xm_sendblock() fonction : https://gitlab.denx.de/u-boot/u-boot/blob/master/tools/kwboot.c#L375 kwboot_tty_recv detects the timeout but the return value is based on the last character received (line 403) The variable c is not initialized so if it keeps the previous value which is ACK => rc=0 => infinite loop There are several ways to fix the bug: * Surround the "switch(c)" with a test: if ( !((rc == -1) && (errno == ETIMEDOUT)) ) { rc = -1; switch (c) { case ACK: rc = 0; break; case NAK: errno = EBADMSG; break; case CAN: errno = ECANCELED; break; default: errno = EPROTO; break; } } return rc; * In the case of a TIMEOUT set c to a specific value and add the case in the switch Do you agree with my diagnosis? What is the best solution to fix this bug? Should I provide a patch? Thank you, Stephane

3 2

Netgear RN102 U-Boot Nand Driver Modification
by Abdus Rainey 06 Jan '23

06 Jan '23

I have recently modded a Netgear RN102 NAND flash from 128 MB to 4096 MB (Samsung k9gbg08u0a) but i have a problem with NAND initialization. I can boot with kwboot which is unique for Armada CPU's. Here is my log from kwboot with my stock mtd0: root@whitepawnxeon:/home/jigsaw/Downloads# kwboot -t -B 115200 /dev/ttyUSB0 -b mtd0stockuboot.img -p Sending boot message. Please reboot the target...- Sending boot image... 0 % [......................................................................] 0 % [......................................................................] 1 % [......................................................................] 1 % [......................................................................] 2 % [......................................................................] 2 % [......................................................................] 3 % [......................................................................] 3 % [......................................................................] 4 % [......................................................................] 5 % [......... General initialization - Version: 1.0.0 High speed PHY - Version: 2.1.4 (COM-PHY-V20) Update PEX Device ID 0x6710 High speed PHY - Ended Successfully 0000 DDR3 Training Sequence - Ver 5.7.1 DDR3 Training Sequence - Run without PBS. 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[......................................................................] 94 % [......................................................................] 95 % [......................................................................] 95 % [......................................................................] 96 % [......................................................................] 96 % [......................................................................] 97 % [......................................................................] 97 % [......................................................................] 98 % [......................................................................] 99 % [......................................................................] 99 % [......................................] [Type Ctrl-\ + c to quit] __ __ _ _ | \/ | __ _ _ ____ _____| | | | |\/| |/ _` | '__\ \ / / _ \ | | | | | | (_| | | \ V / __/ | | |_| |_|\__,_|_| \_/ \___|_|_| _ _ ____ _ | | | | | __ ) ___ ___ | |_ | | | |___| _ \ / _ \ / _ \| __| | |_| |___| |_) | (_) | (_) | |_ \___/ |____/ \___/ \___/ \__| ** LOADER ** U-Boot 2011.12-gec25d27-dirty (Oct 26 2015 - 16:53:05) Marvell version: v2011.12 2014_T2.0p1 06/23/2015 ReadyNAS-102 V2.0 Board: DB-88F6710-BP SoC: MV6710 A1 CPU: Marvell PJ4B v7 UP (Rev 1) LE CPU @ 1200 [MHz] L2 @ 600 [MHz] TClock @ 200 [MHz] DDR @ 600 [MHz] DDR 16Bit Width, FastPath Memory Access DRAM: 512 MiB Map: Code: 0x1feef000:0x1ff9ef34 BSS: 0x1ffef0a0 Stack: 0x1f9eeef8 Heap: 0x1f9ef000:0x1feef000 NAND: (ID 0xd7ec) nand_get_flash_type: second ID read did not match ac,d7 against ec,52 No NAND device found!!! 0 MiB MMC: MRVL_MMC: 0 *** Warning - readenv() failed, using default environment Initialize and scan all PCI interfaces PEX unit.port(active IF[-first bus]): ------------------------------------------ PEX 0: Root Complex Interface, Detected Link X1, GEN 2.0 PEX 1: Root Complex Interface, Detected Link X1, GEN 2.0 FPU not initialized USB 0: Host Mode USB 1: Host Mode Shutting down unused interfaces: GBE0 SDIO AUDIO TDM Modules/Interfaces Detected: RGMII1 Phy PEX0 (Lane 0) PEX1 (Lane 1) SATA0 (Lane 2) SATA1 (Lane 3) Net: , egiga1 [PRIME] Detect MVT/MP board... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data Power On! Updating env to v3... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data raise: Signal # 8 caught raise: Signal # 8 caught __ __ _ _ | \/ | __ _ _ ____ _____| | | | |\/| |/ _` | '__\ \ / / _ \ | | | | | | (_| | | \ V / __/ | | |_| |_|\__,_|_| \_/ \___|_|_| _ _ ____ _ | | | | | __ ) ___ ___ | |_ | | | |___| _ \ / _ \ / _ \| __| | |_| |___| |_) | (_) | (_) | |_ \___/ |____/ \___/ \___/ \__| ** LOADER ** U-Boot 2011.12-gec25d27-dirty (Oct 26 2015 - 16:53:05) Marvell version: v2011.12 2014_T2.0p1 06/23/2015 ReadyNAS-102 V2.0 Board: DB-88F6710-BP SoC: MV6710 A1 CPU: Marvell PJ4B v7 UP (Rev 1) LE CPU @ 1200 [MHz] L2 @ 600 [MHz] TClock @ 200 [MHz] DDR @ 600 [MHz] DDR 16Bit Width, FastPath Memory Access DRAM: 512 MiB Map: Code: 0x1feef000:0x1ff9ef34 BSS: 0x1ffef0a0 Stack: 0x1f9eeef8 Heap: 0x1f9ef000:0x1feef000 NAND: (ID 0xd7ec) nand_get_flash_type: second ID read did not match ac,d7 against ec,53 No NAND device found!!! 0 MiB MMC: MRVL_MMC: 0 *** Warning - readenv() failed, using default environment Initialize and scan all PCI interfaces PEX unit.port(active IF[-first bus]): ------------------------------------------ PEX 0: Root Complex Interface, Detected Link X1, GEN 2.0 PEX 1: Root Complex Interface, Detected Link X1, GEN 2.0 FPU not initialized USB 0: Host Mode USB 1: Host Mode Shutting down unused interfaces: GBE0 SDIO AUDIO TDM Modules/Interfaces Detected: RGMII1 Phy PEX0 (Lane 0) PEX1 (Lane 1) SATA0 (Lane 2) SATA1 (Lane 3) Net: , egiga1 [PRIME] Detect MVT/MP board... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data Power On! Updating env to v3... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data raise: Signal # 8 caught raise: Signal # 8 caught __ __ _ _ | \/ | __ _ _ ____ _____| | | | |\/| |/ _` | '__\ \ / / _ \ | | | | | | (_| | | \ V / __/ | | |_| |_|\__,_|_| \_/ \___|_|_| _ _ ____ _ | | | | | __ ) ___ ___ | |_ | | | |___| _ \ / _ \ / _ \| __| | |_| |___| |_) | (_) | (_) | |_ \___/ |____/ \___/ \___/ \__| ** LOADER ** U-Boot 2011.12-gec25d27-dirty (Oct 26 2015 - 16:53:05) Marvell version: v2011.12 2014_T2.0p1 06/23/2015 ReadyNAS-102 V2.0 Board: DB-88F6710-BP SoC: MV6710 A1 CPU: Marvell PJ4B v7 UP (Rev 1) LE CPU @ 1200 [MHz] L2 @ 600 [MHz] TClock @ 200 [MHz] DDR @ 600 [MHz] DDR 16Bit Width, FastPath Memory Access DRAM: 512 MiB Map: Code: 0x1feef000:0x1ff9ef34 BSS: 0x1ffef0a0 Stack: 0x1f9eeef8 Heap: 0x1f9ef000:0x1feef000 NAND: (ID 0xd7ec) nand_get_flash_type: second ID read did not match ac,d7 against ec,53 No NAND device found!!! 0 MiB MMC: MRVL_MMC: 0 *** Warning - readenv() failed, using default environment Initialize and scan all PCI interfaces PEX unit.port(active IF[-first bus]): ------------------------------------------ PEX 0: Root Complex Interface, Detected Link X1, GEN 2.0 PEX 1: Root Complex Interface, Detected Link X1, GEN 2.0 FPU not initialized USB 0: Host Mode USB 1: Host Mode Shutting down unused interfaces: GBE0 SDIO AUDIO TDM Modules/Interfaces Detected: RGMII1 Phy PEX0 (Lane 0) PEX1 (Lane 1) SATA0 (Lane 2) SATA1 (Lane 3) Net: , egiga1 [PRIME] As you can see u-boot sees device id and manufacturer id but cannot recognize it.My stock u-boot is very old and i get u-boot source code from Netgear GPL.(ReadyNASOS_V6.6.0_WW_src.zip) In here https://forum.doozan.com/read.php?2,106589,108204#msg-108204 you can see my whole story about this device. Can someone suggest any solution?

2 1

[RESEND PATCH v2 0/3] net: fm: Add support for loading firmware from filesystem
by Sean Anderson 28 Nov '22

28 Nov '22

This adds support for loading Fman firmware from a filesystem using the firmware loader subsystem. It was originally part of [1], but has been split off because it is conceptually separate. [1] https://lore.kernel.org/u-boot/20220324182306.2037094-1-sean.anderson@seco.… Changes in v2: - Split series into two Sean Anderson (3): misc: fs_loader: Add function to get the chosen loader net: fm: Add firmware name parameter net: fm: Support loading firmware from a filesystem arch/arm/mach-k3/common.c | 2 +- arch/arm/mach-omap2/boot-common.c | 2 +- drivers/fpga/socfpga_arria10.c | 24 ++----------------- drivers/misc/fs_loader.c | 27 +++++++++++++++++++++ drivers/net/fm/fm.c | 40 +++++++++++++++++++++++++++---- drivers/net/fm/fm.h | 2 +- drivers/net/fm/init.c | 4 ++-- drivers/qe/Kconfig | 4 ++++ include/fs_loader.h | 12 ++++++++++ 9 files changed, 86 insertions(+), 31 deletions(-) -- 2.35.1.1320.gc452695387.dirty

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Nokia RX51 U-Boot USB support updates?
by Tom Rini 27 Nov '22

27 Nov '22

Hey all, So, the DM_USB migration deadline issue has been addressed by the series here: https://patchwork.ozlabs.org/project/uboot/list/?series=252793&state=* which splits out host and gadget support from the CONFIG_USB symbol itself. The migration deadline was for host support, and as noted, N900 is gadget only. That particular issue is resolved. But investigating that issue lead me to figure out some other problems, that I do need someone to say how will be addressed. Now that the other board removal series has been applied, and then with: https://patchwork.ozlabs.org/project/uboot/patch/20210708014348.4010-1-trin… also applied (for which the maintainer is happy to take), this brings N900 as the last and only user of the "old" musb driver (the "new" musb driver is now almost 9 years old) and also the last and only user of the usbtty driver. I suspect that moving to the "new" MUSB driver, for gadget only, and with that enabling DM_USB_GADGET should be a mechanical affair, so long as you can fit within the space constraints of the platform. I'm not immediately sure how hard it will be to update usbtty.c to modern gadget APIs. If there are size problems, then, well, we need solutions proposed (it's possible that some of the usb-uclass.c code is host-only and needs moving, but that likely won't stop gadget from needing it for gadget related information, to bring up a specific example). It's also likely that the MUSB support needs a little further clean-up for supporting building as gadget-only when there's some common code under a host-only check. What I would like is for someone to step forward and say they'll pick up this work. Is there an immediate deadline? No. I don't think that would be helpful. I'm not going to dictate how long it takes for someone to do the work, that's for the person doing the work to say how long they think it'll take. Thanks all! -- Tom

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[PATCH 1/2] spi: fsl_qspi: Add support for i.MX7ULP
by Ye Li 09 Nov '22

09 Nov '22

Add compatible string and driver data for i.MX7ULP. Meanwhile, the address set to SFA1AD/SFA2AD/SFB1AD/SFB2AD should align with 1KB, because the lowest 10 bits are reserved by the registers definition. For i.MX7ULP which has only 128Bytes AHB buffer, must align it when setting the registers and selecting cs. Signed-off-by: Ye Li <ye.li(a)nxp.com> Reviewed-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> Reviewed-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- drivers/spi/fsl_qspi.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index e715f98..d9f531a 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -231,6 +231,15 @@ static const struct fsl_qspi_devtype_data imx6ul_data = { .little_endian = true, }; +static const struct fsl_qspi_devtype_data imx7ulp_data = { + .rxfifo = SZ_64, + .txfifo = SZ_64, + .ahb_buf_size = SZ_128, + .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | + QUADSPI_QUIRK_USE_TDH_SETTING, + .little_endian = true, +}; + static const struct fsl_qspi_devtype_data ls1021a_data = { .rxfifo = SZ_128, .txfifo = SZ_64, @@ -485,7 +494,7 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave) static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op) { memcpy_fromio(op->data.buf.in, - q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size, + q->ahb_addr + q->selected * ALIGN(q->devtype_data->ahb_buf_size, 0x400), op->data.nbytes); } @@ -589,7 +598,7 @@ static int fsl_qspi_exec_op(struct spi_slave *slave, addr_offset = q->memmap_phy; qspi_writel(q, - q->selected * q->devtype_data->ahb_buf_size + addr_offset, + q->selected * ALIGN(q->devtype_data->ahb_buf_size, 0x400) + addr_offset, base + QUADSPI_SFAR); qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) | @@ -695,13 +704,13 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q) * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD, * SFB2AD accordingly. */ - qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) + addr_offset, base + QUADSPI_SFA1AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 2 + addr_offset, base + QUADSPI_SFA2AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 3 + addr_offset, base + QUADSPI_SFB1AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 4 + addr_offset, base + QUADSPI_SFB2AD); q->selected = -1; @@ -799,6 +808,7 @@ static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, }, { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, }, { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, }, + { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, }, { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, }, { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, }, { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, }, -- 2.7.4

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[PATCH v1] spi: nuvoton: add NPCM PSPI controller driver
by Jim Liu 27 Oct '22

27 Oct '22

Add Nuvoton NPCM BMC Peripheral SPI controller driver. NPCM750 include two general-purpose SPI interface. Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/npcm_pspi.c | 226 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 232 insertions(+) create mode 100644 drivers/spi/npcm_pspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1e515cb2b..4e4e05f849 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -289,6 +289,11 @@ config NPCM_FIU_SPI This enables support for the Flash Interface Unit SPI controller in master mode. +config NPCM_PSPI + bool "PSPI driver for Nuvoton NPCM SoC" + help + PSPI driver for NPCM SoC + config NXP_FSPI bool "NXP FlexSPI driver" depends on SPI_MEM diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06e81b465b..1b843636bc 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o +obj-$(CONFIG_NPCM_PSPI) += npcm_pspi.o obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c new file mode 100644 index 0000000000..bd9ac65411 --- /dev/null +++ b/drivers/spi/npcm_pspi.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology. + */ + +#include <common.h> +#include <dm.h> +#include <spi.h> +#include <clk.h> +#include <asm/gpio.h> +#include <linux/iopoll.h> + +#define MAX_DIV 127 + +/* Register offsets */ +#define PSPI_DATA 0 +#define PSPI_CTL1 2 +#define PSPI_STAT 4 + +/* PSPI_CTL1 fields */ +#define PSPI_CTL1_SPIEN BIT(0) +#define PSPI_CTL1_SCM BIT(7) +#define PSPI_CTL1_SCIDL BIT(8) +#define PSPI_CTL1_SCDV_MASK GENMASK(15, 9) +#define PSPI_CTL1_SCDV_SHIFT 9 + +/* PSPI_STAT fields */ +#define PSPI_STAT_BSY BIT(0) +#define PSPI_STAT_RBF BIT(1) + +struct npcm_pspi_priv { + void __iomem *base; + struct clk clk; + struct gpio_desc cs_gpio; + u32 max_hz; +}; + +static inline void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + + dm_gpio_set_value(&priv->cs_gpio, 0); +} + +static inline void spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + + dm_gpio_set_value(&priv->cs_gpio, 1); +} + +static inline void npcm_pspi_enable(struct npcm_pspi_priv *priv) +{ + u16 val; + + val = readw(priv->base + PSPI_CTL1); + val |= PSPI_CTL1_SPIEN; + writew(val, priv->base + PSPI_CTL1); +} + +static inline void npcm_pspi_disable(struct npcm_pspi_priv *priv) +{ + u16 val; + + val = readw(priv->base + PSPI_CTL1); + val &= ~PSPI_CTL1_SPIEN; + writew(val, priv->base + PSPI_CTL1); +} + +static int npcm_pspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + void __iomem *base = priv->base; + const u8 *tx = dout; + u8 *rx = din; + u32 bytes = bitlen / 8; + u8 tmp; + u32 val; + int i, ret = 0; + + npcm_pspi_enable(priv); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + for (i = 0; i < bytes; i++) { + /* Making sure we can write */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + !(val & PSPI_STAT_BSY), + 1000000); + if (ret < 0) + break; + + if (tx) + writeb(*tx++, base + PSPI_DATA); + else + writeb(0, base + PSPI_DATA); + + /* Wait till write completed */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + !(val & PSPI_STAT_BSY), + 1000000); + if (ret < 0) + break; + + /* Wait till read buffer full */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + (val & PSPI_STAT_RBF), + 1000000); + if (ret < 0) + break; + + tmp = readb(base + PSPI_DATA); + if (rx) + *rx++ = tmp; + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + npcm_pspi_disable(priv); + + return ret; +} + +static int npcm_pspi_set_speed(struct udevice *bus, uint speed) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + ulong apb_clock; + u32 divisor; + u16 val; + + apb_clock = clk_get_rate(&priv->clk); + if (!apb_clock) + return -EINVAL; + + if (speed > priv->max_hz) + speed = priv->max_hz; + + divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed) - 1); + if (divisor > MAX_DIV) + divisor = MAX_DIV; + + val = readw(priv->base + PSPI_CTL1); + val &= ~PSPI_CTL1_SCDV_MASK; + val |= divisor << PSPI_CTL1_SCDV_SHIFT; + writew(val, priv->base + PSPI_CTL1); + + debug("%s: apb_clock=%lu speed=%d divisor=%u\n", + __func__, apb_clock, speed, divisor); + + return 0; +} + +static int npcm_pspi_set_mode(struct udevice *bus, uint mode) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + u16 pspi_mode, val; + + switch (mode & (SPI_CPOL | SPI_CPHA)) { + case SPI_MODE_0: + pspi_mode = 0; + break; + case SPI_MODE_1: + pspi_mode = PSPI_CTL1_SCM; + break; + case SPI_MODE_2: + pspi_mode = PSPI_CTL1_SCIDL; + break; + case SPI_MODE_3: + pspi_mode = PSPI_CTL1_SCIDL | PSPI_CTL1_SCM; + break; + default: + break; + } + + val = readw(priv->base + PSPI_CTL1); + val &= ~(PSPI_CTL1_SCIDL | PSPI_CTL1_SCM); + val |= pspi_mode; + writew(val, priv->base + PSPI_CTL1); + + return 0; +} + +static int npcm_pspi_probe(struct udevice *bus) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + int node = dev_of_offset(bus); + int ret; + + ret = clk_get_by_index(bus, 0, &priv->clk); + if (ret < 0) + return ret; + + priv->base = dev_read_addr_ptr(bus); + priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); + gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0, + &priv->cs_gpio, GPIOD_IS_OUT); + + return 0; +} + +static const struct dm_spi_ops npcm_pspi_ops = { + .xfer = npcm_pspi_xfer, + .set_speed = npcm_pspi_set_speed, + .set_mode = npcm_pspi_set_mode, +}; + +static const struct udevice_id npcm_pspi_ids[] = { + { .compatible = "nuvoton,npcm845-pspi"}, + { .compatible = "nuvoton,npcm750-pspi"}, + { } +}; + +U_BOOT_DRIVER(npcm_pspi) = { + .name = "npcm_pspi", + .id = UCLASS_SPI, + .of_match = npcm_pspi_ids, + .ops = &npcm_pspi_ops, + .priv_auto = sizeof(struct npcm_pspi_priv), + .probe = npcm_pspi_probe, +}; -- 2.17.1

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[PATCH 0/3] Clarify standalone application support
by Paul Barker 26 Oct '22

26 Oct '22

While looking into the support for u-boot standalone applications I noticed that there was some mis-alignment between the license exception and the files which needed to be included to get a functioning application. I also noticed that the set of SPI access functions defined in the jump table was missing a key function and did not match the set of prototypes defined in the exports header. These patches should rectify the issues I found. Paul Barker (3): Licenses: Clarify exceptions for standalone apps examples: hello_world: Drop inclusion of common header exports: Fix export of SPI access functions Licenses/Exceptions | 12 ++++++++---- examples/standalone/hello_world.c | 1 - include/_exports.h | 4 ++++ include/exports.h | 15 ++++++++++++++- 4 files changed, 26 insertions(+), 6 deletions(-) -- 2.25.1

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