May 2022 - U-Boot

[PATCH] mach-rockchip: make_fit_atf.py: support OP-TEE tee.bin v1 format
by Jerome Forissier 20 Jun '22

20 Jun '22

This commit adds support for the OP-TEE 'tee.bin' v1 format for Rockchip platforms. Since OP-TEE 3.8.0, tee.bin contains meta-data in a proprietary format in addition to the ELF data. They are essential information for proper initialization of the TEE core, such as the size of the memory region covered by the TEE or a compact representation of runtime relocation data when ASLR is enabled. With OP-TEE 3.8.0 onwards, 'tee.elf' MUST NOT be used and 'tee.bin' MUST be used instead. Ignoring this recommendation can lead to crashes as described in [3]. Link: [1] https://github.com/OP-TEE/optee_os/commit/5dd1570ac5b0f6563b1a9c074533a1910… Link: [2] https://github.com/OP-TEE/optee_os/blob/3.17.0/scripts/gen_tee_bin.py#L275-… Link: [3] https://github.com/OP-TEE/optee_os/issues/4542 Signed-off-by: Jerome Forissier <jerome.forissier(a)linaro.org> --- arch/arm/mach-rockchip/make_fit_atf.py | 43 +++++++++++++++++++++----- 1 file changed, 35 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index f3224d2555..fcea652388 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -137,7 +137,7 @@ def generate_atf_fit_dts_bl31(fit_file, bl31_file_name, tee_file_name, dtbs_file num_segments = len(segments) if tee_file_name: - tee_segments = unpack_elf(tee_file_name) + tee_segments = unpack_tee_file(tee_file_name) for index, entry, paddr, data in tee_segments: append_tee_node(fit_file, num_segments + index + 1, paddr, entry) num_segments = num_segments + len(tee_segments) @@ -169,7 +169,7 @@ def generate_atf_binary(bl31_file_name): def generate_tee_binary(tee_file_name): if tee_file_name: - for index, entry, paddr, data in unpack_elf(tee_file_name): + for index, entry, paddr, data in unpack_tee_file(tee_file_name): file_name = 'tee_0x%08x.bin' % paddr with open(file_name, "wb") as atf: atf.write(data) @@ -194,6 +194,31 @@ def unpack_elf(filename): segments.append((index, e_entry, p_paddr, p_data)) return segments +def unpack_tee_file(filename): + if filename.endswith('.elf'): + return unpack_elf(filename) + with open(filename, 'rb') as file: + bin = file.read() + segments = [] + if bin[0:5] == b'OPTE\x01': + # OP-TEE v1 format (tee.bin) + init_sz, start_hi, start_lo, _, paged_sz = struct.unpack_from('<5I', + bin, + 0x8) + if paged_sz != 0: + raise ValueError("OP-TEE paged mode not supported") + e_entry = (start_hi << 32) + start_lo + p_addr = e_entry + p_data = bin[0x1c:] + if len(p_data) != init_sz: + raise ValueError("Invalid file '%s': size mismatch " + "(expected %d, have %d)" % (filename, init_sz, + len(p_data))) + segments.append((0, e_entry, p_addr, p_data)) + else: + raise ValueError("Unknown format for TEE file '%s'" % filename) + return segments + def main(): uboot_elf = "./u-boot" fit_its = sys.stdout @@ -210,11 +235,13 @@ def main(): logging.warning(' Please read Building section in doc/README.rockchip') if "TEE" in os.environ: - tee_elf = os.getenv("TEE") + tee_file = os.getenv("TEE") + elif os.path.isfile("./tee.bin"): + tee_file = "./tee.bin" elif os.path.isfile("./tee.elf"): - tee_elf = "./tee.elf" + tee_file = "./tee.elf" else: - tee_elf = "" + tee_file = "" opts, args = getopt.getopt(sys.argv[1:], "o:u:b:t:h") for opt, val in opts: @@ -225,16 +252,16 @@ def main(): elif opt == "-b": bl31_elf = val elif opt == "-t": - tee_elf = val + tee_file = val elif opt == "-h": print(__doc__) sys.exit(2) dtbs = args - generate_atf_fit_dts(fit_its, bl31_elf, tee_elf, uboot_elf, dtbs) + generate_atf_fit_dts(fit_its, bl31_elf, tee_file, uboot_elf, dtbs) generate_atf_binary(bl31_elf) - generate_tee_binary(tee_elf) + generate_tee_binary(tee_file) if __name__ == "__main__": main() -- 2.17.1

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[PATCH] drivers: usb: dwc3: Add support for AM62 USB wrapper driver
by Aswath Govindraju 20 Jun '22

20 Jun '22

Add support for AM62 USB wrapper for DWC3 Controller in AM62 SoC. Signed-off-by: Aswath Govindraju <a-govindraju(a)ti.com> --- Link to corresponding kernel dt-bindings and driver patches, - https://patchwork.kernel.org/project/linux-usb/list/?series=629613 drivers/usb/dwc3/Kconfig | 7 + drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-am62.c | 284 +++++++++++++++++++++++++++++++++++ 3 files changed, 292 insertions(+) create mode 100644 drivers/usb/dwc3/dwc3-am62.c diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 62aa65bf0cd2..87e19720ab84 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -63,6 +63,13 @@ config USB_DWC3_LAYERSCAPE Host and Peripheral operation modes are supported. OTG is not supported. +config USB_DWC3_AM62 + tristate "Texas Instruments AM62 Platforms" + depends on ARCH_K3 || COMPILE_TEST + default USB_DWC3 + help + Support of USB2 functionality in TI's AM62 platforms + menu "PHY Subsystem" config USB_DWC3_PHY_OMAP diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 0dd1ba87cd94..26bc3a7379b7 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -7,6 +7,7 @@ dwc3-y := core.o obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o +obj-$(CONFIG_USB_DWC3_AM62) += dwc3-am62.o obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o diff --git a/drivers/usb/dwc3/dwc3-am62.c b/drivers/usb/dwc3/dwc3-am62.c new file mode 100644 index 000000000000..a3ad609036e2 --- /dev/null +++ b/drivers/usb/dwc3/dwc3-am62.c @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dwc3-am62.c - TI specific Glue layer for AM62 DWC3 USB Controller + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com + */ + +#include <common.h> +#include <asm-generic/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <syscon.h> +#include <malloc.h> +#include <usb.h> +#include <usb/xhci.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <regmap.h> +#include <linux/usb/otg.h> +#include <dm/lists.h> + +/* USB WRAPPER register offsets */ +#define USBSS_PID 0x0 +#define USBSS_OVERCURRENT_CTRL 0x4 +#define USBSS_PHY_CONFIG 0x8 +#define USBSS_PHY_TEST 0xc +#define USBSS_CORE_STAT 0x14 +#define USBSS_HOST_VBUS_CTRL 0x18 +#define USBSS_MODE_CONTROL 0x1c +#define USBSS_WAKEUP_CONFIG 0x30 +#define USBSS_WAKEUP_STAT 0x34 +#define USBSS_OVERRIDE_CONFIG 0x38 +#define USBSS_IRQ_MISC_STATUS_RAW 0x430 +#define USBSS_IRQ_MISC_STATUS 0x434 +#define USBSS_IRQ_MISC_ENABLE_SET 0x438 +#define USBSS_IRQ_MISC_ENABLE_CLR 0x43c +#define USBSS_IRQ_MISC_EOI 0x440 +#define USBSS_INTR_TEST 0x490 +#define USBSS_VBUS_FILTER 0x614 +#define USBSS_VBUS_STAT 0x618 +#define USBSS_DEBUG_CFG 0x708 +#define USBSS_DEBUG_DATA 0x70c +#define USBSS_HOST_HUB_CTRL 0x714 + +/* PHY CONFIG register bits */ +#define USBSS_PHY_VBUS_SEL_MASK GENMASK(2, 1) +#define USBSS_PHY_VBUS_SEL_SHIFT 1 +#define USBSS_PHY_LANE_REVERSE BIT(0) + +/* MODE CONTROL register bits */ +#define USBSS_MODE_VALID BIT(0) + +/* IRQ_MISC_STATUS_RAW register bits */ +#define USBSS_IRQ_MISC_RAW_VBUSVALID BIT(22) +#define USBSS_IRQ_MISC_RAW_SESSVALID BIT(20) + +/* IRQ_MISC_STATUS register bits */ +#define USBSS_IRQ_MISC_VBUSVALID BIT(22) +#define USBSS_IRQ_MISC_SESSVALID BIT(20) + +/* IRQ_MISC_ENABLE_SET register bits */ +#define USBSS_IRQ_MISC_ENABLE_SET_VBUSVALID BIT(22) +#define USBSS_IRQ_MISC_ENABLE_SET_SESSVALID BIT(20) + +/* IRQ_MISC_ENABLE_CLR register bits */ +#define USBSS_IRQ_MISC_ENABLE_CLR_VBUSVALID BIT(22) +#define USBSS_IRQ_MISC_ENABLE_CLR_SESSVALID BIT(20) + +/* VBUS_STAT register bits */ +#define USBSS_VBUS_STAT_SESSVALID BIT(2) +#define USBSS_VBUS_STAT_VBUSVALID BIT(0) + +/* Mask for PHY PLL REFCLK */ +#define PHY_PLL_REFCLK_MASK GENMASK(3, 0) + +struct dwc3_data { + struct udevice *dev; + void __iomem *usbss; + struct regmap *syscon; + unsigned int offset; + unsigned int vbus_divider; +}; + +static inline u32 dwc3_ti_readl(struct dwc3_data *data, u32 offset) +{ + return readl(data->usbss + offset); +} + +static inline void dwc3_ti_writel(struct dwc3_data *data, u32 offset, u32 value) +{ + writel(value, data->usbss + offset); +} + +static const int dwc3_ti_rate_table[] = { /* in KHZ */ + 9600, + 10000, + 12000, + 19200, + 20000, + 24000, + 25000, + 26000, + 38400, + 40000, + 58000, + 50000, + 52000, +}; + +static int phy_syscon_pll_refclk(struct dwc3_data *data, int rate_code) +{ + struct udevice *dev = data->dev; + struct ofnode_phandle_args args; + ofnode node = dev_ofnode(dev); + struct regmap *syscon; + int ret; + + syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-phy-pll-refclk"); + if (IS_ERR(syscon)) { + dev_err(dev, "unable to get ti,syscon-phy-pll-refclk regmap\n"); + return PTR_ERR(syscon); + } + + data->syscon = syscon; + + ret = ofnode_parse_phandle_with_args(node, "ti,syscon-phy-pll-refclk", NULL, 1, + 0, &args); + if (ret) + return ret; + + data->offset = args.args[0]; + + /* Program PHY PLL refclk by reading syscon property */ + ret = regmap_update_bits(data->syscon, data->offset, PHY_PLL_REFCLK_MASK, rate_code); + if (ret) { + dev_err(dev, "failed to set phy pll reference clock rate\n"); + return ret; + } + + return 0; +} + +static int dwc3_ti_bind(struct udevice *parent) +{ + ofnode node; + const char *name = ofnode_get_name(node); + enum usb_dr_mode dr_mode; + struct udevice *dev; + const char *driver = NULL; + int ret; + + node = ofnode_by_compatible(dev_ofnode(parent), "snps,dwc3"); + if (!ofnode_valid(node)) { + ret = -ENODEV; + return 0; + } + + name = ofnode_get_name(node); + dr_mode = usb_get_dr_mode(node); + debug("%s: subnode name: %s\n", __func__, name); + + switch (dr_mode) { + case USB_DR_MODE_PERIPHERAL: + case USB_DR_MODE_OTG: +#if CONFIG_IS_ENABLED(DM_USB_GADGET) + debug("%s: dr_mode: OTG or Peripheral\n", __func__); + driver = "dwc3-generic-peripheral"; +#endif + break; +#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD) + case USB_DR_MODE_HOST: + debug("%s: dr_mode: HOST\n", __func__); + driver = "dwc3-generic-host"; + break; +#endif + default: + debug("%s: unsupported dr_mode\n", __func__); + return -ENODEV; + }; + + if (!driver) + return 0; + + ret = device_bind_driver_to_node(parent, driver, name, + node, &dev); + if (ret) { + debug("%s: not able to bind usb device mode\n", + __func__); + return ret; + } + + return 0; +} + +static int dwc3_ti_probe(struct udevice *dev) +{ + struct dwc3_data *data = dev_get_plat(dev); + struct clk usb2_refclk; + int rate_code, i, ret; + unsigned long rate; + u32 reg; + + data->dev = dev; + + data->usbss = dev_remap_addr_index(dev, 0); + if (IS_ERR(data->usbss)) { + dev_err(dev, "can't map IOMEM resource\n"); + return PTR_ERR(data->usbss); + } + + ret = clk_get_by_name(dev, "ref", &usb2_refclk); + if (ret) { + dev_err(dev, "can't get usb2_refclk\n"); + return ret; + } + + /* Calcuate the rate code */ + rate = clk_get_rate(&usb2_refclk); + rate /= 1000; /* To KHz */ + for (i = 0; i < ARRAY_SIZE(dwc3_ti_rate_table); i++) { + if (dwc3_ti_rate_table[i] == rate) + break; + } + + if (i == ARRAY_SIZE(dwc3_ti_rate_table)) { + dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate); + return -EINVAL; + } + + rate_code = i; + + /* Read the syscon property */ + ret = phy_syscon_pll_refclk(data, rate_code); + if (ret) + return ret; + + /* VBUS divider select */ + reg = dwc3_ti_readl(data, USBSS_PHY_CONFIG); + data->vbus_divider = dev_read_bool(dev, "ti,vbus-divider"); + if (data->vbus_divider) + reg |= 1 << USBSS_PHY_VBUS_SEL_SHIFT; + + dwc3_ti_writel(data, USBSS_PHY_CONFIG, reg); + + /* Set mode valid */ + reg = dwc3_ti_readl(data, USBSS_MODE_CONTROL); + reg |= USBSS_MODE_VALID; + dwc3_ti_writel(data, USBSS_MODE_CONTROL, reg); + + return 0; +} + +/* work queue not required to cancel separately as auto cancel API was used*/ +static int dwc3_ti_remove(struct udevice *dev) +{ + struct dwc3_data *data = dev_get_plat(dev); + u32 reg; + + /* Clear mode valid */ + reg = dwc3_ti_readl(data, USBSS_MODE_CONTROL); + reg &= ~USBSS_MODE_VALID; + dwc3_ti_writel(data, USBSS_MODE_CONTROL, reg); + + return 0; +} + +static const struct udevice_id dwc3_ti_of_match[] = { + { .compatible = "ti,am62-usb", }, + {}, +}; + +U_BOOT_DRIVER(dwc3_ti) = { + .name = "dwc3-ti", + .id = UCLASS_NOP, + .of_match = dwc3_ti_of_match, + .bind = dwc3_ti_bind, + .probe = dwc3_ti_probe, + .remove = dwc3_ti_remove, + .plat_auto = sizeof(struct dwc3_data), + .flags = DM_FLAG_OS_PREPARE, +}; -- 2.17.1

2 1

[PATCH] mtd: rawnand: fsl_elbc: Fix detection when nand_scan_ident() has not selected ecc.mode
by Pali Rohár 20 Jun '22

20 Jun '22

ecc.mode is set to 0 (aliased to NAND_ECC_NONE) either when function nand_scan_ident() has not selected ecc.mode or when it selected it to none ecc mode. Distinguish between these two states by checking of node property "nand-ecc-mode" which function nand_scan_ident() uses for filling ecc.mode. This change fixes usage of none ecc mode if it is specified in DTS file. Fixes: c9ea9019c5aa ("mtd: rawnand: fsl_elbc: Use ECC configuration from device tree") Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/mtd/nand/raw/fsl_elbc_nand.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index b0e3eb607ed4..8e14739b3ee9 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -745,7 +745,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev) return ret; /* If nand_scan_ident() has not selected ecc.mode, do it now */ - if (nand->ecc.mode == NAND_ECC_NONE) { + if (nand->ecc.mode == 0 && + !ofnode_read_string(nand->flash_node, "nand-ecc-mode")) { /* If CS Base Register selects full hardware ECC then use it */ if ((br & BR_DECC) == BR_DECC_CHK_GEN) { nand->ecc.mode = NAND_ECC_HW; -- 2.20.1

2 3

[PATCH v3 1/2] pmic: pca9450: Add upstream regulators subnode match
by Marek Vasut 20 Jun '22

20 Jun '22

The upstream DT regulators node subnodes are named BUCKn and LDOn, the downstream DT regulators node subnodes are named buckn and ldon, add the upstream match. Reviewed-by: Fabio Estevam <festevam(a)denx.de> Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- V2: Add RB by Fabio V3: Rebase on u-boot-imx/master --- drivers/power/pmic/pca9450.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 2394b196c56..26c876c9c45 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; static const struct pmic_child_info pmic_children_info[] = { /* buck */ { .prefix = "b", .driver = PCA9450_REGULATOR_DRIVER}, + { .prefix = "B", .driver = PCA9450_REGULATOR_DRIVER}, /* ldo */ { .prefix = "l", .driver = PCA9450_REGULATOR_DRIVER}, + { .prefix = "L", .driver = PCA9450_REGULATOR_DRIVER}, { }, }; -- 2.35.1

3 5

[Rock Pi 4+] Mainline LPDDR4 RAM initialisation is not sufficient to boot successfully
by Lee Jones 17 Jun '22

17 Jun '22

Good afternoon, There appear to be a number of issues with the Rockchip rk3399 DDR RAM initialisation sequence in Mainline. Specifically, I'm seeing consistent failures on the Rock Pi 4+ during early boot. A typical failure looks something like this: U-Boot TPL 2022.07-rc3-00005-g1b04a961c6 (May 25 2022 - 11:09:19) Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB Channel 1: col error Cap error! 256B stride lpddr4_set_rate: change freq to 400000000 mhz 0, 1 lpddr4_set_rate: change freq to 800000000 mhz 1, 0 Trying to boot from BOOTROM Returning to boot ROM... Even when the system boots to a terminal, which happens very infrequently, the LPDDR4 RAM chip at Channel 1 can have conflicting discovery information printed during TPL. The following 3 lines were printed during successive reboots using the same SD card with no changes: # Boot 1: BW=32 Col=9 Bk=4 CS0 Row=16/15 CS=1 Die BW=16 Size=384MB # Boot 2: BW=32 Col=10 Bk=4 CS0 Row=16/15 CS=1 Die BW=16 Size=768MB # Boot 3: BW=32 Col=10 Bk=4 CS0 Row=15 CS=1 Die BW=16 Size=512MB The story changes when I build the idbloader.img image with Rockchip's TBL (?) binary blob [0]. With that built in, presumably in place of the upstream TBL, both RAM chips are successfully enumerated and boot succeeds with 100% success rate: tools/mkimage -n rk3399 -T rksd -d \ rk3399_ddr_933MHz_v1.25.bin:spl/u-boot-spl.bin idbloader.img Another thing that is very different between the 2 is the initial frequency the LPDDR4 chips are clocked at. Using the upstream TBL version, the default is 50Mhz, which seems very low. If using the Rockchip supplied binary blob file, this is increased to a respectable 416MHz: # Mainline Channel 0: LPDDR4, 50MHz # Rockchip TBL blob Channel 0: LPDDR4,416MHz One thing I did try was to load in the 400Mhz configuration settings from drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc as the default initial values, instead of the 50MHz default taken from arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi, but this failed in a number of ways: Setting clock: Freq: 400MHz (400000000) Calling SDRAM init: 2 Channels Starting SDRAM initialization... mr5:0 mr12:0 mr14:0 Training failed for rank 2, ch 0 (ret: -22) mr5:0 mr12:0 mr14:0 Training failed for rank 1, ch 0 (ret: -22) mr5:0 mr12:0 mr14:0 Training failed for rank 2, ch 1 (ret: -22) mr5:0 mr12:0 mr14:0 Training failed for rank 1, ch 1 (ret: -22) Rank for Channel 1 is 0x0 Rank for Channel 0 is 0x0 Rank for Channel 1 is 0x0 sdram_init: LPDDR4 - 400MHz failed! rk3399_dmc_init DRAM init failed -22 So my question is; does Rockchip, or anyone else for that matter, have any plans on updating Mainline U-Boot with the upgraded/working LPDDR4 initialisation sequence? As ever, any information / help would be gratefully received. NB: If I have missed any critical people out from this discussion, please feel free to loop as many of them in as you see fit. Kind regards, Lee [0] https://github.com/rockchip-linux/rkbin/blob/master/bin/rk33/rk3399_ddr_933… -- Lee Jones [李琼斯] Principal Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog

2 3

[PATCH] Update email address and company name
by Christophe Leroy 17 Jun '22

17 Jun '22

This patch updates my email address and company name. Signed-off-by: Christophe Leroy <christophe.leroy(a)csgroup.eu> --- board/cssi/MAINTAINERS | 4 ++-- doc/git-mailrc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/cssi/MAINTAINERS b/board/cssi/MAINTAINERS index cbf1406a54..7d237b0b20 100644 --- a/board/cssi/MAINTAINERS +++ b/board/cssi/MAINTAINERS @@ -1,5 +1,5 @@ -BOARDS from CS Systemes d'Information -M: Christophe Leroy <christophe.leroy(a)c-s.fr> +BOARDS from CS GROUP France +M: Christophe Leroy <christophe.leroy(a)csgroup.eu> S: Maintained F: board/cssi/ F: include/configs/MCR3000.h diff --git a/doc/git-mailrc b/doc/git-mailrc index 410be387be..0580f56790 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -97,7 +97,7 @@ alias nios2 nios alias powerpc uboot, afleming, stroese, wd, priyankajain, mariosix alias ppc powerpc -alias mpc8xx uboot, wd, Christophe Leroy <christophe.leroy(a)c-s.fr> +alias mpc8xx uboot, wd, Christophe Leroy <christophe.leroy(a)csgroup.eu> alias mpc83xx uboot, mariosix alias mpc85xx uboot, afleming, priyankajain -- 2.35.1

2 1

[PATCH] arch: arm: mach-k3: am642_init: bring back MCU_PADCFG_MMR1 unlock
by Christian Gmeiner 17 Jun '22

17 Jun '22

Without this register unlock it is not possible to configure the pinmux used for mcu spi0. Fixes: 92e46092f2 ("arch: arm: mach-k3: am642_init: Probe ESM nodes") Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- arch/arm/mach-k3/am642_init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index add7ea8377..b16de9c9f0 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -47,6 +47,9 @@ static void ctrl_mmr_unlock(void) mmr_unlock(CTRL_MMR0_BASE, 3); mmr_unlock(CTRL_MMR0_BASE, 5); mmr_unlock(CTRL_MMR0_BASE, 6); + + /* Unlock all MCU_PADCFG_MMR1 module registers */ + mmr_unlock(MCU_PADCFG_MMR1_BASE, 1); } /* -- 2.36.1

3 2

[PATCH] net: Fix discuss discard typo
by Marek Vasut 17 Jun '22

17 Jun '22

Replace discuss with discard, that is what happens with packet with incorrect checksum. Fix the typo. Fixes: 4b37fd146bb ("Convert CONFIG_UDP_CHECKSUM to Kconfig") Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Ramon Fried <rfried.dev(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> --- net/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/Kconfig b/net/Kconfig index 964a4fe4999..564ea8b2d28 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -158,7 +158,7 @@ config UDP_CHECKSUM default y if SANDBOX help Enable this to verify the checksum on UDP packets. If the checksum - is wrong then the packet is discussed and an error is shown, like + is wrong then the packet is discarded and an error is shown, like "UDP wrong checksum 29374a23 30ff3826" config BOOTP_SERVERIP -- 2.35.1

2 1

[PATCH] crypto: fsl_hash: Remove unnecessary alignment check in caam_hash()
by Stefan Roese 17 Jun '22

17 Jun '22

While working on an LX2160 based board and updating to latest mainline I noticed problems using the HW accelerated hash functions on this platform, when trying to boot a FIT Kernel image. Here the resulting error message: Using 'conf-freescale_lx2160a.dtb' configuration Trying 'kernel-1' kernel subimage Verifying Hash Integrity ... sha256Error: Address arguments are not aligned CAAM was not setup properly or it is faulty error! Bad hash value for 'hash-1' hash node in 'kernel-1' image node Bad Data Hash ERROR: can't get kernel image! Testing and checking with Gaurav Jain from NXP has revealed, that this alignment check is not necessary here at all. So let's remove this check completely. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Gaurav Jain <gaurav.jain(a)nxp.com> Cc: dullfire(a)yahoo.com --- drivers/crypto/fsl/fsl_hash.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index a52c4ac957e0..0a371bffd5eb 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -168,12 +168,6 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len, uint32_t *desc; unsigned int size; - if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) || - !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) { - puts("Error: Address arguments are not aligned\n"); - return -EINVAL; - } - desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); -- 2.32.0

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[PATCH] stm32mp1: fix reference for STMicroelectronics
by Patrick Delaunay 17 Jun '22

17 Jun '22

Replace reference to the correct name STMicroelectronics Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/Kconfig | 2 +- arch/arm/cpu/armv7/stv0991/lowlevel.S | 2 +- arch/arm/mach-sti/Kconfig | 2 +- drivers/i2c/designware_i2c.c | 2 +- drivers/i2c/designware_i2c.h | 2 +- drivers/i2c/designware_i2c_pci.c | 2 +- drivers/mtd/nand/raw/fsmc_nand.c | 4 ++-- drivers/mtd/spi/spi-nor-ids.c | 2 +- drivers/net/designware.c | 2 +- drivers/net/designware.h | 2 +- drivers/pinctrl/Kconfig | 2 +- drivers/spi/pl022_spi.c | 2 +- drivers/usb/gadget/designware_udc.c | 2 +- include/configs/stm32mp15_st_common.h | 2 +- include/elf.h | 4 ++-- include/linux/mtd/fsmc_nand.h | 2 +- include/usb/designware_udc.h | 2 +- 17 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5f24ffc0f3..53679b084c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1923,7 +1923,7 @@ config ARCH_STM32 imply CMD_DM config ARCH_STI - bool "Support STMicrolectronics SoCs" + bool "Support STMicroelectronics SoCs" select BLK select CPU_V7A select DM diff --git a/arch/arm/cpu/armv7/stv0991/lowlevel.S b/arch/arm/cpu/armv7/stv0991/lowlevel.S index 218ac70f32..5733eaa15c 100644 --- a/arch/arm/cpu/armv7/stv0991/lowlevel.S +++ b/arch/arm/cpu/armv7/stv0991/lowlevel.S @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2014 stmicroelectronics + * (C) Copyright 2014 STMicroelectronics */ #include <config.h> diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index f9a583af8d..d9e264024c 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -9,7 +9,7 @@ choice config TARGET_STIH410_B2260 bool "96Boards STiH410-B2260" help - Support for 96Board STiH410-B2260 based on STMicrolectronics + Support for 96Board STiH410-B2260 based on STMicroelectronics STiH410 soc. This board complies with 96Board Open Platform Specifications. Features: - 1GB DDR diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 1aae6b64ba..e54de42abc 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar(a)st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar(a)st.com. */ #include <common.h> diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h index a9c50c90ac..049976e8a2 100644 --- a/drivers/i2c/designware_i2c.h +++ b/drivers/i2c/designware_i2c.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar(a)st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar(a)st.com. */ #ifndef __DW_I2C_H_ diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index 1572c2c6bc..46c2545f21 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar(a)st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar(a)st.com. * Copyright 2019 Google Inc */ diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c index 5d197ce0c5..a92c6252a5 100644 --- a/drivers/mtd/nand/raw/fsmc_nand.c +++ b/drivers/mtd/nand/raw/fsmc_nand.c @@ -1,10 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2010 - * Vipin Kumar, ST Microelectronics, vipin.kumar(a)st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar(a)st.com. * * (C) Copyright 2012 - * Amit Virdi, ST Microelectronics, amit.virdi(a)st.com. + * Amit Virdi, STMicroelectronics, amit.virdi(a)st.com. */ #include <common.h> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 7050ddc397..20cd4d7fc9 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -280,7 +280,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ - /* ST Microelectronics -- newer production may have feature updates */ + /* STMicroelectronics -- newer production may have feature updates */ { INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) }, { INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) }, { INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) }, diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 1584b9eac1..0e63f70934 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2010 - * Vipin Kumar, ST Micoelectronics, vipin.kumar(a)st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar(a)st.com. */ /* diff --git a/drivers/net/designware.h b/drivers/net/designware.h index a82afb99ca..ddc3d4f150 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2010 - * Vipin Kumar, ST Micoelectronics, vipin.kumar(a)st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar(a)st.com. */ #ifndef _DW_ETH_H diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 563d96d4f5..8a83f7e57f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -272,7 +272,7 @@ config PINCTRL_STI depends on DM && ARCH_STI default y help - Support pin multiplexing control on STMicrolectronics STi SoCs. + Support pin multiplexing control on STMicroelectronics STi SoCs. The driver is controlled by a device tree node which contains both the GPIO definitions and pin control functions for each available diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c index ea1691438b..828eab3d34 100644 --- a/drivers/spi/pl022_spi.c +++ b/drivers/spi/pl022_spi.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2012 - * Armando Visconti, ST Microelectronics, armando.visconti(a)st.com. + * Armando Visconti, STMicroelectronics, armando.visconti(a)st.com. * * (C) Copyright 2018 * Quentin Schulz, Bootlin, quentin.schulz(a)bootlin.com diff --git a/drivers/usb/gadget/designware_udc.c b/drivers/usb/gadget/designware_udc.c index 7fc5d27d43..41a6e8cb7d 100644 --- a/drivers/usb/gadget/designware_udc.c +++ b/drivers/usb/gadget/designware_udc.c @@ -4,7 +4,7 @@ * TI OMAP1510 USB bus interface driver * * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar(a)st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar(a)st.com. */ #include <common.h> diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 3c0ffb8f56..37b216e6e9 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -2,7 +2,7 @@ /* * Copyright (C) 2021, STMicroelectronics - All Rights Reserved * - * Configuration settings for the STMicroelectonics STM32MP15x boards + * Configuration settings for the STMicroelectronics STM32MP15x boards */ #ifndef __CONFIG_STM32MP15_ST_COMMON_H__ diff --git a/include/elf.h b/include/elf.h index b04e746d61..aeda159f0c 100644 --- a/include/elf.h +++ b/include/elf.h @@ -188,14 +188,14 @@ typedef struct { #define EM_NDR1 57 /* Denso NDR1 microprocessor */ #define EM_STARCORE 58 /* Motorola Start*Core processor */ #define EM_ME16 59 /* Toyota ME16 processor */ -#define EM_ST100 60 /* STMicroelectronic ST100 processor */ +#define EM_ST100 60 /* STMicroelectronics ST100 processor */ #define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ #define EM_X86_64 62 /* AMD x86-64 */ #define EM_PDSP 63 /* Sony DSP Processor */ /* RESERVED 64,65 for future use */ #define EM_FX66 66 /* Siemens FX66 microcontroller */ #define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ -#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ +#define EM_ST7 68 /* STMicroelectronics ST7 8 bit mc */ #define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ #define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ #define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ diff --git a/include/linux/mtd/fsmc_nand.h b/include/linux/mtd/fsmc_nand.h index 6079f9e260..1d8a067f17 100644 --- a/include/linux/mtd/fsmc_nand.h +++ b/include/linux/mtd/fsmc_nand.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2010 - * Vipin Kumar, ST Micoelectronics, vipin.kumar(a)st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar(a)st.com. */ #ifndef __FSMC_NAND_H__ diff --git a/include/usb/designware_udc.h b/include/usb/designware_udc.h index f874e5c35c..f716f07dd0 100644 --- a/include/usb/designware_udc.h +++ b/include/usb/designware_udc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar(a)st.com. + * Vipin Kumar, STMicroelectronics, vipin.kumar(a)st.com. */ #ifndef __DW_UDC_H -- 2.25.1

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