April 2022 - U-Boot

[PATCH 01/16] net: dm9000: Make accessor names lowercase
by Marek Vasut 12 Apr '22

12 Apr '22

Make accessor names lowercase to be consistent with coding style. No functional change. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Ramon Fried <rfried.dev(a)gmail.com> --- drivers/net/dm9000x.c | 214 +++++++++++++++++++++--------------------- 1 file changed, 107 insertions(+), 107 deletions(-) diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index 4f062e99d9b..93699135f75 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -104,24 +104,24 @@ static board_info_t dm9000_info; static int dm9000_probe(void); static u16 dm9000_phy_read(int); static void dm9000_phy_write(int, u16); -static u8 DM9000_ior(int); -static void DM9000_iow(int reg, u8 value); +static u8 dm9000_ior(int); +static void dm9000_iow(int reg, u8 value); /* DM9000 network board routine ---------------------------- */ #ifndef CONFIG_DM9000_BYTE_SWAPPED -#define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r)) -#define DM9000_outw(d,r) writew(d, (volatile u16 *)(r)) -#define DM9000_outl(d,r) writel(d, (volatile u32 *)(r)) -#define DM9000_inb(r) readb((volatile u8 *)(r)) -#define DM9000_inw(r) readw((volatile u16 *)(r)) -#define DM9000_inl(r) readl((volatile u32 *)(r)) +#define dm9000_outb(d,r) writeb(d, (volatile u8 *)(r)) +#define dm9000_outw(d,r) writew(d, (volatile u16 *)(r)) +#define dm9000_outl(d,r) writel(d, (volatile u32 *)(r)) +#define dm9000_inb(r) readb((volatile u8 *)(r)) +#define dm9000_inw(r) readw((volatile u16 *)(r)) +#define dm9000_inl(r) readl((volatile u32 *)(r)) #else -#define DM9000_outb(d, r) __raw_writeb(d, r) -#define DM9000_outw(d, r) __raw_writew(d, r) -#define DM9000_outl(d, r) __raw_writel(d, r) -#define DM9000_inb(r) __raw_readb(r) -#define DM9000_inw(r) __raw_readw(r) -#define DM9000_inl(r) __raw_readl(r) +#define dm9000_outb(d, r) __raw_writeb(d, r) +#define dm9000_outw(d, r) __raw_writew(d, r) +#define dm9000_outl(d, r) __raw_writel(d, r) +#define dm9000_inb(r) __raw_readb(r) +#define dm9000_inw(r) __raw_readw(r) +#define dm9000_inl(r) __raw_readl(r) #endif #ifdef CONFIG_DM9000_DEBUG @@ -129,14 +129,14 @@ static void dump_regs(void) { DM9000_DBG("\n"); - DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0)); - DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1)); - DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2)); - DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3)); - DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4)); - DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5)); - DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6)); - DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR)); + DM9000_DBG("NCR (0x00): %02x\n", dm9000_ior(0)); + DM9000_DBG("NSR (0x01): %02x\n", dm9000_ior(1)); + DM9000_DBG("TCR (0x02): %02x\n", dm9000_ior(2)); + DM9000_DBG("TSRI (0x03): %02x\n", dm9000_ior(3)); + DM9000_DBG("TSRII (0x04): %02x\n", dm9000_ior(4)); + DM9000_DBG("RCR (0x05): %02x\n", dm9000_ior(5)); + DM9000_DBG("RSR (0x06): %02x\n", dm9000_ior(6)); + DM9000_DBG("ISR (0xFE): %02x\n", dm9000_ior(DM9000_ISR)); DM9000_DBG("\n"); } #endif @@ -145,7 +145,7 @@ static void dm9000_outblk_8bit(volatile void *data_ptr, int count) { int i; for (i = 0; i < count; i++) - DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA); + dm9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA); } static void dm9000_outblk_16bit(volatile void *data_ptr, int count) @@ -154,7 +154,7 @@ static void dm9000_outblk_16bit(volatile void *data_ptr, int count) u32 tmplen = (count + 1) / 2; for (i = 0; i < tmplen; i++) - DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); + dm9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); } static void dm9000_outblk_32bit(volatile void *data_ptr, int count) { @@ -162,14 +162,14 @@ static void dm9000_outblk_32bit(volatile void *data_ptr, int count) u32 tmplen = (count + 3) / 4; for (i = 0; i < tmplen; i++) - DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); + dm9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); } static void dm9000_inblk_8bit(void *data_ptr, int count) { int i; for (i = 0; i < count; i++) - ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA); + ((u8 *) data_ptr)[i] = dm9000_inb(DM9000_DATA); } static void dm9000_inblk_16bit(void *data_ptr, int count) @@ -178,7 +178,7 @@ static void dm9000_inblk_16bit(void *data_ptr, int count) u32 tmplen = (count + 1) / 2; for (i = 0; i < tmplen; i++) - ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA); + ((u16 *) data_ptr)[i] = dm9000_inw(DM9000_DATA); } static void dm9000_inblk_32bit(void *data_ptr, int count) { @@ -186,38 +186,38 @@ static void dm9000_inblk_32bit(void *data_ptr, int count) u32 tmplen = (count + 3) / 4; for (i = 0; i < tmplen; i++) - ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA); + ((u32 *) data_ptr)[i] = dm9000_inl(DM9000_DATA); } static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen) { u32 tmpdata; - DM9000_outb(DM9000_MRCMD, DM9000_IO); + dm9000_outb(DM9000_MRCMD, DM9000_IO); - tmpdata = DM9000_inl(DM9000_DATA); + tmpdata = dm9000_inl(DM9000_DATA); *RxStatus = __le16_to_cpu(tmpdata); *RxLen = __le16_to_cpu(tmpdata >> 16); } static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen) { - DM9000_outb(DM9000_MRCMD, DM9000_IO); + dm9000_outb(DM9000_MRCMD, DM9000_IO); - *RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA)); - *RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA)); + *RxStatus = __le16_to_cpu(dm9000_inw(DM9000_DATA)); + *RxLen = __le16_to_cpu(dm9000_inw(DM9000_DATA)); } static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen) { - DM9000_outb(DM9000_MRCMD, DM9000_IO); + dm9000_outb(DM9000_MRCMD, DM9000_IO); *RxStatus = - __le16_to_cpu(DM9000_inb(DM9000_DATA) + - (DM9000_inb(DM9000_DATA) << 8)); + __le16_to_cpu(dm9000_inb(DM9000_DATA) + + (dm9000_inb(DM9000_DATA) << 8)); *RxLen = - __le16_to_cpu(DM9000_inb(DM9000_DATA) + - (DM9000_inb(DM9000_DATA) << 8)); + __le16_to_cpu(dm9000_inb(DM9000_DATA) + + (dm9000_inb(DM9000_DATA) << 8)); } /* @@ -227,10 +227,10 @@ int dm9000_probe(void) { u32 id_val; - id_val = DM9000_ior(DM9000_VIDL); - id_val |= DM9000_ior(DM9000_VIDH) << 8; - id_val |= DM9000_ior(DM9000_PIDL) << 16; - id_val |= DM9000_ior(DM9000_PIDH) << 24; + id_val = dm9000_ior(DM9000_VIDL); + id_val |= dm9000_ior(DM9000_VIDH) << 8; + id_val |= dm9000_ior(DM9000_PIDL) << 16; + id_val |= dm9000_ior(DM9000_PIDH) << 24; if (id_val == DM9000_ID) { printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE, id_val); @@ -252,28 +252,28 @@ dm9000_reset(void) see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */ /* DEBUG: Make all GPIO0 outputs, all others inputs */ - DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT); + dm9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT); /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */ - DM9000_iow(DM9000_GPR, 0); + dm9000_iow(DM9000_GPR, 0); /* Step 2: Software reset */ - DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); + dm9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); do { DM9000_DBG("resetting the DM9000, 1st reset\n"); udelay(25); /* Wait at least 20 us */ - } while (DM9000_ior(DM9000_NCR) & 1); + } while (dm9000_ior(DM9000_NCR) & 1); - DM9000_iow(DM9000_NCR, 0); - DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */ + dm9000_iow(DM9000_NCR, 0); + dm9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */ do { DM9000_DBG("resetting the DM9000, 2nd reset\n"); udelay(25); /* Wait at least 20 us */ - } while (DM9000_ior(DM9000_NCR) & 1); + } while (dm9000_ior(DM9000_NCR) & 1); /* Check whether the ethernet controller is present */ - if ((DM9000_ior(DM9000_PIDL) != 0x0) || - (DM9000_ior(DM9000_PIDH) != 0x90)) + if ((dm9000_ior(DM9000_PIDL) != 0x0) || + (dm9000_ior(DM9000_PIDH) != 0x90)) printf("ERROR: resetting DM9000 -> not responding\n"); } @@ -294,7 +294,7 @@ static int dm9000_init(struct eth_device *dev, struct bd_info *bd) return -1; /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */ - io_mode = DM9000_ior(DM9000_ISR) >> 6; + io_mode = dm9000_ior(DM9000_ISR) >> 6; switch (io_mode) { case 0x0: /* 16-bit mode */ @@ -325,21 +325,21 @@ static int dm9000_init(struct eth_device *dev, struct bd_info *bd) } /* Program operating register, only internal phy supported */ - DM9000_iow(DM9000_NCR, 0x0); + dm9000_iow(DM9000_NCR, 0x0); /* TX Polling clear */ - DM9000_iow(DM9000_TCR, 0); + dm9000_iow(DM9000_TCR, 0); /* Less 3Kb, 200us */ - DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US); + dm9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US); /* Flow Control : High/Low Water */ - DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); + dm9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* SH FIXME: This looks strange! Flow Control */ - DM9000_iow(DM9000_FCR, 0x0); + dm9000_iow(DM9000_FCR, 0x0); /* Special Mode */ - DM9000_iow(DM9000_SMCR, 0); + dm9000_iow(DM9000_SMCR, 0); /* clear TX status */ - DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); + dm9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* Clear interrupt status */ - DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS); + dm9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS); printf("MAC: %pM\n", dev->enetaddr); if (!is_valid_ethaddr(dev->enetaddr)) { @@ -348,20 +348,20 @@ static int dm9000_init(struct eth_device *dev, struct bd_info *bd) /* fill device MAC address registers */ for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) - DM9000_iow(oft, dev->enetaddr[i]); + dm9000_iow(oft, dev->enetaddr[i]); for (i = 0, oft = 0x16; i < 8; i++, oft++) - DM9000_iow(oft, 0xff); + dm9000_iow(oft, 0xff); /* read back mac, just to be sure */ for (i = 0, oft = 0x10; i < 6; i++, oft++) - DM9000_DBG("%02x:", DM9000_ior(oft)); + DM9000_DBG("%02x:", dm9000_ior(oft)); DM9000_DBG("\n"); /* Activate DM9000 */ /* RX enable */ - DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); + dm9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* Enable TX/RX interrupt mask */ - DM9000_iow(DM9000_IMR, IMR_PAR); + dm9000_iow(DM9000_IMR, IMR_PAR); i = 0; while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */ @@ -408,31 +408,31 @@ static int dm9000_send(struct eth_device *netdev, void *packet, int length) DM9000_DMP_PACKET(__func__ , packet, length); - DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ + dm9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ /* Move data to DM9000 TX RAM */ - DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */ + dm9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */ /* push the data to the TX-fifo */ (db->outblk)(packet, length); /* Set TX length to DM9000 */ - DM9000_iow(DM9000_TXPLL, length & 0xff); - DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff); + dm9000_iow(DM9000_TXPLL, length & 0xff); + dm9000_iow(DM9000_TXPLH, (length >> 8) & 0xff); /* Issue TX polling command */ - DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ + dm9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ /* wait for end of transmission */ tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; - while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) || - !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) { + while ( !(dm9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) || + !(dm9000_ior(DM9000_ISR) & IMR_PTM) ) { if (get_timer(0) >= tmo) { printf("transmission timeout\n"); break; } } - DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ + dm9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ DM9000_DBG("transmit done\n\n"); return 0; @@ -448,9 +448,9 @@ static void dm9000_halt(struct eth_device *netdev) /* RESET devie */ dm9000_phy_write(0, 0x8000); /* PHY RESET */ - DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */ - DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */ - DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */ + dm9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */ + dm9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */ + dm9000_iow(DM9000_RCR, 0x00); /* Disable RX */ } /* @@ -465,23 +465,23 @@ static int dm9000_rx(struct eth_device *netdev) /* Check packet ready or not, we must check the ISR status first for DM9000A */ - if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */ + if (!(dm9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */ return 0; - DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */ + dm9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */ /* There is _at least_ 1 package in the fifo, read them all */ for (;;) { - DM9000_ior(DM9000_MRCMDX); /* Dummy read */ + dm9000_ior(DM9000_MRCMDX); /* Dummy read */ /* Get most updated data, only look at bits 0:1, See application notes DM9000 */ - rxbyte = DM9000_inb(DM9000_DATA) & 0x03; + rxbyte = dm9000_inb(DM9000_DATA) & 0x03; /* Status check: this byte must be 0 or 1 */ if (rxbyte > DM9000_PKT_RDY) { - DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */ - DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ + dm9000_iow(DM9000_RCR, 0x00); /* Stop Device */ + dm9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ printf("DM9000 error: status check fail: 0x%x\n", rxbyte); return 0; @@ -532,22 +532,22 @@ static int dm9000_rx(struct eth_device *netdev) #if !defined(CONFIG_DM9000_NO_SROM) void dm9000_read_srom_word(int offset, u8 *to) { - DM9000_iow(DM9000_EPAR, offset); - DM9000_iow(DM9000_EPCR, 0x4); + dm9000_iow(DM9000_EPAR, offset); + dm9000_iow(DM9000_EPCR, 0x4); udelay(8000); - DM9000_iow(DM9000_EPCR, 0x0); - to[0] = DM9000_ior(DM9000_EPDRL); - to[1] = DM9000_ior(DM9000_EPDRH); + dm9000_iow(DM9000_EPCR, 0x0); + to[0] = dm9000_ior(DM9000_EPDRL); + to[1] = dm9000_ior(DM9000_EPDRH); } void dm9000_write_srom_word(int offset, u16 val) { - DM9000_iow(DM9000_EPAR, offset); - DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); - DM9000_iow(DM9000_EPDRL, (val & 0xff)); - DM9000_iow(DM9000_EPCR, 0x12); + dm9000_iow(DM9000_EPAR, offset); + dm9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); + dm9000_iow(DM9000_EPDRL, (val & 0xff)); + dm9000_iow(DM9000_EPCR, 0x12); udelay(8000); - DM9000_iow(DM9000_EPCR, 0); + dm9000_iow(DM9000_EPCR, 0); } #endif @@ -564,20 +564,20 @@ static void dm9000_get_enetaddr(struct eth_device *dev) Read a byte from I/O port */ static u8 -DM9000_ior(int reg) +dm9000_ior(int reg) { - DM9000_outb(reg, DM9000_IO); - return DM9000_inb(DM9000_DATA); + dm9000_outb(reg, DM9000_IO); + return dm9000_inb(DM9000_DATA); } /* Write a byte to I/O port */ static void -DM9000_iow(int reg, u8 value) +dm9000_iow(int reg, u8 value) { - DM9000_outb(reg, DM9000_IO); - DM9000_outb(value, DM9000_DATA); + dm9000_outb(reg, DM9000_IO); + dm9000_outb(value, DM9000_DATA); } /* @@ -589,11 +589,11 @@ dm9000_phy_read(int reg) u16 val; /* Fill the phyxcer register into REG_0C */ - DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); - DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ + dm9000_iow(DM9000_EPAR, DM9000_PHY | reg); + dm9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ udelay(100); /* Wait read complete */ - DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ - val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); + dm9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ + val = (dm9000_ior(DM9000_EPDRH) << 8) | dm9000_ior(DM9000_EPDRL); /* The read data keeps on REG_0D & REG_0E */ DM9000_DBG("dm9000_phy_read(0x%x): 0x%x\n", reg, val); @@ -608,14 +608,14 @@ dm9000_phy_write(int reg, u16 value) { /* Fill the phyxcer register into REG_0C */ - DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); + dm9000_iow(DM9000_EPAR, DM9000_PHY | reg); /* Fill the written data into REG_0D & REG_0E */ - DM9000_iow(DM9000_EPDRL, (value & 0xff)); - DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); - DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ + dm9000_iow(DM9000_EPDRL, (value & 0xff)); + dm9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); + dm9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ udelay(500); /* Wait write complete */ - DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ + dm9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ DM9000_DBG("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg, value); } -- 2.35.1

2 31

[PATCH] net: tftp: fix tftp server initialization
by Arjan Minzinga Zijlstra 12 Apr '22

12 Apr '22

Some globals where not properly initialized causing timeouts as data packets where not immediately acknowledged. Signed-off-by: Arjan Minzinga Zijlstra <arjan.minzingazijlstra(a)fox-it.com> --- net/tftp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/tftp.c b/net/tftp.c index 62a9648474..9d5fe2f2d9 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -912,6 +912,8 @@ void tftp_start_server(void) tftp_block_size = TFTP_BLOCK_SIZE; tftp_cur_block = 0; tftp_our_port = WELL_KNOWN_PORT; + tftp_windowsize = 1; + tftp_next_ack = tftp_windowsize; #ifdef CONFIG_TFTP_TSIZE tftp_tsize = 0; -- 2.25.1

2 2

Re: [PATCH] net: tftp: fix tftp server initialization
by Arjan Minzinga Zijlstra 12 Apr '22

12 Apr '22

> On Thu, Mar 31, 2022 at 2:50 PM Arjan Minzinga Zijlstra <arjan.minzingazijlstra(a)fox-it.com> wrote: > > Some globals where not properly initialized causing timeouts > > as data packets where not immediately acknowledged. > I don't see a scenario where these two variables will not be initialized. > Can you please elaborate ? These variables are only set on tftp oack packets (which are optional AFAIK) and in the tftp_start() function. However when running the tftpsrv cmd, tftp_start_server() is called, which didn't initialized said variables.

2 1

[PATCH] imx8mq: soc: Set the BYPASS ID SWAP bit (GPR10 bit 1)
by Peng Fan (OSS) 12 Apr '22

12 Apr '22

From: Peng Fan <peng.fan(a)nxp.com> Set the BYPASS ID SWAP bit (GPR10 bit 1). The ID SWAP function randomly make TZASC grant non-secure access to secure memory. TZASC ID SWAP should be bypassed by setting the bit TZASC_ID_SWAP_BYPASS(bit 1) in IOMUX_GPR10 register. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- arch/arm/mach-imx/imx8m/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 7397b99a1eee..404322cb69f1 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -72,7 +72,7 @@ void enable_tzc380(void) * According to TRM, TZASC_ID_SWAP_BYPASS should be set in * order to avoid AXI Bus errors when GPU is in use */ - if (is_imx8mm() || is_imx8mn() || is_imx8mp()) + if (is_imx8mq() || is_imx8mm() || is_imx8mn() || is_imx8mp()) setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS); /* -- 2.25.1

2 1

[PATCH 1/2] ARM: imx: imx8m: Add 933 MHz PLL settings
by Marek Vasut 12 Apr '22

12 Apr '22

Add settings for operating PLL at 933 MHz. This setting is useful in case the LPDDR4 DRAM should operate at 1866 MHz or 3733 MT/s. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 76132defc21..4db55f86081 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -48,6 +48,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) #ifdef CONFIG_SPL_BUILD static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), + PLL_1443X_RATE(933000000U, 311, 4, 1, 0), PLL_1443X_RATE(800000000U, 300, 9, 0, 0), PLL_1443X_RATE(750000000U, 250, 8, 0, 0), PLL_1443X_RATE(650000000U, 325, 3, 2, 0), -- 2.34.1

4 7

[PATCH v2 1/5] imx8mm-cl-iot-gate: Add SPL EEPROM support
by Fabio Estevam 12 Apr '22

12 Apr '22

From: Fabio Estevam <festevam(a)denx.de> imx8mm-cl-iot-gate supports multiple DDR sizes and models. The DDR type can be retrieved from the EEPROM, so add SPL code that can be used to get the DDR information. Based on the original code from Compulab's U-Boot. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- Changes since v1: - None board/compulab/imx8mm-cl-iot-gate/Makefile | 2 +- .../compulab/imx8mm-cl-iot-gate/eeprom_spl.c | 130 ++++++++++++++++++ 2 files changed, 131 insertions(+), 1 deletion(-) create mode 100644 board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c diff --git a/board/compulab/imx8mm-cl-iot-gate/Makefile b/board/compulab/imx8mm-cl-iot-gate/Makefile index 3a2bfc4dc4b1..3800b21a6fd0 100644 --- a/board/compulab/imx8mm-cl-iot-gate/Makefile +++ b/board/compulab/imx8mm-cl-iot-gate/Makefile @@ -8,6 +8,6 @@ obj-y += imx8mm-cl-iot-gate.o ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o eeprom_spl.o obj-y += ddr/ endif diff --git a/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c new file mode 100644 index 000000000000..ee6d2bb0016a --- /dev/null +++ b/board/compulab/imx8mm-cl-iot-gate/eeprom_spl.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* (C) Copyright 2019 CompuLab, Ltd. <www.compulab.co.il> */ + +#include <common.h> +#include <i2c.h> +#include <linux/kernel.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/mach-imx/gpio.h> +#include <asm-generic/gpio.h> +#include <asm/setup.h> +#include <linux/delay.h> + +#ifdef CONFIG_SPL_BUILD + +#define CONFIG_SYS_I2C_EEPROM_ADDR_P1 0x51 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +static iomux_v3_cfg_t const eeprom_pads[] = { + IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define EEPROM_WP_GPIO IMX_GPIO_NR(1, 13) + +static void cl_eeprom_we(int enable) +{ + static int done; + + if (done) { + gpio_direction_output(EEPROM_WP_GPIO, enable); + return; + } + + imx_iomux_v3_setup_multiple_pads(eeprom_pads, ARRAY_SIZE(eeprom_pads)); + gpio_request(EEPROM_WP_GPIO, "eeprom_wp"); + gpio_direction_output(EEPROM_WP_GPIO, enable); + done = 1; +} + +static int cl_eeprom_read(uint offset, uchar *buf, int len) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); + if (ret) { + printf("%s: Cannot find EEPROM: %d\n", __func__, ret); + return ret; + } + + return dm_i2c_read(dev, offset, buf, len); +} + +static int cl_eeprom_write(uint offset, uchar *buf, int len) +{ + struct udevice *dev; + int ret; + + cl_eeprom_we(1); + + ret = i2c_get_chip_for_busnum(1, CONFIG_SYS_I2C_EEPROM_ADDR_P1, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); + if (ret) { + printf("%s: Cannot find EEPROM: %d\n", __func__, ret); + return ret; + } + + return dm_i2c_write(dev, offset, buf, len); +} + +/* Reserved for fututre use area */ +#define BOARD_DDRINFO_OFFSET 0x40 +#define BOARD_DDR_SIZE 4 +static u32 board_ddrinfo = 0xdeadbeef; + +#define BOARD_DDRSUBIND_OFFSET 0x44 +#define BOARD_DDRSUBIND_SIZE 1 +static u8 board_ddrsubind = 0xff; + +#define BOARD_OSIZE_OFFSET 0x80 +#define BOARD_OSIZE_SIZE 4 +static u32 board_osize = 0xdeadbeef; + +#define BOARD_DDRINFO_VALID(A) ((A) != 0xdeadbeef) + +u32 cl_eeprom_get_ddrinfo(void) +{ + if (!BOARD_DDRINFO_VALID(board_ddrinfo)) { + if (cl_eeprom_read(BOARD_DDRINFO_OFFSET, (uchar *)&board_ddrinfo, BOARD_DDR_SIZE)) + return 0; + } + return board_ddrinfo; +}; + +u32 cl_eeprom_set_ddrinfo(u32 ddrinfo) +{ + if (cl_eeprom_write(BOARD_DDRINFO_OFFSET, (uchar *)&ddrinfo, BOARD_DDR_SIZE)) + return 0; + + board_ddrinfo = ddrinfo; + + return board_ddrinfo; +}; + +u8 cl_eeprom_get_subind(void) +{ + if (cl_eeprom_read(BOARD_DDRSUBIND_OFFSET, (uchar *)&board_ddrsubind, BOARD_DDRSUBIND_SIZE)) + return 0xff; + + return board_ddrsubind; +}; + +u8 cl_eeprom_set_subind(u8 ddrsubind) +{ + if (cl_eeprom_write(BOARD_DDRSUBIND_OFFSET, (uchar *)&ddrsubind, BOARD_DDRSUBIND_SIZE)) + return 0xff; + board_ddrsubind = ddrsubind; + + return board_ddrsubind; +}; + +/* override-size ifaces */ +u32 cl_eeprom_get_osize(void) +{ + if (cl_eeprom_read(BOARD_OSIZE_OFFSET, (uchar *)&board_osize, BOARD_OSIZE_SIZE)) + return 0; + + return board_osize; +}; +#endif -- 2.25.1

2 9

[PATCH v5 0/7] imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
by Ariel D'Alessandro 12 Apr '22

12 Apr '22

Introduce BSH SystemMaster (SMM) S2 board family, which consists of: iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. This patchset also adds support for NXP TJA11xx Ethernet PHYs. Changes in v5: * Export init_nand_clk() function. * Drop __ASSEMBLY__ in ddr config. * Init nand clk in spl, required when usb boot is forced. * Migrate symbols to defconfig. Changes in v4: * Add new Reviewed-by tags to patches. * Set atf-bl31 blob type in device tree binman configuration. Changes in v3: * Added nxp-c45-tja11xx driver. * Added ethernet support to iMX8MN BSH SMM S2 boards. Changes in v2: * Properly added MAINTAINERS entry. * Fixed binman configuration. * Picked device tree from kernel. * Removed CONFIG_SPL_BUILD anti-pattern in board config. * Removed downstream stuff in bootargs. * Added board documentation. Ariel D'Alessandro (4): phy: nxp-c45-tja11xx: Rename functions to be c45 tja11xx specific iopoll: Extend read_poll_timeout macro to support variable parameters net: phy: Add phy_modify() accessor bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards Michael Trimarchi (3): imx8m: add regs used by GPMI imx8m: add init_nand_clk net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver arch/arm/dts/Makefile | 2 + arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi | 423 ++++++++ .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 225 +++++ arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi | 15 + arch/arm/dts/imx8mn-bsh-smm-s2.dts | 48 + arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 + arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 80 ++ arch/arm/include/asm/arch-imx8m/clock.h | 1 + arch/arm/include/asm/arch-imx8m/imx-regs.h | 7 + arch/arm/mach-imx/imx8m/Kconfig | 15 + arch/arm/mach-socfpga/reset_manager_s10.c | 20 +- board/bsh/imx8mn_smm_s2/Kconfig | 49 + board/bsh/imx8mn_smm_s2/MAINTAINERS | 8 + board/bsh/imx8mn_smm_s2/Makefile | 13 + board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 941 ++++++++++++++++++ board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 941 ++++++++++++++++++ board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 23 + board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 8 + board/bsh/imx8mn_smm_s2/spl.c | 97 ++ configs/imx8mn_bsh_smm_s2_defconfig | 96 ++ configs/imx8mn_bsh_smm_s2pro_defconfig | 93 ++ doc/board/bsh/imx8mn_bsh_smm_s2.rst | 62 ++ doc/board/bsh/index.rst | 9 + doc/board/index.rst | 1 + drivers/mmc/rockchip_sdhci.c | 9 +- drivers/net/phy/Kconfig | 5 + drivers/net/phy/Makefile | 1 + drivers/net/phy/nxp-c45-tja11xx.c | 6 +- drivers/net/phy/nxp-tja11xx.c | 277 ++++++ drivers/net/phy/phy.c | 23 + include/configs/imx8mn_bsh_smm_s2.h | 51 + include/configs/imx8mn_bsh_smm_s2_common.h | 59 ++ include/configs/imx8mn_bsh_smm_s2pro.h | 35 + include/linux/iopoll.h | 12 +- include/phy.h | 3 + 35 files changed, 3651 insertions(+), 22 deletions(-) create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig create mode 100644 board/bsh/imx8mn_smm_s2/MAINTAINERS create mode 100644 board/bsh/imx8mn_smm_s2/Makefile create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg create mode 100644 board/bsh/imx8mn_smm_s2/spl.c create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig create mode 100644 doc/board/bsh/imx8mn_bsh_smm_s2.rst create mode 100644 doc/board/bsh/index.rst create mode 100644 drivers/net/phy/nxp-tja11xx.c create mode 100644 include/configs/imx8mn_bsh_smm_s2.h create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h -- 2.34.1

2 14

[PATCH] mtd: nand: mxs_nand_spl: Remove the page aligned access
by Ye Li 12 Apr '22

12 Apr '22

The mxs_nand_spl driver can support to read from page unaligned offset, so don't need to set bl_len to ask spl_load_simple_fit to handle the page unaligned access. Actually spl_load_simple_fit has two parts of reading: spl_simple_fit_read and spl_load_fit_image. The spl_load_fit_image can handle the page unaligned offset, but the spl_simple_fit_read can't do it. spl_simple_fit_read requires the FIT location at page aligned offset. Hence, remove the nand_get_mtd overwrite function from mxs_nand_spl to use page unaligned read by driver. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/mtd/nand/raw/mxs_nand_spl.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 9e0b8afb..59a67ee 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -283,11 +283,6 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) return 0; } -struct mtd_info *nand_get_mtd(void) -{ - return mtd; -} - int nand_default_bbt(struct mtd_info *mtd) { return 0; -- 2.7.4

3 2

[PATCH] pinctrl: nxp: don't automatically select DEVRES
by Angus Ainslie 12 Apr '22

12 Apr '22

If we select DEVRES here then it breaks building an imx8m SPL without DEVRES support. Signed-off-by: Angus Ainslie <angus(a)akkea.ca> --- drivers/pinctrl/nxp/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index 4fb0916a37..3657e9deb9 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -92,7 +92,6 @@ config PINCTRL_IMX8 config PINCTRL_IMX8M bool "IMX8M pinctrl driver" depends on ARCH_IMX8M && PINCTRL_FULL - select DEVRES select PINCTRL_IMX help Say Y here to enable the imx8m pinctrl driver -- 2.25.1

2 1

[PATCH 0/2] enable DM_SERIAL on imx8mn-evk and imx8mn-ddr4-evk
by Heiko Thiery 12 Apr '22

12 Apr '22

I was only able to test it on a 8MNANOD3L-EVK board. Please help testing this change on the other 2 eval boards (8MNANOLPD4-EVK, 8MNANOD4-EVK). Heiko Thiery (2): ARM: imx: imx8mn-evk: enable DM_SERIAL ARM: imx: imx8mn-ddr4-evk: enable DM_SERIAL configs/imx8mn_ddr4_evk_defconfig | 2 ++ configs/imx8mn_evk_defconfig | 2 ++ 2 files changed, 4 insertions(+) -- 2.30.2

3 5