March 2022 - U-Boot

[PATCH 0/2] U-Boot ENV in EXT4 support for Expressobin (revised)
by Rogier Stam 11 May '22

11 May '22

Hi Per comments of Stefan I have split the patch in two: - one for env file changes - one for espressobin related changes Let me know if any other changes are needed. Regards Rogier Rogier Stam (2): Fix Espressobin build for configs where ENV is not in SPI Add SCSI scan for ENV in EXT4 or FAT arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi | 2 ++ board/Marvell/mvebu_armada-37xx/board.c | 4 +++- env/ext4.c | 5 +++++ env/fat.c | 5 +++++ 4 files changed, 15 insertions(+), 1 deletion(-) -- 2.7.4

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[PATCH 0/8] stm32mp: command stm32prog improvements
by Patrick Delaunay 10 May '22

10 May '22

Several patches to improve the command stm32prog command. This command is used to program the STMicroelectronics boards with the tools STM32CubeProgrammer and flashlayout file. Patrick Delaunay (8): stm32mp: stm32prog: fix comment stm32mp: stm32prog: add CONFIG_CMD_STM32PROG_OTP stm32mp: stm32prog: add TEE support in stm32prog command stm32mp: stm32prog: add support of STM32IMAGE version 2 stm32mp: stm32prog: add support of UUID for FIP partition stm32mp: stm32prog: handle interruption during the first enumeration stm32mp: stm32prog: handle U-Boot script in flashlayout alternate stm32mp: stm32prog: handle flashlayout without STM32 image header arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig | 7 + .../cmd_stm32prog/cmd_stm32prog.c | 13 +- .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 418 ++++++++++++++---- .../mach-stm32mp/cmd_stm32prog/stm32prog.h | 47 +- .../cmd_stm32prog/stm32prog_usb.c | 9 +- 5 files changed, 378 insertions(+), 116 deletions(-) -- 2.25.1

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[PATCH v1 1/1] gpio: npcm: Add support for Nuvoton NPCM SoCs
by Stanley Chu 05 May '22

05 May '22

Add Nuvoton BMC NPCM7xx/NPCM8xx gpio driver Signed-off-by: Stanley Chu <yschu(a)nuvoton.com> --- drivers/gpio/Kconfig | 7 +++ drivers/gpio/Makefile | 1 + drivers/gpio/npcm_gpio.c | 123 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 131 insertions(+) create mode 100644 drivers/gpio/npcm_gpio.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8d0e47c67d..e1a1f1c4db 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -247,6 +247,13 @@ config MXS_GPIO help Support GPIO controllers on i.MX23 and i.MX28 platforms +config NPCM_GPIO + bool "Nuvoton NPCM GPIO driver" + depends on DM_GPIO + help + Support GPIO controllers on Nuvovon NPCM SoCs. + NPCM7xx/NPCM8xx contain 8 GPIO banks, each bank contains 32 pins. + config OMAP_GPIO bool "TI OMAP GPIO driver" depends on ARCH_OMAP2PLUS diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 63e9be6034..a42ae77285 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o +obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o obj-$(CONFIG_PCA953X) += pca953x.o obj-$(CONFIG_PCA9698) += pca9698.o obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o diff --git a/drivers/gpio/npcm_gpio.c b/drivers/gpio/npcm_gpio.c new file mode 100644 index 0000000000..8afd57fa8e --- /dev/null +++ b/drivers/gpio/npcm_gpio.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Nuvoton Technology Corp. + */ + +#include <common.h> +#include <dm.h> +#include <asm/gpio.h> +#include <linux/io.h> + +#define NPCM_GPIOS_PER_BANK 32 + +/* Register offsets */ +#define GPIO_DIN 0x4 /* RO - Data In */ +#define GPIO_DOUT 0xC /* RW - Data Out */ +#define GPIO_OE 0x10 /* RW - Output Enable */ +#define GPIO_IEM 0x58 /* RW - Input Enable Mask */ +#define GPIO_OES 0x70 /* WO - Output Enable Register Set */ +#define GPIO_OEC 0x74 /* WO - Output Enable Register Clear */ + +struct npcm_gpio_priv { + void __iomem *base; +}; + +static int npcm_gpio_direction_input(struct udevice *dev, unsigned int offset) +{ + struct npcm_gpio_priv *priv = dev_get_priv(dev); + + writel(BIT(offset), priv->base + GPIO_OEC); + setbits_le32(priv->base + GPIO_IEM, BIT(offset)); + + return 0; +} + +static int npcm_gpio_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + struct npcm_gpio_priv *priv = dev_get_priv(dev); + + clrbits_le32(priv->base + GPIO_IEM, BIT(offset)); + writel(BIT(offset), priv->base + GPIO_OES); + + if (value) + setbits_le32(priv->base + GPIO_DOUT, BIT(offset)); + else + clrbits_le32(priv->base + GPIO_DOUT, BIT(offset)); + + return 0; +} + +static int npcm_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct npcm_gpio_priv *priv = dev_get_priv(dev); + + if (readl(priv->base + GPIO_IEM) & BIT(offset)) + return !!(readl(priv->base + GPIO_DIN) & BIT(offset)); + + if (readl(priv->base + GPIO_OE) & BIT(offset)) + return !!(readl(priv->base + GPIO_DOUT) & BIT(offset)); + + return -EINVAL; +} + +static int npcm_gpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct npcm_gpio_priv *priv = dev_get_priv(dev); + + if (value) + setbits_le32(priv->base + GPIO_DOUT, BIT(offset)); + else + clrbits_le32(priv->base + GPIO_DOUT, BIT(offset)); + + return 0; +} + +static int npcm_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct npcm_gpio_priv *priv = dev_get_priv(dev); + + if (readl(priv->base + GPIO_IEM) & BIT(offset)) + return GPIOF_INPUT; + + if (readl(priv->base + GPIO_OE) & BIT(offset)) + return GPIOF_OUTPUT; + + return GPIOF_FUNC; +} + +static const struct dm_gpio_ops npcm_gpio_ops = { + .direction_input = npcm_gpio_direction_input, + .direction_output = npcm_gpio_direction_output, + .get_value = npcm_gpio_get_value, + .set_value = npcm_gpio_set_value, + .get_function = npcm_gpio_get_function, +}; + +static int npcm_gpio_probe(struct udevice *dev) +{ + struct npcm_gpio_priv *priv = dev_get_priv(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + uc_priv->gpio_count = NPCM_GPIOS_PER_BANK; + uc_priv->bank_name = dev->name; + + return 0; +} + +static const struct udevice_id npcm_gpio_match[] = { + { .compatible = "nuvoton,npcm845-gpio" }, + { .compatible = "nuvoton,npcm750-gpio" }, + { } +}; + +U_BOOT_DRIVER(npcm_gpio) = { + .name = "npcm_gpio", + .id = UCLASS_GPIO, + .of_match = npcm_gpio_match, + .probe = npcm_gpio_probe, + .priv_auto = sizeof(struct npcm_gpio_priv), + .ops = &npcm_gpio_ops, +}; -- 2.17.1

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[PATCH] w1: w1-gpio: Loosen timings to improve cold boot reliability
by Chris Morgan 05 May '22

05 May '22

From: Chris Morgan <macromorgan(a)hotmail.com> On my NTC CHIP whenever I do a cold boot any attached DIPs cannot be found. Rebooting on the other hand appears to fix the issue. I found that if I modified the timing slightly (but still within spec) the w1 identification on cold boot became far more reliable. Signed-off-by: Chris Morgan <macromorgan(a)hotmail.com> --- drivers/w1/w1-gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/w1/w1-gpio.c b/drivers/w1/w1-gpio.c index 9346f810ce..5565de2a92 100644 --- a/drivers/w1/w1-gpio.c +++ b/drivers/w1/w1-gpio.c @@ -22,8 +22,8 @@ #define W1_TIMING_E 9 #define W1_TIMING_F 55 #define W1_TIMING_G 0 -#define W1_TIMING_H 480 -#define W1_TIMING_I 70 +#define W1_TIMING_H 600 +#define W1_TIMING_I 100 #define W1_TIMING_J 410 struct w1_gpio_pdata { -- 2.30.2

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[PATCH 0/7] sunxi: Fix U-Boot proper SPI operation
by Andre Przywara 05 May '22

05 May '22

Hi, despite U-Boot supporting SPI on Allwinner chips and SPI flash in general for a while, it wasn't really working well for many sunxi boards. Booting from SPI is handled by separate SPL code, which works fine, but the "sf" command in U-Boot proper is often just not operational. This series tries to improve the situation, by: - cleaning up the SPI Kconfig situation for sunxi (patch 2) - adding support for environment in SPI flash (patch 3-5) - trying to enable more boards for U-Boot-proper SPI flash (patch 6) As an added bonus there is some whacky code to make the SPI flash usable in Linux on H6 boards. Marking this as RFC. Actually even after this series many boards still miss out, because they are lacking the required "spi0" alias in the DT. We could go with *-u-boot.dtsi fixes for now (as the SoPine does), but even mainline DT support wouldn't help, as we are somewhat stuck with DT updates. But that's a story for another time, let's get this SPI support fixed first. Cheers, Andre Andre Przywara (6): sunxi: Kconfig: Fix up SPI configuration env: sunxi: Define location in SPI flash sunxi: use boot source for determining environment location env: sunxi: enable ENV_IS_IN_SPI_FLASH sunxi: boards: Enable SPI flash support in U-Boot proper sunxi: H6: Enable SPI0 in DT when no eMMC is used Daniel Wagenknecht (1): sunxi: SPI: fix pinmuxing for Allwinner H6 SoCs arch/arm/Kconfig | 2 + arch/arm/mach-sunxi/Kconfig | 13 ++- board/sunxi/board.c | 101 +++++++++++++++++++++-- configs/libretech_all_h3_it_h5_defconfig | 2 - configs/libretech_all_h5_cc_h5_defconfig | 2 - configs/oceanic_5205_5inmfd_defconfig | 1 + configs/orangepi_pc2_defconfig | 2 + configs/orangepi_r1_defconfig | 2 + configs/orangepi_win_defconfig | 2 + configs/orangepi_zero2_defconfig | 2 + configs/orangepi_zero_defconfig | 2 + configs/pine64-lts_defconfig | 2 + configs/pine_h64_defconfig | 3 + configs/pinecube_defconfig | 2 + configs/sopine_baseboard_defconfig | 1 + drivers/spi/spi-sunxi.c | 3 +- env/Kconfig | 7 +- 17 files changed, 131 insertions(+), 18 deletions(-) -- 2.25.1

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[PATCH v1] imx: imx8qm-rom7720: switch to binman
by Oliver Graute 03 May '22

03 May '22

Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> --- arch/arm/dts/imx8qm-rom7720-a1.dts | 1 + arch/arm/dts/imx8qm-u-boot.dtsi | 133 ++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 1 + .../advantech/imx8qm_rom7720_a1/imximage.cfg | 4 +- configs/imx8qm_rom7720_a1_4G_defconfig | 2 +- doc/board/advantech/imx8qm-rom7720-a1.rst | 3 +- 6 files changed, 139 insertions(+), 5 deletions(-) create mode 100644 arch/arm/dts/imx8qm-u-boot.dtsi diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts b/arch/arm/dts/imx8qm-rom7720-a1.dts index d1f2fff869..332d441c6d 100644 --- a/arch/arm/dts/imx8qm-rom7720-a1.dts +++ b/arch/arm/dts/imx8qm-rom7720-a1.dts @@ -10,6 +10,7 @@ /memreserve/ 0x80000000 0x00020000; #include "fsl-imx8qm.dtsi" +#include "imx8qm-u-boot.dtsi" / { model = "Advantech iMX8QM Qseven series"; diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi b/arch/arm/dts/imx8qm-u-boot.dtsi new file mode 100644 index 0000000000..5da420ece6 --- /dev/null +++ b/arch/arm/dts/imx8qm-u-boot.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +/ { + binman: binman { + multiple-images; + }; +}; + +&binman { + u-boot-spl-ddr { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; + }; + + spl { + filename = "spl.bin"; + + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x100000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + fit,fdt-list = "of-list"; + #address-cells = <1>; + + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + load = <CONFIG_SYS_TEXT_BASE>; + type = "standalone"; + + uboot_blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; + }; + }; + + atf { + arch = "arm64"; + compression = "none"; + description = "ARM Trusted Firmware"; + entry = <0x00910000>; + load = <0x00091000>; + type = "firmware"; + + atf_blob { + filename = "bl31.bin"; + type = "blob-ext"; + }; + }; + + scfw { + arch = "arm64"; + compression = "none"; + description = "System Controler Firmware"; + type = "firmware"; + + scfw_blob { + filename = "mx8qm-val-scfw-tcm.bin"; + type = "blob-ext"; + }; + }; + + seco { + arch = "arm64"; + compression = "none"; + description = "Seco Firmware"; + type = "firmware"; + + seco_blob { + filename = "mx8qm-ahab-container.img"; + type = "blob-ext"; + }; + }; + + fdt { + filename = "imx8qm-rom7720-a1"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + filename = "imx8qm-rom7720-a1"; + fdt = "fdt"; + firmware = "uboot"; + loadables = "atf"; + }; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl { + filename = "spl.bin"; + offset = <0x0>; + type = "blob-ext"; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index b43739e5c6..b42b985cdf 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -81,6 +81,7 @@ config TARGET_CONGA_QMX8 config TARGET_IMX8QM_ROM7720_A1 bool "Support i.MX8QM ROM-7720-A1" + select BINMAN select BOARD_LATE_INIT select SUPPORT_SPL select IMX8QM diff --git a/board/advantech/imx8qm_rom7720_a1/imximage.cfg b/board/advantech/imx8qm_rom7720_a1/imximage.cfg index e324c7ca37..58eeef54f6 100644 --- a/board/advantech/imx8qm_rom7720_a1/imximage.cfg +++ b/board/advantech/imx8qm_rom7720_a1/imximage.cfg @@ -5,8 +5,8 @@ #define __ASSEMBLY__ -/* Boot from SD, sector size 0x400 */ -BOOT_FROM SD 0x400 +BOOT_FROM sd + /* SoC type IMX8QM */ SOC_TYPE IMX8QM /* Append seco container image */ diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig index fb43fa1962..26afa4f8d7 100644 --- a/configs/imx8qm_rom7720_a1_4G_defconfig +++ b/configs/imx8qm_rom7720_a1_4G_defconfig @@ -18,7 +18,7 @@ CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_BOOTDELAY=3 CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/doc/board/advantech/imx8qm-rom7720-a1.rst b/doc/board/advantech/imx8qm-rom7720-a1.rst index bd4be1dbeb..953cf01fde 100644 --- a/doc/board/advantech/imx8qm-rom7720-a1.rst +++ b/doc/board/advantech/imx8qm-rom7720-a1.rst @@ -57,8 +57,7 @@ Build U-Boot $ export ATF_LOAD_ADDR=0x80000000 $ export BL33_LOAD_ADDR=0x80020000 $ make imx8qm_rom7720_a1_4G_defconfig - $ make u-boot.bin - $ make flash.bin + $ make Flash the binary into the SD card --------------------------------- -- 2.17.1

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[PATCH u-boot-marvell 0/8] Turris Omnia: Add support for configuring mSATA and WWAN slots via env variables
by Pali Rohár 02 May '22

02 May '22

Some mPCIe cards are broken and their PIN 43 incorrectly that card is mSATA. U-Boot SPL on Turris Omnia is using PIN 43 for configuring PCIe vs SATA functionality on SerDes. Allow to configure functionality via additional env variable "omnia_msata_slot" which may override PIN 43. To force PCIe mode for broken MiniPCIe cards, call U-Boot commands: => setenv omnia_msata_slot pcie => saveenv => reset PCI-SIG in PCIe Mini CEM 2.1 spec added support for USB3.0 mode to mPCIe cards. PCIe and USB3.0 functions share same pins (like SATA pins on mSATA with PCIe on mPCIe) and therefore only one function may be active at the same time. This mode was introduced by PCI-SIG specially for LTE/5G modems. One mPCIe slot on Turris Omnia is connected to A385 CPU SerDes which can be configured for PCIe or USB3.0 function. It is the slot with SIM card suitable for cellular modems. As PCIe Mini CEM 2.1 spec say that detection of PCIe vs USB3.0 functionality is platform specific, add a new U-Boot variable "omnia_wwan_slot" for configuring functionality in this slot. By default PCIe is used like before. To set this WWAN slot to USB3.0 mode, call U-Boot commands: => setenv omnia_wwan_slot usb3 => saveenv => reset Pali Rohár (8): env: sf: Allow to use env_sf_init_addr() at any stage arm: mvebu: turris_omnia: Provide env_sf_get_env_addr() function arm: mvebu: turris_omnia: Enable ENV support in SPL arm: mvebu: turris_omnia: Define only one serdes map variable arm: mvebu: turris_omnia: Allow to configure mSATA slot via env variable arm: mvebu: turris_omnia: Extract code for disabling sata/pcie arm: mvebu: turris_omnia: Signal error when sata/pcie DT mode arm: mvebu: turris_omnia: Add support for USB3.0 mode in WWAN MiniPCIe slot board/CZ.NIC/turris_omnia/turris_omnia.c | 207 +++++++++++++++++------ configs/turris_omnia_defconfig | 1 + env/sf.c | 22 +-- 3 files changed, 163 insertions(+), 67 deletions(-) -- 2.20.1

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[PATCH v4 00/11] enable menu-driven boot device selection
by Masahisa Kojima 28 Apr '22

28 Apr '22

This patch series adds the menu-driven boot device selection, by extending the existing "bootmenu" to include UEFI and distro_boot related entries, and supports menu-driven UEFI boot variable maintenance. This patch series also includes the removable media support that UEFI specification requires to support. The menu example is as follows. *** U-Boot Boot Menu *** bootmenu_00 : Boot 1. kernel bootmenu_01 : Boot 2. kernel bootmenu_02 : Reset board UEFI BOOT0000 : debian UEFI BOOT0001 : ubuntu UEFI BOOT0002 : mmc0:1 UEFI BOOT0003 : mmc0:2 UEFI BOOT0004 : nvme0:1 UEFI BOOT0005 : nvme0:2 UEFI BOOT0006 : usb0:2 UEFI BOOT0007 : usb1:1 UEFI BOOT0008 : usb1:2 distro_boot : usb0 distro_boot : scsi0 distro_boot : virtio0 distro_boot : dhcp Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit [Major changes from RFC v3] - add Kconfig option to disable U-Boot console - add UEFI boot variable maintenance feature - support removable media support and user selection - app bootmenu enhancement documentation [How to run on QEMU(arm64)] 1) clone source code $ git clone https://git.linaro.org/people/masahisa.kojima/u-boot.git \ -b kojima/bootmenu_v4_upstream_0324 --depth 1 2) prepare U-Boot .config $ make qemu_arm64_menuconfig then, enable CONFIG_CMD_BOOTMENU and CONFIG_AUTOBOOT_MENU_SHOW 3) run on QEMU(arm64) example $ qemu-system-aarch64 -machine virt,gic-version=3 -cpu cortex-a57 -m 4G -nographic \ -no-acpi -bios ./u-boot.bin -hda xxx.img AKASHI Takahiro (2): efi_loader: export efi_locate_device_handle() efi_loader: bootmgr: add booting from removable media Masahisa Kojima (9): bootmenu: fix menu API error handling lib/charset: add u16_strlcat() function test: unit test for u16_strlcat() menu: always show the menu regardless of the number or entry bootmenu: add UEFI and disto_boot entries bootmenu: factor out the user input handling efi_loader: add menu-driven UEFI Boot Variable maintenance bootmenu: add removable media entries doc:bootmenu: add UEFI boot variable and distro boot support cmd/Kconfig | 10 + cmd/bootmenu.c | 678 +++++++---- common/menu.c | 139 ++- doc/usage/bootmenu.rst | 65 ++ include/charset.h | 15 + include/config_distro_bootcmd.h | 14 +- include/efi_default_filename.h | 26 + include/efi_loader.h | 63 ++ include/menu.h | 20 + lib/charset.c | 21 + lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_bootmenu_maintenance.c | 1244 +++++++++++++++++++++ lib/efi_loader/efi_bootmgr.c | 50 +- lib/efi_loader/efi_boottime.c | 59 +- lib/efi_loader/efi_console.c | 81 ++ lib/efi_loader/efi_disk.c | 11 + lib/efi_loader/efi_file.c | 75 +- test/unicode_ut.c | 45 + 18 files changed, 2357 insertions(+), 260 deletions(-) create mode 100644 include/efi_default_filename.h create mode 100644 lib/efi_loader/efi_bootmenu_maintenance.c -- 2.17.1

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[PATCH] mtd: spi-nor-ids: Add support for W25Q512JV
by Dhananjay Phadke 28 Apr '22

28 Apr '22

Add support for Winbond W25Q512JV 64MB SPI NOR flash. https://www.digikey.com/en/product-highlight/w/winbond/w25q512jv-512-mb-ser… Signed-off-by: Dhananjay Phadke <dphadke(a)linux.microsoft.com> --- drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index b551ebd75e..017b165141 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -355,6 +355,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q512jv", 0xef7020, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | -- 2.25.1

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[PATCH] rockchip: rk3399: Add Nanopi M4V2 board support
by Shuying Li 25 Apr '22

25 Apr '22

From: Libunko <libunko(a)qq.com> Add initial support for Nanopi M4V2 board. Specification - Rockchip RK3399 - Dual-Channel 4GB LPDDR4 - SD card slot - eMMC socket - RTL8211E 1Gbps - AP6356S WiFI/BT - HDMI In/Out, MIPI DSI/CSI - USB 3.0 x4 - USB Type C power and data - GPIO1, GPIO2 expansion ports - DC5V/3A Signed-off-by: Shuying Li <libunko(a)qq.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-m4v2-u-boot.dtsi | 7 +++ arch/arm/dts/rk3399-nanopi-m4v2.dts | 67 +++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 ++ configs/nanopi-m4v2-rk3399_defconfig | 61 +++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 6 files changed, 143 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-m4v2-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-m4v2.dts create mode 100644 configs/nanopi-m4v2-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f8f529435b..7e8dfcef88 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -130,6 +130,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ rk3399-nanopi-m4-2gb.dtb \ + rk3399-nanopi-m4v2.dtb \ rk3399-nanopi-neo4.dtb \ rk3399-orangepi.dtb \ rk3399-pinebook-pro.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-m4v2-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-m4v2-u-boot.dtsi new file mode 100644 index 0000000000..ff8e99cb7f --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4v2-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Shuying Li <libunko(a)qq.com> + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-m4v2.dts b/arch/arm/dts/rk3399-nanopi-m4v2.dts new file mode 100644 index 0000000000..03d956d2c4 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4v2.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPi M4V2 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + * Copyright (C) 2020 Shuying Li <libunko(a)qq.com> + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi M4V2"; + compatible = "friendlyarm,nanopi-m4v2", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2: vcc5v0-usb2 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb2"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_core>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_usb2>; +}; + +&vbus_typec { + regulator-always-on; + vin-supply = <&vdd_5v>; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 4c889e06a6..9967d68a88 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -49,6 +49,12 @@ S: Maintained F: configs/nanopi-m4-2gb-rk3399_defconfig F: arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi +NANOPC-M4V2 +M: Shuying Li <libunko(a)qq.com> +S: Maintained +F: configs/nanopi-m4v2-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-m4v2-u-boot.dtsi + NANOPI-NEO4 M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained diff --git a/configs/nanopi-m4v2-rk3399_defconfig b/configs/nanopi-m4v2-rk3399_defconfig new file mode 100644 index 0000000000..d5c58d549f --- /dev/null +++ b/configs/nanopi-m4v2-rk3399_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4v2" +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4v2.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 8c92de0c92..25746f1a2e 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -61,6 +61,7 @@ List of mainline supported rockchip boards: - Firefly ROC-RK3399-PC - FriendlyElec NanoPC-T4 (nanopc-t4-rk3399) - FriendlyElec NanoPi M4 (nanopi-m4-rk3399) + - FriendlyElec NanoPi M4V2 (nanopi-m4v2-rk3399) - FriendlyARM NanoPi NEO4 (nanopi-neo4-rk3399) - Google Bob (chromebook_bob) - Khadas Edge (khadas-edge-rk3399) -- 2.25.1

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