March 2022 - U-Boot

[PATCH v3] usb: dwc2: handle return code of dev_read_size() in of to, plat function
by Wolfgang Grandegger 14 Mar '22

14 Mar '22

dev_read_size() returns -EINVAL (-22) if the property "g-tx-fifo-size" does not exist. If that's the case, we now keep the default value of 0. Signed-off-by: Wolfgang Grandegger <wg(a)aries-embedded.de> --- Changes since v2: - fix compiler error using latest U-Boot version Changes since v1: - removed unrelated changes (missing empty line) - improved commit message drivers/usb/gadget/dwc2_udc_otg.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index 2748270ad6..77988f78ab 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -996,8 +996,9 @@ static int dwc2_udc_otg_of_to_plat(struct udevice *dev) plat->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0); plat->np_tx_fifo_sz = dev_read_u32_default(dev, "g-np-tx-fifo-size", 0); - plat->tx_fifo_sz_nb = - dev_read_size(dev, "g-tx-fifo-size") / sizeof(u32); + ret = dev_read_size(dev, "g-tx-fifo-size"); + if (ret > 0) + plat->tx_fifo_sz_nb = ret / sizeof(u32); if (plat->tx_fifo_sz_nb > DWC2_MAX_HW_ENDPOINTS) plat->tx_fifo_sz_nb = DWC2_MAX_HW_ENDPOINTS; if (plat->tx_fifo_sz_nb) { -- 2.28.0

2 1

[PATCH] drivers/adc/rockchip-saradc: remove double semi-colon
by Giulio Benetti 14 Mar '22

14 Mar '22

Signed-off-by: Giulio Benetti <giulio.benetti(a)benettiengineering.com> --- drivers/adc/rockchip-saradc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index e464d33f22..e0cbab6aa0 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -131,7 +131,7 @@ int rockchip_saradc_of_to_plat(struct udevice *dev) } priv->data = data; - uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;; + uc_pdata->data_mask = (1 << priv->data->num_bits) - 1; uc_pdata->data_format = ADC_DATA_FORMAT_BIN; uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5; uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1; -- 2.25.1

2 4

[PATCH v2] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON when necessary
by haibo.chen＠nxp.com 14 Mar '22

14 Mar '22

From: Haibo Chen <haibo.chen(a)nxp.com> After commit f132aab40327 ("Revert "mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it involve issue in mmc_switch_voltage(), because of the special design of usdhc. For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these are reserved bits(Though RM contain the definition of these bits, but actually internal IC logic do not implement, already confirm with IC team). Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card clock output. Here is the definition of this bit in RM: [8] FRC_SDCLK_ON Force CLK output active Do not set this bit to 1 unless it is necessary. Also, make sure that this bit is cleared when uSDHC’s clock is about to be changed (frequency change, clock source change, or delay chain tuning). 0b - CLK active or inactive is fully controlled by the hardware. 1b - Force CLK active In default, the FRC_SDCLK_ON is 0. This means, when there is no command or data transfer on bus, hardware will gate off the card clock. But in some case, we need the card clock keep on. Take IO voltage 1.8v switch as example, after IO voltage change to 1.8v, spec require gate off the card clock for 5ms, and gate on the clock back, once detect the card clock on, then the card will draw the dat0 to high immediately. If there is not clock gate off/on behavior, some card will keep the dat0 to low level. This is the reason we fail in mmc_switch_voltage(). To fix this issue, and concern that this is only the fsl usdhc hardware design limitation, set the bit FRC_SDCLK_ON in the beginning of the wait_dat0() and clear it in the end. To make sure the 1.8v IO voltage switch process align with SD specification. For standard tuning process, usdhc specification also require the card clock keep on, so also add these behavior in fsl_esdhc_execute_tuning(). Reviewed-by: Marek Vasut <marex(a)denx.de> Tested-by: Fabio Estevam <festevam(a)gmail.com> Signed-off-by: Haibo Chen <haibo.chen(a)nxp.com> --- drivers/mmc/fsl_esdhc_imx.c | 25 ++++++++++++++++++++++--- include/fsl_esdhc_imx.h | 2 ++ 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 9299635f50..e0108144e7 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -831,13 +831,16 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) struct mmc *mmc = &plat->mmc; u32 irqstaten = esdhc_read32(&regs->irqstaten); u32 irqsigen = esdhc_read32(&regs->irqsigen); - int i, ret = -ETIMEDOUT; - u32 val, mixctrl; + int i, err, ret = -ETIMEDOUT; + u32 val, mixctrl, tmp; /* clock tuning is not needed for upto 52MHz */ if (mmc->clock <= 52000000) return 0; + /* make sure the card clock keep on */ + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */ if (priv->flags & ESDHC_FLAG_STD_TUNING) { val = esdhc_read32(&regs->autoc12err); @@ -897,6 +900,12 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) esdhc_stop_tuning(mmc); + /* change to default setting, let host control the card clock */ + esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + err = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (err) + dev_warn(dev, "card clock not gate off as expect.\n"); + return ret; } #endif @@ -1555,14 +1564,24 @@ static int __maybe_unused fsl_esdhc_set_enhanced_strobe(struct udevice *dev) static int fsl_esdhc_wait_dat0(struct udevice *dev, int state, int timeout_us) { - int ret; + int ret, err; u32 tmp; struct fsl_esdhc_priv *priv = dev_get_priv(dev); struct fsl_esdhc *regs = priv->esdhc_regs; + /* make sure the card clock keep on */ + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, !!(tmp & PRSSTAT_DAT0) == !!state, timeout_us); + + /* change to default setting, let host control the card clock */ + esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + err = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (err) + dev_warn(dev, "card clock not gate off as expect.\n"); + return ret; } diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index 2153f29bef..b8efd2a166 100644 --- a/include/fsl_esdhc_imx.h +++ b/include/fsl_esdhc_imx.h @@ -37,6 +37,7 @@ #define VENDORSPEC_HCKEN 0x00001000 #define VENDORSPEC_IPGEN 0x00000800 #define VENDORSPEC_INIT 0x20007809 +#define VENDORSPEC_FRC_SDCLK_ON 0x00000100 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) @@ -94,6 +95,7 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_SDOFF (0x00000080) #define PRSSTAT_SDSTB (0X00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) -- 2.17.1

4 4

[PATCH v2] usb: dwc2: handle return code of dev_read_size() in of to, plat function
by Wolfgang Grandegger 14 Mar '22

14 Mar '22

dev_read_size() returns -EINVAL (-22) if the property "g-tx-fifo-size" does not exist. If that's the case, we now keep the default value of 0. Signed-off-by: Wolfgang Grandegger <wg(a)aries-embedded.de> --- Changes since v1: - removed unrelated changes (missing empty line) - improved commit message drivers/usb/gadget/dwc2_udc_otg.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index 2748270..12e91bb 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -996,8 +996,9 @@ static int dwc2_udc_otg_of_to_plat(struct udevice *dev) plat->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0); plat->np_tx_fifo_sz = dev_read_u32_default(dev, "g-np-tx-fifo-size", 0); - plat->tx_fifo_sz_nb = - dev_read_size(dev, "g-tx-fifo-size") / sizeof(u32); + ret = dev_read_size(dev, "g-tx-fifo-size"); + if (ret > 0) + platdata->tx_fifo_sz_nb = ret / sizeof(u32); if (plat->tx_fifo_sz_nb > DWC2_MAX_HW_ENDPOINTS) plat->tx_fifo_sz_nb = DWC2_MAX_HW_ENDPOINTS; if (plat->tx_fifo_sz_nb) { -- 1.9.1

2 3

[PATCH 1/2] arm64: dts: rk3399-rock-pi-4b-u-boot: add optee node
by Peter Griffin 14 Mar '22

14 Mar '22

Allow u-boot to probe optee so we can access secure os from the bootloader. Signed-off-by: Peter Griffin <peter.griffin(a)linaro.org> --- arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi index 85ee5770ad..95ca99ecbc 100644 --- a/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi @@ -4,3 +4,13 @@ */ #include "rk3399-rock-pi-4-u-boot.dtsi" + +/ { + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + +}; -- 2.25.1

3 4

[PATCH 1/2] arm64: dts: rk3399-rock-pi-4b-u-boot: add optee node
by Peter Griffin 14 Mar '22

14 Mar '22

Allow u-boot to probe optee so we can access secure os from the bootloader. Signed-off-by: Peter Griffin <peter.griffin(a)linaro.org> --- arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi index 85ee5770ad..95ca99ecbc 100644 --- a/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi @@ -4,3 +4,13 @@ */ #include "rk3399-rock-pi-4-u-boot.dtsi" + +/ { + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + +}; -- 2.25.1

2 1

[PATCH v2] adc: rockchip-saradc: add support for getting reference voltage value
by Peter Cai 14 Mar '22

14 Mar '22

Mirroring commit 97ab802aa36f ("adc: meson-saradc: add support for getting reference voltage value") for meson-saradc, this adds support for getting the "vref-supply" regulator and register it as the ADC's reference voltage regulator, so clients can translate sampled ADC values to voltage. Signed-off-by: Peter Cai <peter(a)typeblog.net> Reviewed-by: John Keeping <john(a)metanate.com> Tested-by: John Keeping <john(a)metanate.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Philipp Tomsich <philipp.tomsich(a)vrull.eu> Cc: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v2: - Reordered local variables in `rockchip_saradc_probe`. --- drivers/adc/rockchip-saradc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index e464d33f2267..4007188133c8 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -13,6 +13,7 @@ #include <asm/io.h> #include <linux/bitops.h> #include <linux/err.h> +#include <power/regulator.h> #define SARADC_CTRL_CHN_MASK GENMASK(2, 0) #define SARADC_CTRL_POWER_CTRL BIT(3) @@ -100,8 +101,11 @@ int rockchip_saradc_stop(struct udevice *dev) int rockchip_saradc_probe(struct udevice *dev) { + struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); struct rockchip_saradc_priv *priv = dev_get_priv(dev); + struct udevice *vref; struct clk clk; + int vref_uv; int ret; ret = clk_get_by_index(dev, 0, &clk); @@ -114,6 +118,23 @@ int rockchip_saradc_probe(struct udevice *dev) priv->active_channel = -1; + ret = device_get_supply_regulator(dev, "vref-supply", &vref); + if (ret) { + printf("can't get vref-supply: %d\n", ret); + return ret; + } + + vref_uv = regulator_get_value(vref); + if (vref_uv < 0) { + printf("can't get vref-supply value: %d\n", vref_uv); + return vref_uv; + } + + /* VDD supplied by common vref pin */ + uc_pdata->vdd_supply = vref; + uc_pdata->vdd_microvolts = vref_uv; + uc_pdata->vss_microvolts = 0; + return 0; } -- 2.35.1

3 2

[PATCH] rockchip: Set default LNX_KRNL_IMG_TEXT_OFFSET_BASE to SYS_TEXT_BASE
by Alper Nebi Yasak 14 Mar '22

14 Mar '22

U-Boot can be chainloaded from vendor firmware on ARM64 chromebooks from a GPT partition (roughly the same as in doc/chromium/chainload.rst), but an appropriate image header must be built-in to the U-Boot binary by enabling LINUX_KERNEL_IMAGE_HEADER. This header has a field for an image load offset from 2MiB alignment which must also be customized through LNX_KRNL_IMG_TEXT_OFFSET_BASE. Set it equal to SYS_TEXT_BASE by default for Rockchip boards, which happens to make this offset zero and works fine on chromebook_kevin both for chainloading and bare-metal use. Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> --- Looks like ARM64 chromebooks also need POSITION_INDEPENDENT=y to chainload that way, but I'm not enabling the configs here. I'm thinking of selecting these from new configs that also enable binman definitions for the kernel partition and legacy boot images. arch/arm/mach-rockchip/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 92f35309e4a6..308dc09b0389 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -390,6 +390,9 @@ config ROCKCHIP_SPI_IMAGE containing U-Boot. The image is built by binman. U-Boot sits near the start of the image. +config LNX_KRNL_IMG_TEXT_OFFSET_BASE + default SYS_TEXT_BASE + source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3128/Kconfig" -- 2.34.1

3 2

[PATCH] include: configs: move USB first in the boot order for rk3399
by Dan Johansen 14 Mar '22

14 Mar '22

In Manjaro ARM we have used this patch for years now and it was requested that we upstream it. This will make all rk3399 based boards try USB boot before SD or eMMC. Can be quite handy on some devices, where the other devices are not easy to get to. Signed-off-by: Dan Johansen <strit(a)manjaro.org> --- include/configs/rockchip-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index ba7061a287..5dc92373b2 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -55,9 +55,9 @@ #ifdef CONFIG_ROCKCHIP_RK3399 #define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_USB(func) \ BOOT_TARGET_MMC(func) \ BOOT_TARGET_NVME(func) \ - BOOT_TARGET_USB(func) \ BOOT_TARGET_PXE(func) \ BOOT_TARGET_DHCP(func) \ BOOT_TARGET_SF(func) -- 2.34.1

2 2

[PATCH] rockchip: ram: sdram_rk3x88: replace comma by semicolon
by Johan Jonker 14 Mar '22

14 Mar '22

A comma at the end of a line gives sometimes strange effects in combination with some code formatters, so replace a comma by a semicolon in the sdram_rk3188.c and sdram_rk3288.c files. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- drivers/ram/rockchip/sdram_rk3188.c | 2 +- drivers/ram/rockchip/sdram_rk3288.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index d9ed8adf..be8ba446 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -762,7 +762,7 @@ static int sdram_init(struct dram_info *dram, * CS1, n=2 * CS0 & CS1, n = 3 */ - sdram_params->ch[channel].rank = 2, + sdram_params->ch[channel].rank = 2; clrsetbits_le32(&publ->pgcr, 0xF << 18, (sdram_params->ch[channel].rank | 1) << 18); diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index f3e4a280..227a3cc6 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -862,7 +862,7 @@ static int sdram_init(struct dram_info *dram, * CS1, n=2 * CS0 & CS1, n = 3 */ - sdram_params->ch[channel].rank = 2, + sdram_params->ch[channel].rank = 2; clrsetbits_le32(&publ->pgcr, 0xF << 18, (sdram_params->ch[channel].rank | 1) << 18); -- 2.20.1

4 3