March 2022 - U-Boot

[PATCH] usb: dwc3: Add support to reset usb ULPI phy
by Michal Simek 04 Mar '22

04 Mar '22

From: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> When usb PHY initialization is done, the PHY need to be reset. Signed-off-by: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/usb/dwc3/Kconfig | 2 +- drivers/usb/dwc3/dwc3-generic.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 62aa65bf0cd2..685bda3729e5 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -25,7 +25,7 @@ config USB_DWC3_OMAP config USB_DWC3_GENERIC bool "Generic implementation of a DWC3 wrapper (aka dwc3 glue)" - depends on DM_USB && USB_DWC3 && MISC + depends on DM_USB && USB_DWC3 && MISC && DM_GPIO help Select this for Xilinx ZynqMP and similar Platforms. This wrapper supports Host and Peripheral operation modes. diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index b1e019b5b91a..17d35a6dc60c 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -25,6 +25,7 @@ #include <reset.h> #include <clk.h> #include <usb/xhci.h> +#include <asm/gpio.h> struct dwc3_glue_data { struct clk_bulk clks; @@ -42,6 +43,7 @@ struct dwc3_generic_priv { void *base; struct dwc3 dwc3; struct phy_bulk phys; + struct gpio_desc ulpi_reset; }; struct dwc3_generic_host_priv { @@ -77,6 +79,26 @@ static int dwc3_generic_probe(struct udevice *dev, if (rc && rc != -ENOTSUPP) return rc; + if (device_is_compatible(dev->parent, "xlnx,zynqmp-dwc3")) { + rc = gpio_request_by_name(dev->parent, "reset-gpios", 0, + &priv->ulpi_reset, GPIOD_ACTIVE_LOW); + if (rc != -EBUSY && rc) + return rc; + + /* Toggle ulpi to reset the phy. */ + rc = dm_gpio_set_value(&priv->ulpi_reset, 1); + if (rc) + return rc; + + mdelay(5); + + rc = dm_gpio_set_value(&priv->ulpi_reset, 0); + if (rc) + return rc; + + mdelay(5); + } + if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) reset_deassert_bulk(&glue->resets); @@ -98,6 +120,12 @@ static int dwc3_generic_remove(struct udevice *dev, { struct dwc3 *dwc3 = &priv->dwc3; + if (device_is_compatible(dev->parent, "xlnx,zynqmp-dwc3")) { + struct gpio_desc *ulpi_reset = &priv->ulpi_reset; + + dm_gpio_free(ulpi_reset->dev, ulpi_reset); + } + dwc3_remove(dwc3); dwc3_shutdown_phy(dev, &priv->phys); unmap_physmem(dwc3->regs, MAP_NOCACHE); -- 2.35.1

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[PATCH u-boot-marvell 00/10] tools: kwboot: Fix boot and terminal mode
by Pali Rohár 04 Mar '22

04 Mar '22

This patch series fixes sending boot and debug patterns by doing it in separate thread. Entering BootROM debug mode via '-d' option is now more stable and working fine on Armada 385. There is also support for backspace key and updated documentation. Stefan and Tony, could you test this patch series on more Marvell boards which you have? Specially if '-d' option is working too. *** BLURB HERE *** Pali Rohár (10): tools: kwboot: Check for return value of kwboot_tty_send() and tcflush() tools: kwboot: Remove msg_req_delay tools: kwboot: Cleanup bootmsg and debugmsg variables tools: kwboot: Use separate thread for sending boot message pattern tools: kwboot: Fix sending and processing debug message pattern (-d option) tools: kwboot: Add support for backspace key in mini terminal tools: kwboot: Update usage tools: kwboot: Update manpage tools: kwboot: Update doc about Avanta tools: kwboot: Update references with public links doc/kwboot.1 | 105 ++++++++++- tools/Makefile | 3 + tools/kwboot.c | 462 ++++++++++++++++++++++++++++++++++++++++--------- 3 files changed, 483 insertions(+), 87 deletions(-) -- 2.20.1

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[PATCH] ARM: mvebu: x530: clearfog: Add ODT configuration
by Chris Packham 04 Mar '22

04 Mar '22

Commit 369e532691e0 ("ddr: marvell: a38x: allow board specific ODT configuration") added the odt_config member to struct mv_ddr_topology_map ahead of the clk_enable and ck_delay members. This means that any boards that configured either of clk_enable or ck_delay needed to have their board topology updated. This affects the x530 and clearfog boards. Other A38x boards don't touch any of the trailing members of mv_ddr_topology_map so don't need updating. Fixes: 369e532691e0 ("ddr: marvell: a38x: allow board specific ODT configuration") Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- board/alliedtelesis/x530/x530.c | 1 + board/solidrun/clearfog/clearfog.c | 1 + 2 files changed, 2 insertions(+) diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index 8b31045a0743..c0ec2afa3011 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -73,6 +73,7 @@ static struct mv_ddr_topology_map board_topology_map = { {0}, /* timing parameters */ { {0} }, /* electrical configuration */ {0}, /* electrical parameters */ + 0, /* ODT configuration */ 0, /* Clock enable mask */ 160 /* Clock delay */ }; diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index c920cf8d6b50..03adb591d826 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -147,6 +147,7 @@ static struct mv_ddr_topology_map board_topology_map = { {0}, /* timing parameters */ { {0} }, /* electrical configuration */ {0,}, /* electrical parameters */ + 0, /* ODT configuration */ 0x3, /* clock enable mask */ }; -- 2.35.1

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[PATCH u-boot-marvell] arm64: a37xx: pinctrl: Fix PWM pins indexes
by Marek Behún 04 Mar '22

04 Mar '22

From: Marek Behún <marek.behun(a)nic.cz> Commit 5534fb4f4833 ("arm64: a37xx: pinctrl: Correct PWM pins definitions") introduced bogus definitions os PWM pins: all 4 pins have index 11, instead of having indexes 11, 12, 13, 14. Fix this. Signed-off-by: Marek Behún <marek.behun(a)nic.cz> --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 1cf1f06f10..e76ef153e6 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -162,11 +162,11 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"), PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3), "pwm", "led"), - PIN_GRP_GPIO_3("pwm1", 11, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4), + PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4), "pwm", "led"), - PIN_GRP_GPIO_3("pwm2", 11, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5), + PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5), "pwm", "led"), - PIN_GRP_GPIO_3("pwm3", 11, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6), + PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6), "pwm", "led"), PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"), PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"), -- 2.34.1

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[PATCH] drivers: rtc: fix null pointer access in armada38x_rtc_reset
by fberder＠outlook.fr 04 Mar '22

04 Mar '22

From: Francois Berder <fberder(a)outlook.fr> Replace null pointer by pointer to device registers when calling armada38x_rtc_write. Signed-off-by: Francois Berder <fberder(a)outlook.fr> --- drivers/rtc/armada38x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/rtc/armada38x.c b/drivers/rtc/armada38x.c index 2d264acf77..2af64e3912 100644 --- a/drivers/rtc/armada38x.c +++ b/drivers/rtc/armada38x.c @@ -121,7 +121,7 @@ static int armada38x_rtc_reset(struct udevice *dev) armada38x_rtc_write(0, rtc, RTC_CONF_TEST); mdelay(500); armada38x_rtc_write(0, rtc, RTC_TIME); - armada38x_rtc_write(BIT(0) | BIT(1), 0, RTC_STATUS); + armada38x_rtc_write(BIT(0) | BIT(1), rtc, RTC_STATUS); } return 0; -- 2.30.1 (Apple Git-130)

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[PATCH u-boot-marvell] arm: a37xx: pci: Fix a3700_fdt_fix_pcie_regions() function again
by Marek Behún 04 Mar '22

04 Mar '22

From: Pali Rohár <pali(a)kernel.org> The a3700_fdt_fix_pcie_regions() function still computes nonsense. It computes the fixup offset from the PCI address taken from the first row of the "ranges" array, which means that: - PCI address must equal CPU address (otherwise the computed fix offset will be wrong), - the first row must contain the lowest address. This is the case for the default device-tree, which is why we didn't notice it. It also adds the fixup offset to all PCI and CPU addresses, which is wrong. Instead: 1) The fixup offset must be computed from the CPU address, not PCI address. 2) The fixup offset must be computed from the row containing the lowest CPU address, which is not necessarily contained in the first row. 3) The PCI address - the address to which the PCIe controller remaps the address space as seen from the point of view of the PCIe device - must be fixed by the fix offset in the same way as the CPU address only in the special case when the CPU adn PCI addresses are the same. Same addresses means that remapping is disabled, and thus if we change the CPU address, we need also to change the PCI address so that the remapping is still disabled afterwards. Consider an example: The ranges entries contain: PCI address CPU address 70000000 EA000000 E9000000 E9000000 EB000000 EB000000 By default CPU PCIe window is at: E8000000 - F0000000 Consider the case when TF-A moves it to: F2000000 - FA000000 Until now the function would take the PCI address of the first entry: 70000000, and the new base, F2000000, to compute the fix offset: F2000000 - 70000000 = 82000000, and then add 8200000 to all addresses, resulting in PCI address CPU address F2000000 6C000000 6B000000 6B000000 6D000000 6D000000 which is complete nonsense - none of the CPU addresses is in the requested window. Now it will take the lowest CPU address, which is in second row, E9000000, and compute the fix offset F2000000 - E9000000 = 09000000, and then add it to all CPU addresses and those PCI addresses which equal to their corresponding CPU addresses, resulting in PCI address CPU address 70000000 F3000000 F2000000 F2000000 F4000000 F4000000 where all of the CPU addresses are in the needed window. Fixes: 4a82fca8e330 ("arm: a37xx: pci: Fix a3700_fdt_fix_pcie_regions() function") Signed-off-by: Pali Rohár <pali(a)kernel.org> Signed-off-by: Marek Behún <marek.behun(a)nic.cz> --- arch/arm/mach-mvebu/armada3700/cpu.c | 81 +++++++++++++++++++--------- 1 file changed, 55 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index 23492f49da..52b5109b73 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -316,8 +316,8 @@ static int fdt_setprop_inplace_u32_partial(void *blob, int node, int a3700_fdt_fix_pcie_regions(void *blob) { - int acells, pacells, scells; - u32 base, fix_offset; + u32 base, lowest_cpu_addr, fix_offset; + int pci_cells, cpu_cells, size_cells; const u32 *ranges; int node, pnode; int ret, i, len; @@ -331,51 +331,80 @@ int a3700_fdt_fix_pcie_regions(void *blob) return node; ranges = fdt_getprop(blob, node, "ranges", &len); - if (!ranges || len % sizeof(u32)) - return -ENOENT; + if (!ranges || !len || len % sizeof(u32)) + return -EINVAL; /* * The "ranges" property is an array of - * { <child address> <parent address> <size in child address space> } + * { <PCI address> <CPU address> <size in PCI address space> } + * where number of PCI address cells and size cells is stored in the + * "#address-cells" and "#size-cells" properties of the same node + * containing the "ranges" property and number of CPU address cells + * is stored in the parent's "#address-cells" property. * - * All 3 elements can span a diffent number of cells. Fetch their sizes. + * All 3 elements can span a diffent number of cells. Fetch them. */ pnode = fdt_parent_offset(blob, node); - acells = fdt_address_cells(blob, node); - pacells = fdt_address_cells(blob, pnode); - scells = fdt_size_cells(blob, node); + pci_cells = fdt_address_cells(blob, node); + cpu_cells = fdt_address_cells(blob, pnode); + size_cells = fdt_size_cells(blob, node); - /* Child PCI addresses always use 3 cells */ - if (acells != 3) - return -ENOENT; + /* PCI addresses always use 3 cells */ + if (pci_cells != 3) + return -EINVAL; + + /* CPU addresses on Armada 37xx always use 2 cells */ + if (cpu_cells != 2) + return -EINVAL; + + for (i = 0; i < len / sizeof(u32); + i += pci_cells + cpu_cells + size_cells) { + /* + * Parent CPU addresses on Armada 37xx are always 32-bit, so + * check that the high word is zero. + */ + if (fdt32_to_cpu(ranges[i + pci_cells])) + return -EINVAL; + + if (i == 0 || + fdt32_to_cpu(ranges[i + pci_cells + 1]) < lowest_cpu_addr) + lowest_cpu_addr = fdt32_to_cpu(ranges[i + pci_cells + 1]); + } - /* Calculate fixup offset from first child address (in last cell) */ - fix_offset = base - fdt32_to_cpu(ranges[2]); + /* Calculate fixup offset from the lowest (first) CPU address */ + fix_offset = base - lowest_cpu_addr; - /* If fixup offset is zero then there is nothing to fix */ + /* If fixup offset is zero there is nothing to fix */ if (!fix_offset) return 0; /* - * Fix address (last cell) of each child address and each parent - * address + * Fix each CPU address and corresponding PCI address if PCI address + * is not already remapped (has the same value) */ - for (i = 0; i < len / sizeof(u32); i += acells + pacells + scells) { + for (i = 0; i < len / sizeof(u32); + i += pci_cells + cpu_cells + size_cells) { + u32 cpu_addr; + u64 pci_addr; int idx; - /* fix child address */ - idx = i + acells - 1; + /* Fix CPU address */ + idx = i + pci_cells + cpu_cells - 1; + cpu_addr = fdt32_to_cpu(ranges[idx]); ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx, - fdt32_to_cpu(ranges[idx]) + - fix_offset); + cpu_addr + fix_offset); if (ret) return ret; - /* fix parent address */ - idx = i + acells + pacells - 1; + /* Fix PCI address only if it isn't remapped (is same as CPU) */ + idx = i + pci_cells - 1; + pci_addr = ((u64)fdt32_to_cpu(ranges[idx - 1]) << 32) | + fdt32_to_cpu(ranges[idx]); + if (cpu_addr != pci_addr) + continue; + ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx, - fdt32_to_cpu(ranges[idx]) + - fix_offset); + cpu_addr + fix_offset); if (ret) return ret; } -- 2.34.1

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[PATCH u-boot-marvell] arm: mvebu: turris_omnia: Enable ext4 write support in defconfig
by Marek Behún 04 Mar '22

04 Mar '22

From: Marek Behún <marek.behun(a)nic.cz> Enable ext4 write support in Turris Omnia's defconfig. Some users find it useful. Signed-off-by: Marek Behún <marek.behun(a)nic.cz> --- configs/turris_omnia_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 280dd55f00..5b1fdbfb2d 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -93,3 +93,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_WDT=y CONFIG_WDT_ORION=y +CONFIG_EXT4_WRITE=y -- 2.34.1

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[PATCH 1/2] pci: pci_mvebu: Remove unused SELECT and lane_mask
by Pali Rohár 04 Mar '22

04 Mar '22

Macro SELECT() is unused and struct mvebu_pcie field lane_mask is unused too. Remove them. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/pci/pci_mvebu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 5a0a59a8b9ec..16fe54fd366f 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -30,8 +30,6 @@ #include <linux/sizes.h> /* PCIe unit register offsets */ -#define SELECT(x, n) ((x >> n) & 1UL) - #define PCIE_DEV_ID_OFF 0x0000 #define PCIE_CMD_OFF 0x0004 #define PCIE_DEV_REV_OFF 0x0008 @@ -77,7 +75,6 @@ struct mvebu_pcie { u32 lane; bool is_x4; int devfn; - u32 lane_mask; int sec_busno; char name[16]; unsigned int mem_target; -- 2.20.1

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[PATCH] tools: kwboot: Fix quitting terminal
by Pali Rohár 04 Mar '22

04 Mar '22

Sometimes kwboot after quitting terminal prints error message: terminal: Bad address This is caused by trying to call write() syscall with count of (size_t)-1 bytes. When quit sequence is split into more read() calls then number of input bytes (nin) at the end of cycle can underflow and be negative. Fix it. Fixes: de7514046ea5 ("tools: kwboot: Fix detection of quit esc sequence") Signed-off-by: Pali Rohár <pali(a)kernel.org> --- tools/kwboot.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/kwboot.c b/tools/kwboot.c index 68c0ef1f1b07..2d2d545d8258 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -1197,7 +1197,7 @@ kwboot_term_pipe(int in, int out, const char *quit, int *s) if (buf[i] == quit[*s]) { (*s)++; if (!quit[*s]) { - nin = i - *s; + nin = (i > *s) ? (i - *s) : 0; break; } } else { @@ -1208,7 +1208,7 @@ kwboot_term_pipe(int in, int out, const char *quit, int *s) } if (i == nin) - nin -= *s; + nin -= (nin > *s) ? *s : nin; } if (kwboot_write(out, buf, nin) < 0) -- 2.20.1

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[PATCH 1/2] x86: Add an enum name for the GNVS firmware type
by Simon Glass 04 Mar '22

04 Mar '22

This enum is currently anonymous. Add a name so it can be used in the code. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/x86/include/asm/intel_gnvs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h index fc743dc928..b12d7f9485 100644 --- a/arch/x86/include/asm/intel_gnvs.h +++ b/arch/x86/include/asm/intel_gnvs.h @@ -47,7 +47,7 @@ enum { BINF_RW_B = 2 }; -enum { +enum cros_fw_type_t { FIRMWARE_TYPE_AUTO_DETECT = -1, FIRMWARE_TYPE_RECOVERY = 0, FIRMWARE_TYPE_NORMAL = 1, -- 2.35.1.574.g5d30c73bfb-goog

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