March 2022 - U-Boot

Status of Intel (Altera) Arria-10 support
by Marcel Gielen [Celestia-STS] 03 Mar '22

03 Mar '22

It has been a while ago when I had to do something with an intel Arria-10. At that time the support was a bit troublesome. Some of the issues faced: U-Boot 2nd stage requires SDRAM to run. The ARRIA-10 DDR controller for the HPS requires at least the peripheral part of the FPGA to be configured. Configuring of the (peripheral part) of FPGA consequently has to be done from the SPL to make SDRAM available. Peripheral and core part of the FPGA must come from the same build. As a consequence, selecting the FPGA binary to load is not possible from u-boot scripting. Having multiple boot options, failsafe boot, recovery, which are normally possible with u-boot scripting are not possible due to the FPGA constraint to the SPL. How is the status with respect to those issues ? Have any additions or improvements been made since approx. 2 years ago ? I also wonder how other Arria-10 users deal with this, 'in field' updating the FPGA becomes now just as risky as updating the bootloader (which we by default avoid). Of course, there possible solutions by modifying the SPL, but I prefer not to re-invent the wheel in case there are other solutions. Any suggestions are appreciated, Marcel

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[PATCH v2 0/3] Add SPI boot to SPL on SUNIV/F1C100s
by Jesse Taube 03 Mar '22

03 Mar '22

This patch adds the ability to detect the BROM's boot source, as well as the ability to boot from SPI. Jesse Taube (3): mach-sunxi: Add boot device detection for SUNIV/F1C100s mach-sunxi: Add SPL SPI boot for SUNIV mach-sunxi: Enable SPI boot for SUNIV and licheepi nano arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/include/asm/arch-sunxi/spl.h | 10 +++++ arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/board.c | 57 +++++++++++++------------- arch/arm/mach-sunxi/spl_spi_sunxi.c | 24 +++++++---- configs/licheepi_nano_defconfig | 1 + 6 files changed, 58 insertions(+), 37 deletions(-) -- 2.34.1

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[PATCH] sunxi: f1c100s: Drop SYSRESET to enable reset functionality
by Andre Przywara 03 Mar '22

03 Mar '22

The F1C100s DT contains the wrong compatible string for the watchdog, which breaks reset functionality. Updating the DT goes via the Linux tree, but to allow reset functionality meanwhile (useful for development!), disable SYSRESET for now, to let the old-fashioned watchdog driver kick in and provide the reset_cpu() implementation. Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- configs/licheepi_nano_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index 9fd1dcc9958..67b7b85c491 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -10,3 +10,4 @@ CONFIG_DRAM_CLK=156 CONFIG_DRAM_ZQ=0 # CONFIG_VIDEO_SUNXI is not set CONFIG_SPL_SPI_SUNXI=y +# CONFIG_SYSRESET is not set -- 2.35.1

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[PATCH v2 0/6] armv8: fixes and cleanups
by Andre Przywara 02 Mar '22

02 Mar '22

Hi, revamping this small series, just small changes: - rebasing on top of origin/master, there was a trivial conflict - checking for FEAT_LSE2 before trying unaligned accesses (patch 1/6) Michael Walle tested the whole of v1 successfully, and the changes should not affect this result. Mark Kettenis tested this on the Apple M1, but patch 1/6 has changed, so I don't dare to carry over his tag. ------------- I was looking into the arm64 boot code lately and stumbled upon some issues. Also Nishanth brought back memories of a lengthy debug session, which was caused due to U-Boot keeping SErrors masked. As the resulting patches are all somewhat related, I gathered this series here to address those problems. Patches 1 to 3 address exception handling issues, with the SError enablement being the most prominent fix here. Patch 4 cleans up asm/io.h. This was on the list before[1], but was somehow lost when it was intercepted by a shorter version of itself. Patches 5 and 6 clean up some unnecessarily complicated AArch64 assembly code. I did only some light testing, as some code paths do not apply to boards I have (ARMV8_MULTIENTRY). However v1 was tested by Michael Walle in both EL3 and EL2. Cheers, Andre [1] https://lists.denx.de/pipermail/u-boot/2019-January/354296.html Andre Przywara (6): cmd: exception: arm64: fix undefined, add faults armv8: Always unmask SErrors armv8: Force SP_ELx stack pointer usage arm: Clean up asm/io.h armv8: Simplify switch_el macro armv8: Fix and simplify branch_if_master/branch_if_slave arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 11 +-- arch/arm/cpu/armv8/start.S | 10 +- arch/arm/include/asm/io.h | 98 +------------------- arch/arm/include/asm/macro.h | 37 +++----- arch/arm/include/asm/system.h | 1 + arch/arm/mach-rmobile/lowlevel_init_gen3.S | 2 +- arch/arm/mach-socfpga/lowlevel_init_soc64.S | 2 +- board/cortina/presidio-asic/lowlevel_init.S | 2 +- cmd/arm/exception64.c | 64 ++++++++++++- 9 files changed, 85 insertions(+), 142 deletions(-) -- 2.25.1

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arm: Simple delay function because of an chicken and egg problem
by Johannes (krjdev) Krottmayer 02 Mar '22

02 Mar '22

Hi, I'm running into an chicken and egg problem when modifying (fixing) some drivers for STMicroelectronics SoC's. The problem, I will implement a timeout, when accessing some registers. Unfortunately I cannot use the basic mdelay() or higher level functions, which use this function, because there on these SoC's there isn't setup and enabled the timer before. Also the ARMv7-M SysTick timer will not be used. I could write a simple delay loop which counts down at the frequency from the processor speed. But I think, this is not a good idea. Any suggestion, what I can do? I'm still new in U-Boot, so I don't know if there a simple delay function exists. Thanks in advance! Johannes K.

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[PATCH 0/9] Enable the pylint checker in CI
by Simon Glass 02 Mar '22

02 Mar '22

This series adds a new errors-only pylint check and adds it to the CI systems. It also fixes the current errors in the U-Boot Python code, disabling errors where it seems necessary. A small patch to buildman allows it to build sandbox without any changes to the default config file. Simon Glass (9): patman: Correct pylint errors buildman: Correct pylint errors dtoc: Correct pylint errors binman: Correct pylint errors moveconfig: Correct pylint errors test: Correct pylint errors Makefile: Add a way to check for pylint errors buildman: Update default config to build for sandbox Azure/GitLab CI: Add the pylint checker .azure-pipelines.yml | 22 +++++++++++++++++++++ .gitlab-ci.yml | 16 +++++++++++++++ Makefile | 10 ++++++++-- doc/develop/python_cq.rst | 11 +++++++++++ test/py/tests/test_android/test_avb.py | 2 +- test/py/tests/test_bind.py | 8 ++++---- test/py/tests/vboot_evil.py | 3 ++- test/py/u_boot_console_base.py | 8 ++++++++ tools/binman/cmdline.py | 2 +- tools/binman/control.py | 6 ++++++ tools/binman/elf_test.py | 13 ++++++------ tools/binman/entry.py | 2 ++ tools/binman/entry_test.py | 7 ++----- tools/binman/etype/blob_dtb.py | 3 +++ tools/binman/etype/blob_phase.py | 3 +++ tools/binman/etype/cbfs.py | 3 +++ tools/binman/etype/fdtmap.py | 5 +++++ tools/binman/etype/files.py | 2 ++ tools/binman/etype/section.py | 1 + tools/binman/etype/u_boot_dtb_with_ucode.py | 3 +++ tools/binman/ftest.py | 21 ++------------------ tools/buildman/bsettings.py | 1 + tools/buildman/builder.py | 2 +- tools/buildman/cfgutil.py | 6 +++--- tools/buildman/func_test.py | 6 ------ tools/buildman/kconfiglib.py | 1 + tools/buildman/main.py | 4 ++-- tools/concurrencytest/__init__.py | 0 tools/dtoc/test_dtoc.py | 6 +++--- tools/dtoc/test_fdt.py | 6 +++--- tools/moveconfig.py | 5 +---- tools/patman/checkpatch.py | 4 +++- tools/patman/command.py | 8 +------- tools/patman/commit.py | 2 +- tools/patman/cros_subprocess.py | 18 ++++------------- tools/patman/func_test.py | 10 ++++++++++ tools/patman/patchstream.py | 2 +- tools/patman/series.py | 3 +-- tools/patman/settings.py | 4 ++-- tools/patman/tools.py | 10 +++++----- 40 files changed, 154 insertions(+), 95 deletions(-) create mode 100644 tools/concurrencytest/__init__.py -- 2.35.1.265.g69c8d7142f-goog

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[PATCH v2] drivers: adc: fix return value if timeout occurs
by Francois Berder 02 Mar '22

02 Mar '22

Because unsigned integers cannot be negative, timeout variable is never less than zero. Hence, checks in Amlogic Meson ADC driver to detect timeouts always evaluated to false. Fix that. Signed-off-by: Francois Berder <fberder(a)outlook.fr> --- Changes for v2: - Replace timeout handling logic by regmap_read_poll_timeout drivers/adc/meson-saradc.c | 33 ++++++++++++++------------------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c index 1a45a3a265..b36f09cdb1 100644 --- a/drivers/adc/meson-saradc.c +++ b/drivers/adc/meson-saradc.c @@ -192,7 +192,8 @@ meson_saradc_get_fifo_count(struct meson_saradc_priv *priv) static int meson_saradc_lock(struct meson_saradc_priv *priv) { - uint val, timeout = 10000; + uint val; + int ret; /* prevent BL30 from using the SAR ADC while we are using it */ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, @@ -202,17 +203,14 @@ static int meson_saradc_lock(struct meson_saradc_priv *priv) /* * wait until BL30 releases it's lock (so we can use the SAR ADC) */ - do { - udelay(1); - regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); - } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--); - - if (timeout < 0) { + ret = + regmap_read_poll_timeout(priv->regmap, MESON_SAR_ADC_DELAY, val, + val & MESON_SAR_ADC_DELAY_BL30_BUSY, 1, + 10); + if (ret) printf("Timeout while waiting for BL30 unlock\n"); - return -ETIMEDOUT; - } - return 0; + return ret; } static void meson_saradc_unlock(struct meson_saradc_priv *priv) @@ -246,22 +244,19 @@ static int meson_saradc_calib_val(struct meson_saradc_priv *priv, int val) static int meson_saradc_wait_busy_clear(struct meson_saradc_priv *priv) { - uint regval, timeout = 10000; + uint regval; /* * NOTE: we need a small delay before reading the status, otherwise * the sample engine may not have started internally (which would * seem to us that sampling is already finished). */ - do { - udelay(1); - regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval); - } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--); + udelay(1); - if (timeout < 0) - return -ETIMEDOUT; - - return 0; + return regmap_read_poll_timeout(priv->regmap, MESON_SAR_ADC_REG0, + regval, + FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, + regval), 1, 10); } static int meson_saradc_read_raw_sample(struct meson_saradc_priv *priv, -- 2.25.1

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[PATCH v2 0/6] Exception handling in HYP mode on ARMv7-A
by Jim Posen 02 Mar '22

02 Mar '22

Currently, when U-Boot is running in hypervisor mode on ARMv7-A CPUs with virtualization extensions, the exception handling does not work. A couple things need to change which are detailed in my earlier message to the u-boot mailing list with the subject "Exception handling in HYP mode on ARMv7-A". I have verified that this patch series works on the ODroid XU4 and the Raspberry Pi 3B in Aarch32 mode when running in hypervisor mode. One simple way to verify is by running the miscellaneous "exception" command (CMD_EXCEPTION). This can be tested with QEMU now. Configure with qemu_arm_defconfig and add CMD_EXCEPTION and QEMU_ARM_32BIT_HAS_VIRT. Then run qemu-system-arm \ -machine virt,virtualization \ -nographic -serial mon:stdio \ -bios u-boot.bin U-Boot 2021.10-... ... => exception undefined Changes in v2: - Fix CP15 register written to in start.S - Check processor mode as HVBAR register is only accessible in HYP mode - Add QEMU config option for ARM32 with virtualization extensions Jim Posen (6): Compile for ARMv7-A with virtualization extensions Hypervisor mode interrupt vector table Set HVBAR register correctly Remove dead code Fix PC adjustment logic in exception handlers Config to target QEMU virt machine with virtualization arch/arm/Makefile | 4 + arch/arm/cpu/armv7/start.S | 8 ++ arch/arm/include/asm/u-boot-arm.h | 14 ++-- arch/arm/lib/interrupts.c | 26 +++--- arch/arm/lib/relocate.S | 13 +++ arch/arm/lib/vectors.S | 129 +++++++++++++++++++++++------- arch/arm/mach-bcm283x/Kconfig | 3 + arch/arm/mach-exynos/Kconfig | 1 + arch/arm/mach-qemu/Kconfig | 6 ++ 9 files changed, 153 insertions(+), 51 deletions(-) -- 2.25.1

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[PATCH 1/2] doc: board: amlogic-p20x: fix FIP generation doc
by Neil Armstrong 02 Mar '22

02 Mar '22

The doc used GXL instructions, which couldn't work on GXBB SoCs. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- doc/board/amlogic/p200.rst | 57 +++++++++++++++++--------------------- doc/board/amlogic/p201.rst | 57 +++++++++++++++++--------------------- 2 files changed, 52 insertions(+), 62 deletions(-) diff --git a/doc/board/amlogic/p200.rst b/doc/board/amlogic/p200.rst index c3d6441fd3..1c84f1c9d0 100644 --- a/doc/board/amlogic/p200.rst +++ b/doc/board/amlogic/p200.rst @@ -54,44 +54,39 @@ Go back to mainline U-boot source tree then : $ mkdir fip - $ cp $FIPDIR/gxl/bl2.bin fip/ - $ cp $FIPDIR/gxl/acs.bin fip/ - $ cp $FIPDIR/gxl/bl21.bin fip/ - $ cp $FIPDIR/gxl/bl30.bin fip/ - $ cp $FIPDIR/gxl/bl301.bin fip/ - $ cp $FIPDIR/gxl/bl31.img fip/ + $ cp $FIPDIR/gxb/bl2.bin fip/ + $ cp $FIPDIR/gxb/acs.bin fip/ + $ cp $FIPDIR/gxb/bl21.bin fip/ + $ cp $FIPDIR/gxb/bl30.bin fip/ + $ cp $FIPDIR/gxb/bl301.bin fip/ + $ cp $FIPDIR/gxb/bl31.img fip/ $ cp u-boot.bin fip/bl33.bin $ $FIPDIR/blx_fix.sh \ fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 - $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 $ $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin --bl31 fip/bl31.img --bl33 fip/bl33.bin fip/fip.bin + + $ cat fip/bl2_new.bin fip/fip.bin >fip/boot_new.bin + + $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig --input fip/boot_new.bin --output fip/u-boot.bin and then write the image to SD with: diff --git a/doc/board/amlogic/p201.rst b/doc/board/amlogic/p201.rst index 06da933a2a..a3d451c6e6 100644 --- a/doc/board/amlogic/p201.rst +++ b/doc/board/amlogic/p201.rst @@ -54,44 +54,39 @@ Go back to mainline U-boot source tree then : $ mkdir fip - $ cp $FIPDIR/gxl/bl2.bin fip/ - $ cp $FIPDIR/gxl/acs.bin fip/ - $ cp $FIPDIR/gxl/bl21.bin fip/ - $ cp $FIPDIR/gxl/bl30.bin fip/ - $ cp $FIPDIR/gxl/bl301.bin fip/ - $ cp $FIPDIR/gxl/bl31.img fip/ + $ cp $FIPDIR/gxb/bl2.bin fip/ + $ cp $FIPDIR/gxb/acs.bin fip/ + $ cp $FIPDIR/gxb/bl21.bin fip/ + $ cp $FIPDIR/gxb/bl30.bin fip/ + $ cp $FIPDIR/gxb/bl301.bin fip/ + $ cp $FIPDIR/gxb/bl31.img fip/ $ cp u-boot.bin fip/bl33.bin $ $FIPDIR/blx_fix.sh \ fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 - $ $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 $ $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 - - $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img - $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin --bl31 fip/bl31.img --bl33 fip/bl33.bin fip/fip.bin + + $ cat fip/bl2_new.bin fip/fip.bin >fip/boot_new.bin + + $ $FIPDIR/gxb/aml_encrypt_gxb --bootsig --input fip/boot_new.bin --output fip/u-boot.bin and then write the image to SD with: -- 2.25.1

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[PULL] u-boot-usb/master
by Marek Vasut 02 Mar '22

02 Mar '22

The following changes since commit f9a719e2954473f9be1f8c14a28288f943a00dd2: Prepare v2022.04-rc3 (2022-02-28 18:02:33 -0500) are available in the Git repository at: git://source.denx.de/u-boot-usb.git master for you to fetch changes up to a41b88ec02ea1dbf4e5e6e895625a5fee96097c5: phy: nop-phy: Fix phy reset if no reset-gpio defined (2022-03-01 00:21:11 +0100) ---------------------------------------------------------------- Tim Harvey (1): phy: nop-phy: Fix phy reset if no reset-gpio defined drivers/phy/nop-phy.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)

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