February 2022 - U-Boot

[PATCH u-boot-marvell] pci: mvebu: Ensure that root port is always on root zero bus
by Pali Rohár 17 Feb '22

17 Feb '22

Writing to the PCI_PRIMARY_BUS register of the root port should not change bus number on which is root port present. Same change and exactly same fix as was done in commit for pci-aardvark.c. Fixes: a7b61ab58d5d ("pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port)") Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/pci/pci_mvebu.c | 52 +++++++++++++++++------------------------ 1 file changed, 22 insertions(+), 30 deletions(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index d99a99bae940..5a0a59a8b9ec 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -78,7 +78,6 @@ struct mvebu_pcie { bool is_x4; int devfn; u32 lane_mask; - int first_busno; int sec_busno; char name[16]; unsigned int mem_target; @@ -140,12 +139,12 @@ static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose) static bool mvebu_pcie_valid_addr(struct mvebu_pcie *pcie, int busno, int dev, int func) { - /* On primary bus is only one PCI Bridge */ - if (busno == pcie->first_busno && (dev != 0 || func != 0)) + /* On the root bus is only one PCI Bridge */ + if (busno == 0 && (dev != 0 || func != 0)) return false; /* Access to other buses is possible when link is up */ - if (busno != pcie->first_busno && !mvebu_pcie_link_up(pcie)) + if (busno != 0 && !mvebu_pcie_link_up(pcie)) return false; /* On secondary bus can be only one PCIe device */ @@ -173,15 +172,15 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, } /* - * The configuration space of the PCI Bridge on primary (first) bus is + * The configuration space of the PCI Bridge on the root bus (zero) is * of Type 0 but the BAR registers (including ROM BAR) don't have the * same meaning as in the PCIe specification. Therefore do not access * BAR registers and non-common registers (those which have different * meaning for Type 0 and Type 1 config space) of the PCI Bridge and * instead read their content from driver virtual cfgcache[]. */ - if (busno == pcie->first_busno && ((offset >= 0x10 && offset < 0x34) || - (offset >= 0x38 && offset < 0x3c))) { + if (busno == 0 && ((offset >= 0x10 && offset < 0x34) || + (offset >= 0x38 && offset < 0x3c))) { data = pcie->cfgcache[(offset - 0x10) / 4]; debug("(addr,size,val)=(0x%04x, %d, 0x%08x) from cfgcache\n", offset, size, data); @@ -190,10 +189,10 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, } /* - * PCI bridge is device 0 at primary bus but mvebu has it mapped on - * secondary bus with device number 1. + * PCI bridge is device 0 at the root bus (zero) but mvebu has it + * mapped on secondary bus with device number 1. */ - if (busno == pcie->first_busno) + if (busno == 0) addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset); else addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); @@ -216,8 +215,7 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, return -EINVAL; } - if (busno == pcie->first_busno && - (offset & ~3) == (PCI_HEADER_TYPE & ~3)) { + if (busno == 0 && (offset & ~3) == (PCI_HEADER_TYPE & ~3)) { /* * Change Header Type of PCI Bridge device to Type 1 * (0x01, used by PCI Bridges) because mvebu reports @@ -257,10 +255,10 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, * config registers are not available, so we write their content only * into driver virtual cfgcache[]. * And as explained in mvebu_pcie_probe(), mvebu has its own specific - * way for configuring primary and secondary bus numbers. + * way for configuring secondary bus number. */ - if (busno == pcie->first_busno && ((offset >= 0x10 && offset < 0x34) || - (offset >= 0x38 && offset < 0x3c))) { + if (busno == 0 && ((offset >= 0x10 && offset < 0x34) || + (offset >= 0x38 && offset < 0x3c))) { debug("Writing to cfgcache only\n"); data = pcie->cfgcache[(offset - 0x10) / 4]; data = pci_conv_size_to_32(data, value, offset, size); @@ -270,12 +268,6 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, (offset & ~3) == PCI_ROM_ADDRESS1) data = 0x0; pcie->cfgcache[(offset - 0x10) / 4] = data; - /* mvebu has its own way how to set PCI primary bus number */ - if (offset == PCI_PRIMARY_BUS) { - pcie->first_busno = data & 0xff; - debug("Primary bus number was changed to %d\n", - pcie->first_busno); - } /* mvebu has its own way how to set PCI secondary bus number */ if (offset == PCI_SECONDARY_BUS || (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) { @@ -288,10 +280,10 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, } /* - * PCI bridge is device 0 at primary bus but mvebu has it mapped on - * secondary bus with device number 1. + * PCI bridge is device 0 at the root bus (zero) but mvebu has it + * mapped on secondary bus with device number 1. */ - if (busno == pcie->first_busno) + if (busno == 0) addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset); else addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); @@ -473,9 +465,9 @@ static int mvebu_pcie_probe(struct udevice *dev) * target device equals local device number then request is routed to * PCI Bridge which represent local PCIe Root Port. * - * It means that PCI primary and secondary buses shares one bus number + * It means that PCI root and secondary buses shares one bus number * which is configured via local bus number. Determination if config - * request should go to primary or secondary bus is done based on local + * request should go to root or secondary bus is done based on local * device number. * * PCIe is point-to-point bus, so at secondary bus is always exactly one @@ -487,13 +479,13 @@ static int mvebu_pcie_probe(struct udevice *dev) * secondary bus number. Set it to 0 as U-Boot CONFIG_PCI_PNP code will * later configure it via config write requests to the correct value. * mvebu_pcie_write_config() catches config write requests which tries - * to change primary/secondary bus number and correctly updates local - * bus number based on new secondary bus number. + * to change secondary bus number and correctly updates local bus number + * based on new secondary bus number. * * With this configuration is PCI Bridge available at secondary bus as - * device number 1. But it must be available at primary bus as device + * device number 1. But it must be available at root bus (zero) as device * number 0. So in mvebu_pcie_read_config() and mvebu_pcie_write_config() - * functions rewrite address to the real one when accessing primary bus. + * functions rewrite address to the real one when accessing the root bus. */ mvebu_pcie_set_local_bus_nr(pcie, 0); mvebu_pcie_set_local_dev_nr(pcie, 1); -- 2.20.1

2 2

[PATCH u-boot-mvebu 0/3] arm: mvebu: a37xx: Fix and extend building memory map
by Pali Rohár 17 Feb '22

17 Feb '22

Fix calling build_mem_map() function and extend it to map also CCI-400 and AP BootROM address space. With this change it is possible to access A53 AP BootROM on Armada 3720 from U-Boot and e.g. dump it via U-Boot md command: => md fff00000 1000 Pali Rohár (3): arm: mvebu: a37xx: Fix calling build_mem_map() arm: mvebu: a37xx: Map CCI-400 and AP BootROM address space arm: mvebu: a37xx: Fix comment with name of the function arch/arm/mach-mvebu/armada3700/cpu.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) -- 2.20.1

3 20

[PATCH u-boot-marvell 0/9] arm: a37xx: Fix code and update DTS files to upstream version
by Pali Rohár 17 Feb '22

17 Feb '22

Fix Armada 3720 drivers and all Armada 3720 boards (DB, uDPU, Mox and Espressobin) to be compatible with DTS files from upstream Linux kernel and update all Armada 3720 DTS files to version which is scheduled for Linux kernel 5.18. DTS patches scheduled for unreleased Linux kernel version 5.18 have only changes which were already in U-Boot DTS files. With this change U-Boot's Armada 3720 DTS board files finally could be used for booting Linux kernel. Tested on Turris Mox. Pali Rohár (9): rtc: ds1307: Add bindings for microchip,mcp7940x phy: marvell: a3700: Update compatible string to official DT bindings usb: ehci: ehci-marvell: Update compatible string to official DT bindings watchdog: armada_37xx: Convert to official DT bindings arm: mvebu: turris_mox: Remove hardcoded ethernet node names arm: a37xx: Update sdhci pointers to official DT bindings arm: a37xx: espressobin: Move U-Boot specific partitions node to -u-boot.dtsi arm: a37xx: espressobin: Explicitly enable eMMC node in -u-boot.dtsi arm: a37xx: Update DTS files to version from upstream Linux kernel arch/arm/dts/armada-371x.dtsi | 38 +- arch/arm/dts/armada-3720-db.dts | 226 +++-- .../dts/armada-3720-espressobin-u-boot.dtsi | 31 + arch/arm/dts/armada-3720-espressobin.dts | 189 +---- arch/arm/dts/armada-3720-espressobin.dtsi | 218 +++++ arch/arm/dts/armada-3720-turris-mox.dts | 776 ++++++++++++++++-- arch/arm/dts/armada-3720-uDPU-u-boot.dtsi | 2 +- arch/arm/dts/armada-3720-uDPU.dts | 218 ++--- arch/arm/dts/armada-372x.dtsi | 43 +- arch/arm/dts/armada-37xx.dtsi | 448 ++++++---- board/CZ.NIC/turris_mox/turris_mox.c | 22 +- drivers/phy/marvell/comphy_a3700.c | 2 +- drivers/phy/marvell/comphy_core.c | 3 +- drivers/rtc/ds1307.c | 1 + drivers/usb/host/ehci-marvell.c | 4 +- drivers/watchdog/armada-37xx-wdt.c | 7 +- include/dt-bindings/bus/moxtet.h | 16 + 17 files changed, 1575 insertions(+), 669 deletions(-) create mode 100644 arch/arm/dts/armada-3720-espressobin-u-boot.dtsi create mode 100644 arch/arm/dts/armada-3720-espressobin.dtsi create mode 100644 include/dt-bindings/bus/moxtet.h -- 2.20.1

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[PATCH] tools: kwbimage: Fix dumping DATA registers for v0 images
by Pali Rohár 17 Feb '22

17 Feb '22

End of DATA register section is indicated by zero value in both raddr and rdata. So do not stop dumping registers with non-zero address and zero value. And also print end of DATA registers section. Fixes: 1a8e6b63e24f ("tools: kwbimage: Dump kwbimage config file on '-p -1' option") Signed-off-by: Pali Rohár <pali(a)kernel.org> Reported-by: Tony Dinh <mibodhi(a)gmail.com> Tested-by: Tony Dinh <mibodhi(a)gmail.com> --- tools/kwbimage.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tools/kwbimage.c b/tools/kwbimage.c index 9b63ce80ff4e..99d38cd1cfb2 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -2226,11 +2226,13 @@ static int kwbimage_generate_config(void *ptr, struct image_tool_params *params) ehdr0 = (struct ext_hdr_v0 *)(mhdr0 + 1); if (ehdr0->offset) { for (regdata = (struct ext_hdr_v0_reg *)((uint8_t *)ptr + ehdr0->offset); - (uint8_t *)regdata < (uint8_t *)ptr + header_size && regdata->raddr && - regdata->rdata; + (uint8_t *)regdata < (uint8_t *)ptr + header_size && + (regdata->raddr || regdata->rdata); regdata++) fprintf(f, "DATA 0x%08x 0x%08x\n", le32_to_cpu(regdata->raddr), le32_to_cpu(regdata->rdata)); + if ((uint8_t *)regdata != (uint8_t *)ptr + ehdr0->offset) + fprintf(f, "DATA 0x0 0x0\n"); } } -- 2.20.1

2 2

[PATCH u-boot-marvell 1/4] arm: a37xx: pci: Use standard register macros from pci.h
by Pali Rohár 17 Feb '22

17 Feb '22

PCI config space of the aardvark PCIe Root Port is available only in internal aardvark memory space starting at offset 0x0. PCI Express registers (PCI_EXP_*) start at offset 0xc0. And Advanced Error Reporting registers (PCI_ERR_*) start at offset 0x100. Replace custom aardvark register macros by standard PCI macros from include/pci.h file with fixed offset. Some DEVCTL and AER macros are not defined in include/pci.h file, so define them in the same way as in linux uapi header file pci_regs.h. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/pci/pci-aardvark.c | 82 ++++++++++++++------------------------ include/pci.h | 24 +++++++++++ 2 files changed, 54 insertions(+), 52 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 22b6d8b62865..ad4edd715bd6 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -35,28 +35,10 @@ #include <linux/delay.h> #include <linux/ioport.h> -/* PCIe core registers */ -#define PCIE_CORE_CMD_STATUS_REG 0x4 -#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) -#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) -#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) -#define PCIE_CORE_DEV_REV_REG 0x8 -#define PCIE_CORE_EXP_ROM_BAR_REG 0x30 -#define PCIE_CORE_PCIEXP_CAP_OFF 0xc0 -#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 -#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) -#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) -#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE 0x2 -#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT 5 -#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE 0x2 -#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 -#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 -#define PCIE_CORE_LINK_TRAINING BIT(5) -#define PCIE_CORE_ERR_CAPCTL_REG 0x118 -#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) -#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) -#define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7) -#define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8) +/* PCIe Root Port register offsets */ +#define ADVK_ROOT_PORT_PCI_CFG_OFF 0x0 +#define ADVK_ROOT_PORT_PCI_EXP_OFF 0xc0 +#define ADVK_ROOT_PORT_PCI_ERR_OFF 0x100 /* PIO registers base address and register offsets */ #define PIO_BASE_ADDR 0x4000 @@ -394,7 +376,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, if ((offset >= 0x10 && offset < 0x34) || (offset >= 0x38 && offset < 0x3c)) data = pcie->cfgcache[(offset - 0x10) / 4]; else - data = advk_readl(pcie, offset & ~3); + data = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3)); if ((offset & ~3) == (PCI_HEADER_TYPE & ~3)) { /* @@ -406,14 +388,13 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, data |= PCI_HEADER_TYPE_BRIDGE << 16; } - if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL) { + if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_RTCTL) { /* CRSSVE bit is stored only in cache */ if (pcie->cfgcrssve) data |= PCI_EXP_RTCTL_CRSSVE; } - if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + - (PCI_EXP_RTCAP & ~3)) { + if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + (PCI_EXP_RTCAP & ~3)) { /* CRS is emulated below, so set CRSVIS capability */ data |= PCI_EXP_RTCAP_CRSVIS << 16; } @@ -583,9 +564,9 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, data = 0x0; pcie->cfgcache[(offset - 0x10) / 4] = data; } else { - data = advk_readl(pcie, offset & ~3); + data = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3)); data = pci_conv_size_to_32(data, value, offset, size); - advk_writel(pcie, data, offset & ~3); + advk_writel(pcie, data, ADVK_ROOT_PORT_PCI_CFG_OFF + (offset & ~3)); } if (offset == PCI_PRIMARY_BUS) @@ -595,7 +576,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) pcie->sec_busno = (data >> 8) & 0xff; - if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL) + if ((offset & ~3) == ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_RTCTL) pcie->cfgcrssve = data & PCI_EXP_RTCTL_CRSSVE; return 0; @@ -834,26 +815,25 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) * Type 1 registers is redirected to the virtual cfgcache[] buffer, * which avoids changing unrelated registers. */ - reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); + reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); reg &= ~0xffffff00; reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8; - advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); - - /* Set Advanced Error Capabilities and Control PF0 register */ - reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | - PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | - PCIE_CORE_ERR_CAPCTL_ECRC_CHECK | - PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV; - advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); - - /* Set PCIe Device Control and Status 1 PF0 register */ - reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | - (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE << - PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT) | - (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE << - PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT) | - PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE; - advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); + advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); + + /* Enable generation and checking of ECRC on PCIe Root Port */ + reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_ERR_OFF + PCI_ERR_CAP); + reg |= PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE; + advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_ERR_OFF + PCI_ERR_CAP); + + /* Set PCIe Device Control register on PCIe Root Port */ + reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_DEVCTL); + reg &= ~PCI_EXP_DEVCTL_RELAX_EN; + reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; + reg &= ~PCI_EXP_DEVCTL_PAYLOAD; + reg &= ~PCI_EXP_DEVCTL_READRQ; + reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; + reg |= PCI_EXP_DEVCTL_READRQ_512B; + advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_DEVCTL); /* Program PCIe Control 2 to disable strict ordering */ reg = PCIE_CORE_CTRL2_RESERVED | @@ -994,11 +974,9 @@ static int pcie_advk_remove(struct udevice *dev) for (i = 0; i < OB_WIN_COUNT; i++) pcie_advk_disable_ob_win(pcie, i); - reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); - reg &= ~(PCIE_CORE_CMD_MEM_ACCESS_EN | - PCIE_CORE_CMD_IO_ACCESS_EN | - PCIE_CORE_CMD_MEM_IO_REQ_EN); - advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); + reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND); + reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_COMMAND); reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg &= ~LINK_TRAINING_EN; diff --git a/include/pci.h b/include/pci.h index 9e7910b271b8..673c95c6bb79 100644 --- a/include/pci.h +++ b/include/pci.h @@ -484,6 +484,22 @@ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ #define PCI_EXP_DEVCTL 8 /* Device Control */ +#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ +#define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */ +#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ +#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ +#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ +#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */ +#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */ +#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */ +#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */ +#define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */ +#define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */ #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ @@ -522,6 +538,14 @@ #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Target Link Speed 5.0GT/s */ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Target Link Speed 8.0GT/s */ +/* Advanced Error Reporting */ +#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ +#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ +#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ +#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ +#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ +#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ + /* Single Root I/O Virtualization Registers */ #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ -- 2.20.1

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[PATCH v1 1/1] env: fat: Allow overriding interface, device and partition
by hyyxohk 17 Feb '22

17 Feb '22

For platform which can boot on different device, this allows to override interface, device and partition from board code. Signed-off-by: hyyxohk <hyyoxhk(a)163.com> --- env/fat.c | 30 +++++++++++++++++------------- include/env_internal.h | 20 ++++++++++++++++++++ 2 files changed, 37 insertions(+), 13 deletions(-) diff --git a/env/fat.c b/env/fat.c index 9d37d26f9e..fdd875034b 100644 --- a/env/fat.c +++ b/env/fat.c @@ -32,7 +32,12 @@ DECLARE_GLOBAL_DATA_PTR; -static char *env_fat_device_and_part(void) +__weak const char *env_fat_get_intf(void) +{ + return (const char *)CONFIG_ENV_FAT_INTERFACE; +} + +__weak char *env_fat_get_dev_part(void) { #ifdef CONFIG_MMC static char *part_str; @@ -60,13 +65,14 @@ static int env_fat_save(void) int dev, part; int err; loff_t size; + const char *ifname = env_fat_get_intf(); + const char *dev_and_part = env_fat_get_dev_part(); err = env_export(&env_new); if (err) return err; - part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE, - env_fat_device_and_part(), + part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); if (part < 0) return 1; @@ -77,8 +83,7 @@ static int env_fat_save(void) * This printf is embedded in the messages from env_save that * will calling it. The missing \n is intentional. */ - printf("Unable to use %s %d:%d... ", - CONFIG_ENV_FAT_INTERFACE, dev, part); + printf("Unable to use %s %d:%d... ", ifname, dev, part); return 1; } @@ -93,8 +98,7 @@ static int env_fat_save(void) * This printf is embedded in the messages from env_save that * will calling it. The missing \n is intentional. */ - printf("Unable to write \"%s\" from %s%d:%d... ", - file, CONFIG_ENV_FAT_INTERFACE, dev, part); + printf("Unable to write \"%s\" from %s%d:%d... ", file, ifname, dev, part); return 1; } @@ -117,14 +121,15 @@ static int env_fat_load(void) struct disk_partition info; int dev, part; int err1; + const char *ifname = env_fat_get_intf(); + const char *dev_and_part = env_fat_get_dev_part(); #ifdef CONFIG_MMC - if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "mmc")) + if (!strcmp(ifname, "mmc")) mmc_initialize(NULL); #endif - part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE, - env_fat_device_and_part(), + part = blk_get_device_part_str(ifname, dev_and_part, &dev_desc, &info, 1); if (part < 0) goto err_env_relocate; @@ -135,8 +140,7 @@ static int env_fat_load(void) * This printf is embedded in the messages from env_save that * will calling it. The missing \n is intentional. */ - printf("Unable to use %s %d:%d... ", - CONFIG_ENV_FAT_INTERFACE, dev, part); + printf("Unable to use %s %d:%d... ", ifname, dev, part); goto err_env_relocate; } @@ -154,7 +158,7 @@ static int env_fat_load(void) * will calling it. The missing \n is intentional. */ printf("Unable to read \"%s\" from %s%d:%d... ", - CONFIG_ENV_FAT_FILE, CONFIG_ENV_FAT_INTERFACE, dev, part); + CONFIG_ENV_FAT_FILE, ifname, dev, part); goto err_env_relocate; } diff --git a/include/env_internal.h b/include/env_internal.h index 174c3b1a79..e42ae826ef 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -245,6 +245,26 @@ const char *env_ext4_get_dev_part(void); * @return an enum env_location value on success, or -ve error code. */ enum env_location env_get_location(enum env_operation op, int prio); + +/** + * env_fat_get_intf() - Provide the interface for env in FAT + * + * It is a weak function allowing board to overidde the default interface for + * U-Boot env in FAT: CONFIG_ENV_FAT_INTERFACE + * + * @return string of interface, empty if not supported + */ +const char *env_fat_get_intf(void); + +/** + * env_fat_get_dev_part() - Provide the device and partition for env in FAT + * + * It is a weak function allowing board to overidde the default device and + * partition used for U-Boot env in FAT: CONFIG_ENV_FAT_DEVICE_AND_PART + * + * @return string of device and partition + */ +char *env_fat_get_dev_part(void) #endif /* DO_DEPS_ONLY */ #endif /* _ENV_INTERNAL_H_ */ -- 2.17.1

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[PATCH V3 00/16] Add support for J721E SK
by Sinthu Raja 17 Feb '22

17 Feb '22

From: Sinthu Raja <sinthu.raja(a)ti.com> Hi All, This series adds support for J721E SK [1]. Below is the detailed description of the J721E SoC and the SK board supporting features. The arch/arm/dts/k3-j721e-r5-sk.dts been queued up in linux-next [2]. Changes in V3: Addressed review comments such as * Removed board_info in the SPL build. https://patchwork.ozlabs.org/project/uboot/patch/20210626145602.15702-2-sin… * Removed K3-generic function call from mach-k3/j721e_init.c * Updated the conditional check to be a positive check for the board(s) which may have daugther cards * Re-order the code in board/ti/j721e/evm.c so that everything is under a single #ifdef Changes in V2: Board name updated from EAIK to SK. * So changed the occurrences of EAIK to SK. * Rename files from eaik to sk. [1] https://www.ti.com/tool/SK-TDA4VM [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/ar… V2: https://patchwork.ozlabs.org/project/uboot/cover/20211102140558.32460-1-sin… V1: https://patchwork.ozlabs.org/project/uboot/cover/20210626145602.15702-1-sin… Sinthu Raja (16): drivers: power: pmic: Add support for tps659412 PMIC drivers: power: regulator: tps65941_regulator: Add support for 3Phase buck board: ti: j721e: Guard functions with right #ifdef to avoid build warnings board: ti: j721e: Enable support for reading EEPROM at next alternate address board: ti: j721e: Add support to update board_name for j721e-sk board: ti: j721e: Disable probing of daughtercards board: ti: j721e: Add support for detecting multiple device trees arm: j721e: Add support for selecting DT based on board name arm: dts: k3-j721e-r5-common-proc-board: Do not use power-domains for I2C arm: dts: k3-j721e-sk: Add initial A72 specific dts support arm: dts: k3-j721e-r5-sk: Add initial R5 specific dts support for j721e-sk configs: j721e_evm_r5: Enable support for building multiple dtbs into FIT configs: j721e_evm_a72: Add SK dtb as part of DTB FIT configs: j721e_evm_a72: Align OSPI partitions on erase block boundary configs: j721e_evm: Store env in MMC FAT partition include: configs: Update env for selecting right dtb arch/arm/dts/Makefile | 4 +- .../arm/dts/k3-j721e-r5-common-proc-board.dts | 5 + arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi | 31 + arch/arm/dts/k3-j721e-r5-sk.dts | 646 ++++++++++++++ arch/arm/dts/k3-j721e-sk-u-boot.dtsi | 280 +++++++ arch/arm/dts/k3-j721e-sk.dts | 791 ++++++++++++++++++ arch/arm/mach-k3/j721e_init.c | 58 ++ board/ti/j721e/evm.c | 122 +-- configs/j721e_evm_a72_defconfig | 11 +- configs/j721e_evm_r5_defconfig | 4 + drivers/power/pmic/tps65941.c | 1 + drivers/power/regulator/tps65941_regulator.c | 2 + include/configs/j721e_evm.h | 4 + 13 files changed, 1907 insertions(+), 52 deletions(-) create mode 100644 arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-j721e-r5-sk.dts create mode 100644 arch/arm/dts/k3-j721e-sk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-j721e-sk.dts -- 2.35.0

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[PATCH 0/2] EMIF tool update to 0.6.1
by Sinthu Raja 17 Feb '22

17 Feb '22

From: Sinthu Raja <sinthu.raja(a)ti.com> Hi All, This patch series introduces a new lpddr4 config file for the J7 SK board. Also, an update to the SK R5 dts file to point to the new DDR configuration file This patch series shall be merged after this [1] patch series. [1] https://lore.kernel.org/all/20211102140558.32460-1-sinthu.raja@ti.com/ Sinthu Raja (2): arm: dts: k3-j721e-sk: EMIF tool update to 0.6.1 with 4266MTs for lpddr4 arm: dts: k3-j721e-r5-sk: Update R5 DT to pick the new DDR config arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi | 2196 ++++++++++++++++++++ arch/arm/dts/k3-j721e-r5-sk.dts | 2 +- 2 files changed, 2197 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi -- 2.31.1

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[PULL] u-boot-usb/master
by Marek Vasut 17 Feb '22

17 Feb '22

The following changes since commit ab8903a24db11571d634ef255976bb364c3ba64d: configs: Resync with savedefconfig (2022-02-14 22:21:29 +0000) are available in the Git repository at: git://source.denx.de/u-boot-usb.git master for you to fetch changes up to d5daa02d8d9e7c403a3339db1966e8413e64e408: usb: xhci: reset endpoint on USB stall (2022-02-16 17:11:31 +0100) ---------------------------------------------------------------- Angus Ainslie (2): usb: dwc3: dwc3-generic: check the parent nodes usb: dwc3: core: stop the core when it's removed Stefan Agner (1): usb: xhci: reset endpoint on USB stall drivers/usb/dwc3/core.c | 9 +++++++++ drivers/usb/dwc3/dwc3-generic.c | 25 ++++++++++++++++++++----- drivers/usb/host/xhci-ring.c | 31 +++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+), 5 deletions(-)

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[PATCH 1/7] microblaze: exception: move privileged instruction exception out of v5 ifdef
by Ovidiu Panait 17 Feb '22

17 Feb '22

The privileged instruction exception seems to have been introduced in microblaze v7.00 along with MMU support, so having it wrapped in MICROBLAZE_v5 ifdefs seems incorrect. Move it out of the ifdef, since all recent microblaze versions support it. Signed-off-by: Ovidiu Panait <ovidiu.panait(a)windriver.com> --- arch/microblaze/cpu/exception.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c index e9476abedb..f60f1fc693 100644 --- a/arch/microblaze/cpu/exception.c +++ b/arch/microblaze/cpu/exception.c @@ -37,10 +37,10 @@ void _hw_exception_handler (void) case 0x5: puts("Divide by zero exception\n"); break; -#ifdef MICROBLAZE_V5 case 0x7: puts("Priviledged or stack protection violation exception\n"); break; +#ifdef MICROBLAZE_V5 case 0x1000: puts("Exception in delay slot\n"); break; -- 2.25.1

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