February 2022 - U-Boot

[PATCH 1/2] ARM: dts: logicpd-som-lv: Resync DTS files with Linux 5.17-rc5
by Adam Ford 14 Mar '22

14 Mar '22

Resync the DTS files for the Logic PD SOM-LV with Linux 5.17-rc5 with some additional pending changes to address issues with wrong pin-muxing on the OMAP35. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts index f7a841a288..f690bc83bf 100644 --- a/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts +++ b/arch/arm/dts/logicpd-som-lv-35xx-devkit.dts @@ -9,5 +9,19 @@ / { model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit"; - compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3"; + compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3"; +}; + +&omap3_pmx_core2 { + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; }; diff --git a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts index a604d92221..e28e9625be 100644 --- a/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts +++ b/arch/arm/dts/logicpd-som-lv-37xx-devkit.dts @@ -11,3 +11,17 @@ model = "LogicPD Zoom DM3730 SOM-LV Development Kit"; compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"; }; + +&omap3_pmx_core2 { + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; +}; diff --git a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/dts/logicpd-som-lv-baseboard.dtsi index 100396f6c2..7d0468a237 100644 --- a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi +++ b/arch/arm/dts/logicpd-som-lv-baseboard.dtsi @@ -51,6 +51,8 @@ &mcbsp2 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; }; &charger { @@ -77,7 +79,7 @@ }; &dss { - status = "ok"; + status = "okay"; vdds_dsi-supply = <&vpll2>; vdda_video-supply = <&video_reg>; pinctrl-names = "default"; @@ -102,35 +104,18 @@ regulator-max-microvolt = <3300000>; }; - lcd0: display@0 { - compatible = "panel-dpi"; - label = "28"; - status = "okay"; - /* default-on; */ + lcd0: display { + /* This isn't the exact LCD, but the timings meet spec */ + compatible = "logicpd,type28"; pinctrl-names = "default"; pinctrl-0 = <&lcd_enable_pin>; - enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ + backlight = <&bl>; + enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; }; }; - - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <3>; - vfront-porch = <2>; - vsync-len = <11>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; }; bl: backlight { diff --git a/arch/arm/dts/logicpd-som-lv.dtsi b/arch/arm/dts/logicpd-som-lv.dtsi index b56524cc7f..385bc8d793 100644 --- a/arch/arm/dts/logicpd-som-lv.dtsi +++ b/arch/arm/dts/logicpd-som-lv.dtsi @@ -27,6 +27,8 @@ /* HS USB Host PHY on PORT 1 */ hsusb2_phy: hsusb2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_reset_pin>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ #phy-cells = <0>; @@ -144,6 +146,8 @@ }; &usbhshost { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_pins>, <&hsusb2_2_pins>; port2-mode = "ehci-phy"; }; @@ -153,8 +157,6 @@ &omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_pins>; mmc3_pins: pinmux_mm3_pins { pinctrl-single,pins = < @@ -166,6 +168,7 @@ OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */ >; }; + mcbsp2_pins: pinmux_mcbsp2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ @@ -183,6 +186,7 @@ OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ >; }; + mcspi1_pins: pinmux_mcspi1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ @@ -250,13 +254,13 @@ }; &omap3_pmx_wkup { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_reset_pin>; + hsusb2_reset_pin: pinmux_hsusb1_reset_pin { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ >; }; + wl127x_gpio: pinmux_wl127x_gpio_pin { pinctrl-single,pins = < OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ @@ -265,21 +269,6 @@ }; }; -&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb2_2_pins>; - hsusb2_2_pins: pinmux_hsusb2_2_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ - OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ - OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ - OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ - >; - }; -}; - &uart2 { interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; pinctrl-names = "default"; -- 2.34.1

2 3

[PATCH] ARM: am3517-evm: Remove more non-DM legacy ethernet reset code
by Adam Ford 14 Mar '22

14 Mar '22

The ethernet controller is DM compliant, and the device tree defines it. There is no need to manually handle pulling the ethernet out of reset. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index f014165928..e787441c74 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -117,17 +117,10 @@ static void am3517_evm_musb_init(void) */ int misc_init_r(void) { - u32 reset; - omap_die_id_display(); am3517_evm_musb_init(); - /* ensure that the Ethernet module is out of reset */ - reset = readl(AM3517_IP_SW_RESET); - reset &= (~CPGMACSS_SW_RST); - writel(reset, AM3517_IP_SW_RESET); - return 0; } @@ -142,7 +135,6 @@ void set_muxconf_regs(void) MUX_AM3517EVM(); } - #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) int board_eth_init(struct bd_info *bis) { -- 2.34.1

3 2

[PATCH 1/4] ARM: omap3_beagle: Remove non-DM initialization
by Romain Naour 14 Mar '22

14 Mar '22

With DM_MMC working for both SPL and U-Boot, this patch removes the legacy style of initializing the MMC driver. Based on omap3_logic: 42140dd0962bc134c0aad27524d0f4cc3955f255. Signed-off-by: Romain Naour <romain.naour(a)gmail.com> --- board/ti/beagle/beagle.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 888a958491..d5a122af2b 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -500,13 +500,6 @@ void set_muxconf_regs(void) MUX_BEAGLE(); } -#if defined(CONFIG_MMC) -int board_mmc_init(struct bd_info *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - #if defined(CONFIG_MMC) void board_mmc_power_init(void) { -- 2.35.1

2 7

[PATCH v2 0/3] J721E: Fix initialization of QSGMII PHY
by Aswath Govindraju 14 Mar '22

14 Mar '22

The following series of patches, - Fix the initialization of QSGMII PHY such that it is only applicable to J721E EVM - Remove the default setting of dorprocboot - Add boot_rprocs command in the GP bootcmd - Add phy initialization command in hs bootcmd Changes since v1: - Add checks such that the QSGMII PHY initialization is only applicable for J721E EVM - Rearranged the order of PHY initialization and boot_rpocs in the bootcmd - Added reported-bys - Split the fix into two patches. Aswath Govindraju (3): include: configs: j721e_evm.h: Fix the env variable corresponding to QSGMII PHY init configs: j721e_evm_a72_defconfig: Fix the bootcmd configs: j721e_hs_evm_a72_defconfig: Add command for initializing QSGMII PHY configs/j721e_evm_a72_defconfig | 2 +- configs/j721e_hs_evm_a72_defconfig | 2 +- include/configs/j721e_evm.h | 19 +++++++++++++++++-- 3 files changed, 19 insertions(+), 4 deletions(-) -- 2.17.1

2 6

[PATCH] ram: aspeed: Rework kconfig options
by Joel Stanley 14 Mar '22

14 Mar '22

Ensure the ASPEED related options are grouped together under the RAM option when enabling support. This also makes some minor grammar corrections and renames options so they present cleanly in menuconfig. There should be no functional change to the configuration or binary. Signed-off-by: Joel Stanley <joel(a)jms.id.au> --- drivers/ram/aspeed/Kconfig | 91 +++++++++++++++++++++----------------- 1 file changed, 51 insertions(+), 40 deletions(-) diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig index 576d5af8688e..0deab8649b64 100644 --- a/drivers/ram/aspeed/Kconfig +++ b/drivers/ram/aspeed/Kconfig @@ -1,66 +1,77 @@ -if RAM || SPL_RAM +menuconfig ASPEED_RAM + bool "ASPEED SDRAM configuration" + depends on RAM && ARCH_ASPEED + default ARCH_ASPEED + help + Configuration options for DDR SDRAM on ASPEED systems. + + RAM initialisation is always built in for the platform. This menu + allows customisation of the configuration used. + +if ASPEED_RAM config ASPEED_DDR4_DUALX8 bool "Enable Dual X8 DDR4 die" - depends on DM && OF_CONTROL && ARCH_ASPEED + depends on ASPEED_RAM + help + Say Y if dual X8 DDR4 die is used on the board. The ASPEED DDRM + SRAM controller needs to know if the memory chip mounted on the + board is dual x8 die or not, otherwise it may get the wrong + size of the memory space. + +config ASPEED_BYPASS_SELFTEST + depends on ASPEED_RAM + depends on ASPEED_AST2600 + bool "Bypass self test during initialization" + help + Say Y here to bypass DRAM self test to speed up the boot time. + +config ASPEED_ECC + bool "ASPEED SDRAM ECC" + depends on ASPEED_RAM + depends on ASPEED_AST2600 help - Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram - controller needs to know if the memory chip mounted on the board is dual - x8 die or not. Or it may get the wrong size of the memory space. + Enable SDRAM ECC function. This configures the SDRAM controller to + perform error detection and correction, sacrificing 1/9th of the + installed RAM to do so. -if ASPEED_AST2600 + +config ASPEED_ECC_SIZE + int "ECC size: 0=driver auto-caluated" + depends on ASPEED_ECC + default 0 + help + SDRAM size with the error correcting code enabled. The unit is + in Megabytes. Noted that only the 8/9 of the configured size + can be used by the system. The remaining 1/9 will be used by + the ECC engine. If the size is set to 0, the sdram driver will + calculate the SDRAM size and set the whole range be ECC enabled. choice - prompt "DDR4 target date rate" + prompt "AST2600 DDR4 target date rate" default ASPEED_DDR4_1600 + depends on ASPEED_RAM + depends on ASPEED_AST2600 config ASPEED_DDR4_400 - bool "DDR4 targets at 400Mbps" - depends on DM && OF_CONTROL && ARCH_ASPEED + bool "400Mbps" help select DDR4 target data rate at 400M config ASPEED_DDR4_800 - bool "DDR4 targets at 800Mbps" - depends on DM && OF_CONTROL && ARCH_ASPEED + bool "800Mbps" help select DDR4 target data rate at 800M config ASPEED_DDR4_1333 - bool "DDR4 targets at 1333Mbps" - depends on DM && OF_CONTROL && ARCH_ASPEED + bool "1333Mbps" help select DDR4 target data rate at 1333M config ASPEED_DDR4_1600 - bool "DDR4 targets at 1600Mbps" - depends on DM && OF_CONTROL && ARCH_ASPEED + bool "1600Mbps" help select DDR4 target data rate at 1600M endchoice -config ASPEED_BYPASS_SELFTEST - bool "bypass self test during DRAM initialization" - help - Say Y here to bypass DRAM self test to speed up the boot time - -config ASPEED_ECC - bool "aspeed SDRAM error correcting code" - depends on DM && OF_CONTROL && ARCH_ASPEED - help - enable SDRAM ECC function - -if ASPEED_ECC -config ASPEED_ECC_SIZE - int "ECC size: 0=driver auto-caluated" - depends on ASPEED_ECC - default 0 - help - SDRAM size with the error correcting code enabled. The unit is - in Megabytes. Noted that only the 8/9 of the configured size - can be used by the system. The remaining 1/9 will be used by - the ECC engine. If the size is set to 0, the sdram driver will - calculate the SDRAM size and set the whole range be ECC enabled. -endif # end of ASPEED_ECC -endif # end of ASPEED_AST2600 -endif # end of RAM || SPL_RAM +endif # End of ASPEED_RAM -- 2.34.1

3 2

ARM: socfpga: gen5: release reset before using USB as device with ums
by Wolfgang Grandegger 14 Mar '22

14 Mar '22

The command "ums 0 mmc 0" does not work because the USB port is still in reset. Releasing it in board_usb_init() fixes the problem. This issue has been observed and fixed on the Aries MCVEVP board. Signed-off-by: Wolfgang Grandegger <wg(a)aries-embedded.de> --- arch/arm/dts/socfpga_cyclone5_mcvevk.dts | 1 + arch/arm/mach-socfpga/board.c | 8 ++++++++ arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h | 2 ++ 3 files changed, 11 insertions(+) diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts index ceaec29770..a673837f25 100644 --- a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts @@ -12,6 +12,7 @@ aliases { ethernet0 = &gmac0; stmpe-i2c0 = &stmpe1; + udc0 = &usb1; }; chosen { diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 7267163222..a2eed73fe9 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -83,6 +83,14 @@ int board_usb_init(int index, enum usb_init_type init) /* Patch the address from OF into the controller pdata. */ socfpga_otg_data.regs_otg = addr; +#ifdef CONFIG_TARGET_SOCFPGA_GEN5 + /* First release reset of the USB port */ + if (addr == SOCFPGA_USB0_ADDRESS) + socfpga_per_reset(SOCFPGA_RESET(USB0), 0); + else if (addr == SOCFPGA_USB1_ADDRESS) + socfpga_per_reset(SOCFPGA_RESET(USB1), 0); +#endif + return dwc2_udc_probe(&socfpga_otg_data); } diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h index d108eac1e2..611403cf00 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h @@ -31,6 +31,8 @@ void socfpga_bridges_reset(int enable); */ #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_USB0 RSTMGR_DEFINE(1, 2) +#define RSTMGR_USB1 RSTMGR_DEFINE(1, 3) #define RSTMGR_NAND RSTMGR_DEFINE(1, 4) #define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) #define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) -- 2.25.1

2 5

[PATCH] drivers/adc/rockchip-saradc: remove double semi-colon
by Giulio Benetti 14 Mar '22

14 Mar '22

Signed-off-by: Giulio Benetti <giulio.benetti(a)benettiengineering.com> --- drivers/adc/rockchip-saradc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index e464d33f22..e0cbab6aa0 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -131,7 +131,7 @@ int rockchip_saradc_of_to_plat(struct udevice *dev) } priv->data = data; - uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;; + uc_pdata->data_mask = (1 << priv->data->num_bits) - 1; uc_pdata->data_format = ADC_DATA_FORMAT_BIN; uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5; uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1; -- 2.25.1

2 4

[PATCH v2] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON when necessary
by haibo.chen＠nxp.com 14 Mar '22

14 Mar '22

From: Haibo Chen <haibo.chen(a)nxp.com> After commit f132aab40327 ("Revert "mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it involve issue in mmc_switch_voltage(), because of the special design of usdhc. For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these are reserved bits(Though RM contain the definition of these bits, but actually internal IC logic do not implement, already confirm with IC team). Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card clock output. Here is the definition of this bit in RM: [8] FRC_SDCLK_ON Force CLK output active Do not set this bit to 1 unless it is necessary. Also, make sure that this bit is cleared when uSDHC’s clock is about to be changed (frequency change, clock source change, or delay chain tuning). 0b - CLK active or inactive is fully controlled by the hardware. 1b - Force CLK active In default, the FRC_SDCLK_ON is 0. This means, when there is no command or data transfer on bus, hardware will gate off the card clock. But in some case, we need the card clock keep on. Take IO voltage 1.8v switch as example, after IO voltage change to 1.8v, spec require gate off the card clock for 5ms, and gate on the clock back, once detect the card clock on, then the card will draw the dat0 to high immediately. If there is not clock gate off/on behavior, some card will keep the dat0 to low level. This is the reason we fail in mmc_switch_voltage(). To fix this issue, and concern that this is only the fsl usdhc hardware design limitation, set the bit FRC_SDCLK_ON in the beginning of the wait_dat0() and clear it in the end. To make sure the 1.8v IO voltage switch process align with SD specification. For standard tuning process, usdhc specification also require the card clock keep on, so also add these behavior in fsl_esdhc_execute_tuning(). Reviewed-by: Marek Vasut <marex(a)denx.de> Tested-by: Fabio Estevam <festevam(a)gmail.com> Signed-off-by: Haibo Chen <haibo.chen(a)nxp.com> --- drivers/mmc/fsl_esdhc_imx.c | 25 ++++++++++++++++++++++--- include/fsl_esdhc_imx.h | 2 ++ 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 9299635f50..e0108144e7 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -831,13 +831,16 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) struct mmc *mmc = &plat->mmc; u32 irqstaten = esdhc_read32(&regs->irqstaten); u32 irqsigen = esdhc_read32(&regs->irqsigen); - int i, ret = -ETIMEDOUT; - u32 val, mixctrl; + int i, err, ret = -ETIMEDOUT; + u32 val, mixctrl, tmp; /* clock tuning is not needed for upto 52MHz */ if (mmc->clock <= 52000000) return 0; + /* make sure the card clock keep on */ + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */ if (priv->flags & ESDHC_FLAG_STD_TUNING) { val = esdhc_read32(&regs->autoc12err); @@ -897,6 +900,12 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) esdhc_stop_tuning(mmc); + /* change to default setting, let host control the card clock */ + esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + err = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (err) + dev_warn(dev, "card clock not gate off as expect.\n"); + return ret; } #endif @@ -1555,14 +1564,24 @@ static int __maybe_unused fsl_esdhc_set_enhanced_strobe(struct udevice *dev) static int fsl_esdhc_wait_dat0(struct udevice *dev, int state, int timeout_us) { - int ret; + int ret, err; u32 tmp; struct fsl_esdhc_priv *priv = dev_get_priv(dev); struct fsl_esdhc *regs = priv->esdhc_regs; + /* make sure the card clock keep on */ + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, !!(tmp & PRSSTAT_DAT0) == !!state, timeout_us); + + /* change to default setting, let host control the card clock */ + esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + err = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (err) + dev_warn(dev, "card clock not gate off as expect.\n"); + return ret; } diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index 2153f29bef..b8efd2a166 100644 --- a/include/fsl_esdhc_imx.h +++ b/include/fsl_esdhc_imx.h @@ -37,6 +37,7 @@ #define VENDORSPEC_HCKEN 0x00001000 #define VENDORSPEC_IPGEN 0x00000800 #define VENDORSPEC_INIT 0x20007809 +#define VENDORSPEC_FRC_SDCLK_ON 0x00000100 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) @@ -94,6 +95,7 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_SDOFF (0x00000080) #define PRSSTAT_SDSTB (0X00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) -- 2.17.1

4 4

[PATCH 1/2] arm64: dts: rk3399-rock-pi-4b-u-boot: add optee node
by Peter Griffin 14 Mar '22

14 Mar '22

Allow u-boot to probe optee so we can access secure os from the bootloader. Signed-off-by: Peter Griffin <peter.griffin(a)linaro.org> --- arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi index 85ee5770ad..95ca99ecbc 100644 --- a/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi @@ -4,3 +4,13 @@ */ #include "rk3399-rock-pi-4-u-boot.dtsi" + +/ { + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + +}; -- 2.25.1

3 4

[PATCH 1/2] arm64: dts: rk3399-rock-pi-4b-u-boot: add optee node
by Peter Griffin 14 Mar '22

14 Mar '22

Allow u-boot to probe optee so we can access secure os from the bootloader. Signed-off-by: Peter Griffin <peter.griffin(a)linaro.org> --- arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi index 85ee5770ad..95ca99ecbc 100644 --- a/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi @@ -4,3 +4,13 @@ */ #include "rk3399-rock-pi-4-u-boot.dtsi" + +/ { + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + +}; -- 2.25.1

2 1