February 2022 - U-Boot

[PATCH v1 0/5] Move board specific files to board directory
by Troy Kisky 16 Mar '22

16 Mar '22

This series intends to let board specific files live in the boards directory. The last patch moves files for nitrogen6x. I have tested it with buildman ./tools/buildman/buildman boundary -b denx_master But it is likely the more scripts then just tools/genboardscfg.py would need to be updated. Troy Kisky (5): kconfig: allow defconfigs to live in board directory dts: allow dts files in board directory scripts: Makefile.autoconf: allow CONFIG_SYS_CONFIG_NAME file to live in board directory genboardcfg: allow defconfigs in board directory nitrogen6x: move board specific files to nitrogen6x directory arch/arm/dts/Makefile | 3 -- board/boundary/nitrogen6x/MAINTAINERS | 13 ------- board/boundary/nitrogen6x/Makefile | 13 +++++++ .../nitrogen6x}/imx6dl-nitrogen6x.dts | 0 .../boundary/nitrogen6x}/imx6q-nitrogen6x.dts | 0 .../boundary/nitrogen6x}/imx6q-sabrelite.dts | 0 .../nitrogen6x}/imx6qdl-nitrogen6x.dtsi | 0 .../nitrogen6x}/imx6qdl-sabrelite.dtsi | 0 .../nitrogen6x}/mx6qsabrelite_defconfig | 0 .../nitrogen6x}/nitrogen6dl2g_defconfig | 0 .../nitrogen6x}/nitrogen6dl_defconfig | 0 .../nitrogen6x}/nitrogen6q2g_defconfig | 0 .../boundary/nitrogen6x}/nitrogen6q_defconfig | 0 .../nitrogen6x}/nitrogen6s1g_defconfig | 0 .../boundary/nitrogen6x}/nitrogen6s_defconfig | 0 .../boundary/nitrogen6x}/nitrogen6x.h | 2 +- dts/Makefile | 11 +++++- scripts/Makefile.autoconf | 9 ++++- scripts/Makefile.lib | 1 + scripts/kconfig/Makefile | 9 ++++- tools/genboardscfg.py | 37 ++++++++++++++++++- 21 files changed, 75 insertions(+), 23 deletions(-) rename {arch/arm/dts => board/boundary/nitrogen6x}/imx6dl-nitrogen6x.dts (100%) rename {arch/arm/dts => board/boundary/nitrogen6x}/imx6q-nitrogen6x.dts (100%) rename {arch/arm/dts => board/boundary/nitrogen6x}/imx6q-sabrelite.dts (100%) rename {arch/arm/dts => board/boundary/nitrogen6x}/imx6qdl-nitrogen6x.dtsi (100%) rename {arch/arm/dts => board/boundary/nitrogen6x}/imx6qdl-sabrelite.dtsi (100%) rename {configs => board/boundary/nitrogen6x}/mx6qsabrelite_defconfig (100%) rename {configs => board/boundary/nitrogen6x}/nitrogen6dl2g_defconfig (100%) rename {configs => board/boundary/nitrogen6x}/nitrogen6dl_defconfig (100%) rename {configs => board/boundary/nitrogen6x}/nitrogen6q2g_defconfig (100%) rename {configs => board/boundary/nitrogen6x}/nitrogen6q_defconfig (100%) rename {configs => board/boundary/nitrogen6x}/nitrogen6s1g_defconfig (100%) rename {configs => board/boundary/nitrogen6x}/nitrogen6s_defconfig (100%) rename {include/configs => board/boundary/nitrogen6x}/nitrogen6x.h (98%) -- 2.32.0

3 25

[PATCH v3 1/6] rockchip: move ROCKCHIP_STIMER_BASE to Kconfig
by Johan Jonker 16 Mar '22

16 Mar '22

Move ROCKCHIP_STIMER_BASE to Kconfig. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- Changed V3: add ROCKCHIP_STIMER --- arch/arm/mach-rockchip/Kconfig | 22 ++++++++++++++++++++++ arch/arm/mach-rockchip/px30/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3036/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3128/Kconfig | 3 +++ arch/arm/mach-rockchip/rk322x/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3288/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3308/Kconfig | 10 ++++++---- arch/arm/mach-rockchip/rk3328/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3368/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3399/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3568/Kconfig | 3 +++ include/configs/px30_common.h | 1 - include/configs/rk3036_common.h | 1 - include/configs/rk3128_common.h | 1 - include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rk3308_common.h | 1 - include/configs/rk3328_common.h | 1 - include/configs/rk3368_common.h | 1 - include/configs/rk3399_common.h | 1 - include/configs/rk3568_common.h | 1 - 21 files changed, 55 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index da6871eb..7a624c64 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -343,6 +343,28 @@ config ROCKCHIP_BOOT_MODE_REG The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) according to the value from this register. +config ROCKCHIP_STIMER + bool "Rockchip STIMER support" + default y + depends on (ROCKCHIP_PX30|| \ + ROCKCHIP_RK3036|| \ + ROCKCHIP_RK3128|| \ + ROCKCHIP_RK322X|| \ + ROCKCHIP_RK3288|| \ + ROCKCHIP_RK3308|| \ + ROCKCHIP_RK3328|| \ + ROCKCHIP_RK3368|| \ + ROCKCHIP_RK3399|| \ + ROCKCHIP_RK3568) + help + Enable Rockchip STIMER support. + +config ROCKCHIP_STIMER_BASE + hex "Rockchip secure timer base address" + depends on ROCKCHIP_STIMER + help + Rockchip secure timer base address. + config ROCKCHIP_SPL_RESERVE_IRAM hex "Size of IRAM reserved in SPL" default 0 diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index aa5cc471..42cc111b 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -30,6 +30,9 @@ config TARGET_PX30_CORE config ROCKCHIP_BOOT_MODE_REG default 0xff010200 +config ROCKCHIP_STIMER_BASE + default 0xff220020 + config SYS_SOC default "px30" diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index b746795d..111531be 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -16,6 +16,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0x200081c8 +config ROCKCHIP_STIMER_BASE + default 0x200440a0 + config SYS_SOC default "rk3036" diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig index b867401c..9cc494eb 100644 --- a/arch/arm/mach-rockchip/rk3128/Kconfig +++ b/arch/arm/mach-rockchip/rk3128/Kconfig @@ -16,6 +16,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0x100a0038 +config ROCKCHIP_STIMER_BASE + default 0x200440a0 + config SYS_SOC default "rk3128" diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 6458cd55..058f848d 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -8,6 +8,9 @@ config TARGET_EVB_RK3229 config ROCKCHIP_BOOT_MODE_REG default 0x110005c8 +config ROCKCHIP_STIMER_BASE + default 0x110d0020 + config SYS_SOC default "rk322x" diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index f37b1bdf..dd8c7826 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -148,6 +148,9 @@ config ROCKCHIP_FAST_SPL config ROCKCHIP_BOOT_MODE_REG default 0xff730094 +config ROCKCHIP_STIMER_BASE + default 0xff810020 + config SYS_SOC default "rk3288" diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 8fa536e1..194353e4 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -8,6 +8,12 @@ config TARGET_ROC_RK3308_CC bool "Firefly roc-rk3308-cc" select BOARD_LATE_INIT +config ROCKCHIP_BOOT_MODE_REG + default 0xff000500 + +config ROCKCHIP_STIMER_BASE + default 0xff1b00a0 + config SYS_SOC default "rk3308" @@ -17,10 +23,6 @@ config SYS_MALLOC_F_LEN config SPL_SERIAL default y -config ROCKCHIP_BOOT_MODE_REG - default 0xff000500 - - source "board/rockchip/evb_rk3308/Kconfig" source "board/firefly/firefly-rk3308/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index d13a1690..f6f1e06a 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -15,6 +15,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff1005c8 +config ROCKCHIP_STIMER_BASE + default 0xff1d0020 + config SYS_SOC default "rk3328" diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 78eb96df..104db367 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -45,6 +45,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff738200 +config ROCKCHIP_STIMER_BASE + default 0xff830020 + config SYS_SOC default "rk3368" diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 17628f91..4bc15c1b 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -114,6 +114,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff320300 +config ROCKCHIP_STIMER_BASE + default 0xff8680a0 + config SYS_SOC default "rk3399" diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 201c63c2..4e7c02cc 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -9,6 +9,9 @@ config TARGET_EVB_RK3568 config ROCKCHIP_BOOT_MODE_REG default 0xfdc20200 +config ROCKCHIP_STIMER_BASE + default 0xfdd1c020 + config SYS_SOC default "rk3568" diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 09923871..dc609013 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020 #define COUNTER_FREQUENCY 24000000 /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index b133d8ec..10cba727 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_ARCH_TIMER #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 8b7a0bbb..71f66d57 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_ARCH_TIMER #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index a46b1ffe..aff24018 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ -#define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_ARCH_TIMER #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index abbb2739..c781bc7e 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_ARCH_TIMER #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 496f4628..edc535fe 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0 #define CONFIG_IRAM_BASE 0xfff80000 #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 #define CONFIG_SPL_STACK 0x00400000 diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index c1e26a01..8a5f0c89 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -10,7 +10,6 @@ #define CONFIG_IRAM_BASE 0xff090000 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 8b239ca0..239296c1 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -15,7 +15,6 @@ #define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_IRAM_BASE 0xff8c0000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index ed72c8bb..4037dba5 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define COUNTER_FREQUENCY 24000000 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0 #define CONFIG_IRAM_BASE 0xff8c0000 diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index afe5050e..705c3454 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define COUNTER_FREQUENCY 24000000 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020 #define CONFIG_IRAM_BASE 0xfdcc0000 -- 2.20.1

5 18

[PATCH] arm: dts: stm32mp15: alignment with v5.17
by Patrick Delaunay 15 Mar '22

15 Mar '22

Device tree alignment with Linux kernel v5.17-rc1 - ARM: dts: stm32: add pull-up to USART3 and UART7 RX pins on STM32MP15 DKx boards - ARM: dts: stm32: clean uart4_idle_pins_a node for stm32mp15 - ARM: dts: stm32: tune the HS USB PHYs on stm32mp15xx-dkx - ARM: dts: stm32: tune the HS USB PHYs on stm32mp157c-ev1 - ARM: dts: stm32: fix stusb1600 pinctrl used on stm32mp157c-dk Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/stm32mp15-pinctrl.dtsi | 32 ++++++++++++++--------------- arch/arm/dts/stm32mp157c-ev1.dts | 22 ++++++++++++++++++++ arch/arm/dts/stm32mp15xx-dkx.dtsi | 16 +++++++++++++++ 3 files changed, 54 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index d3553e0f01..6161f5906e 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -1718,7 +1718,7 @@ stusb1600_pins_a: stusb1600-0 { pins { - pinmux = <STM32_PINMUX('I', 11, ANALOG)>; + pinmux = <STM32_PINMUX('I', 11, GPIO)>; bias-pull-up; }; }; @@ -1737,20 +1737,20 @@ }; uart4_idle_pins_a: uart4-idle-0 { - pins1 { - pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ - }; - pins2 { - pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ - bias-disable; - }; + pins1 { + pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; }; uart4_sleep_pins_a: uart4-sleep-0 { - pins { + pins { pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ - }; + }; }; uart4_pins_b: uart4-1 { @@ -1816,7 +1816,7 @@ }; pins2 { pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ - bias-disable; + bias-pull-up; }; }; @@ -1826,7 +1826,7 @@ }; pins2 { pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ - bias-disable; + bias-pull-up; }; }; @@ -1971,7 +1971,7 @@ pins2 { pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ - bias-disable; + bias-pull-up; }; }; @@ -1988,7 +1988,7 @@ }; pins3 { pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ - bias-disable; + bias-pull-up; }; }; @@ -2012,7 +2012,7 @@ pins2 { pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ - bias-disable; + bias-pull-up; }; }; @@ -2029,7 +2029,7 @@ }; pins3 { pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ - bias-disable; + bias-pull-up; }; }; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 5c5b1ddf7b..e222d2d2cb 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -375,3 +375,25 @@ &usbphyc { status = "okay"; }; + +&usbphyc_port0 { + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; + +&usbphyc_port1 { + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 5502eec94b..f8130bf445 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -702,10 +702,26 @@ &usbphyc_port0 { phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; }; &usbphyc_port1 { phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; }; &vrefbuf { -- 2.25.1

3 5

[PATCH v3 1/2] ram: stm32mp1: Unconditionally enable ASR
by Marek Vasut 15 Mar '22

15 Mar '22

Enable DRAM ASR, auto self-refresh, unconditionally. This saves non-trivial amount of power both at runtime and in suspend (on 2x W632GU6NB-15 ~150mW). Reviewed-by: Patrice Chotard <patrice.chotard(a)foss.st.com> Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> --- V2: Rebase on latest changes in this driver past v2022.01 V3: - Use GENMASK / BIT macros - Add RB from Patrice --- drivers/ram/stm32mp1/stm32mp1_ddr.c | 25 ++++++++++++++++++++++++ drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 6 ++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index 4d78aa5cb13..528a171b454 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -27,6 +27,8 @@ #define RCC_DDRITFCR_DPHYAPBRST (BIT(17)) #define RCC_DDRITFCR_DPHYRST (BIT(18)) #define RCC_DDRITFCR_DPHYCTLRST (BIT(19)) +#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) +#define RCC_DDRITFCR_DDRCKMOD_ASR BIT(20) struct reg_desc { const char *name; @@ -651,6 +653,26 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, wait_sw_done_ack(ctl); } +static void stm32mp1_asr_enable(struct ddr_info *priv) +{ + struct stm32mp1_ddrctl *ctl = priv->ctl; + + clrsetbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCKMOD_MASK, + RCC_DDRITFCR_DDRCKMOD_ASR); + + start_sw_done(ctl); + + setbits_le32(&ctl->hwlpctl, DDRCTRL_HWLPCTL_HW_LP_EN); + writel(DDRCTRL_PWRTMG_POWERDOWN_TO_X32(0x10) | + DDRCTRL_PWRTMG_SELFREF_TO_X32(0x01), + &ctl->pwrtmg); + setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE); + setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN); + + setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + wait_sw_done_ack(ctl); +} + /* board-specific DDR power initializations. */ __weak int board_ddr_power_init(enum ddr_type ddr_type) { @@ -822,6 +844,9 @@ start: stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, config->c_reg.pwrctl); +/* Enable auto-self-refresh, which saves a bit of power at runtime. */ + stm32mp1_asr_enable(priv); + /* enable uMCTL2 AXI port 0 and 1 */ setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN); setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN); diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h index f1a26e31f6c..42be1ba57c7 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h +++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h @@ -265,8 +265,14 @@ struct stm32mp1_ddrphy { #define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) #define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) #define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32(n) (((n) & 0xff) << 16) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32(n) ((n) & 0x1f) + +#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0) + #define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16) -- 2.34.1

2 4

[PATCH] ARM: dts: stm32: Move vdd_io extras into Avenger96 extras
by Marek Vasut 15 Mar '22

15 Mar '22

The vdd_io regulator is present only on DHCOR SoM configured for 1V8 IO, as populated on Avenger96, but not present on 3V3 DHCOR SoM. Move these extras to Avenger96 u-boot DT extras. Fixes: 3919aa1722a ("ARM: dts: stm32: Add DFU support for DHCOR recovery") Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 4 ++++ arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi index 4b1dbf08387..dd6be7fc3c7 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -95,3 +95,7 @@ u-boot,force-b-session-valid; hnp-srp-disable; }; + +&vdd_io { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index ff9ca625bf5..704939d18ae 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -195,10 +195,6 @@ u-boot,dm-spl; }; -&vdd_io { - u-boot,dm-spl; -}; - &vdd_usb { u-boot,dm-spl; }; -- 2.34.1

3 7

[PATCH] ARM: dts: stm32: Add USB OTG pinctrl and regulator nodes into SPL DT on DHCOR
by Marek Vasut 15 Mar '22

15 Mar '22

Fix the following warning in SPL and make sure that even DTs which enforce Vbus detection using u-boot,force-vbus-detection;, the DFU in SPL will work. dwc2-udc-otg usb-otg@49000000: prop pinctrl-0 index 0 invalid phandle Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 71375510b4a..ff9ca625bf5 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -171,6 +171,14 @@ u-boot,dm-spl; }; +&usb33 { + u-boot,dm-spl; +}; + +&usbotg_hs_pins_a { + u-boot,dm-spl; +}; + &usbotg_hs { u-boot,dm-spl; }; -- 2.34.1

2 4

[PATCH] mtd: rawnand: stm32_fmc2: add NAND Write Protect support
by Christophe Kerello 15 Mar '22

15 Mar '22

This patch adds the support of the WP# signal. WP will be disabled before the first access to the NAND flash. Signed-off-by: Christophe Kerello <christophe.kerello(a)foss.st.com> --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index eee65949d77..fb3279b405e 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -12,6 +12,7 @@ #include <log.h> #include <nand.h> #include <reset.h> +#include <asm/gpio.h> #include <dm/device_compat.h> #include <linux/bitfield.h> #include <linux/bitops.h> @@ -149,6 +150,7 @@ struct stm32_fmc2_timings { struct stm32_fmc2_nand { struct nand_chip chip; struct stm32_fmc2_timings timings; + struct gpio_desc wp_gpio; int ncs; int cs_used[FMC2_MAX_CE]; }; @@ -824,6 +826,9 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node) nand->cs_used[i] = cs[i]; } + gpio_request_by_name_nodev(node, "wp-gpios", 0, &nand->wp_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + nand->chip.flash_node = node; return 0; @@ -972,6 +977,10 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev) chip->ecc.size = FMC2_ECC_STEP_SIZE; chip->ecc.strength = FMC2_ECC_BCH8; + /* Disable Write Protect */ + if (dm_gpio_is_valid(&nand->wp_gpio)) + dm_gpio_set_value(&nand->wp_gpio, 0); + ret = nand_scan_ident(mtd, nand->ncs, NULL); if (ret) return ret; -- 2.25.1

2 2

[PATCH 1/2] stm32mp: bsec: add permanent lock write support
by Patrick Delaunay 15 Mar '22

15 Mar '22

Add support of the permanent lock support in U-Boot proper when BSEC is not managed by secure monitor (TF-A SP_MIN or OP-TEE). This patch avoid issue with stm32key command and fuse command on basic boot for this missing feature of U-Boot BSEC driver. Reported-by: Johann Neuhauser <jneuhauser(a)dh-electronics.com> Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/mach-stm32mp/bsec.c | 90 +++++++++++++++++++++++++++++++++--- 1 file changed, 84 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 27d1829501..fd6e1a3957 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -18,6 +18,7 @@ #include <linux/iopoll.h> #define BSEC_OTP_MAX_VALUE 95 +#define BSEC_OTP_UPPER_START 32 #define BSEC_TIMEOUT_US 10000 /* BSEC REGISTER OFFSET (base relative) */ @@ -41,6 +42,7 @@ /* BSEC_CONTROL Register */ #define BSEC_READ 0x000 #define BSEC_WRITE 0x100 +#define BSEC_LOCK 0x200 /* LOCK Register */ #define OTP_LOCK_MASK 0x1F @@ -61,6 +63,11 @@ */ #define BSEC_LOCK_PROGRAM 0x04 +/* + * OTP status: bit 0 permanent lock + */ +#define BSEC_LOCK_PERM BIT(0) + /** * bsec_lock() - manage lock for each type SR/SP/SW * @address: address of bsec IP register @@ -284,6 +291,65 @@ static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp) return ret; } +/** + * bsec_permanent_lock_otp() - permanent lock of OTP in SAFMEM + * @dev: bsec IP device + * @base: base address of bsec IP + * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) + * Return: 0 if no error + */ +static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp) +{ + int ret; + bool power_up = false; + u32 val, addr; + + /* check if safemem is power up */ + if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) { + ret = bsec_power_safmem(base, true); + if (ret) + return ret; + + power_up = true; + } + + /* + * low OTPs = 2 bits word for low OTPs, 1 bits per word for upper OTP + * and only 16 bits used in WRDATA + */ + if (otp < BSEC_OTP_UPPER_START) { + addr = otp / 8; + val = 0x03 << ((otp * 2) & 0xF); + } else { + addr = BSEC_OTP_UPPER_START / 8 + + ((otp - BSEC_OTP_UPPER_START) / 16); + val = 0x01 << (otp & 0xF); + } + + /* set value in write register*/ + writel(val, base + BSEC_OTP_WRDATA_OFF); + + /* set BSEC_OTP_CTRL_OFF with the otp addr and lock request*/ + writel(addr | BSEC_WRITE | BSEC_LOCK, base + BSEC_OTP_CTRL_OFF); + + /* check otp status*/ + ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF, + val, (val & BSEC_MODE_BUSY_MASK) == 0, + BSEC_TIMEOUT_US); + if (ret) + return ret; + + if (val & BSEC_MODE_PROGFAIL_MASK) + ret = -EACCES; + else + ret = bsec_check_error(base, otp); + + if (power_up) + bsec_power_safmem(base, false); + + return ret; +} + /* BSEC MISC driver *******************************************************/ struct stm32mp_bsec_plat { u32 base; @@ -339,9 +405,14 @@ static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp) static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp) { struct stm32mp_bsec_plat *plat = dev_get_plat(dev); + u32 wrlock; /* return OTP permanent write lock status */ - *val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp); + wrlock = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp); + + *val = 0; + if (wrlock) + *val = BSEC_LOCK_PERM; return 0; } @@ -377,15 +448,22 @@ static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp) static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp) { - if (!IS_ENABLED(CONFIG_ARM_SMCCC) || IS_ENABLED(CONFIG_SPL_BUILD)) - return -ENOTSUPP; + struct stm32mp_bsec_plat *plat; + + /* only permanent write lock is supported in U-Boot */ + if (!(val & BSEC_LOCK_PERM)) { + dev_dbg(dev, "lock option without BSEC_LOCK_PERM: %x\n", val); + return 0; /* nothing to do */ + } - if (val == 1) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_WRLOCK_OTP, otp, 0); - if (val == 0) - return 0; /* nothing to do */ + + plat = dev_get_plat(dev); + + return bsec_permanent_lock_otp(dev, plat->base, otp); return -EINVAL; } -- 2.25.1

3 6

[PATCH] board: st: common: update test on misc_read result in command stboard
by Patrick Delaunay 15 Mar '22

15 Mar '22

Update management of misc_read/misc_write, which now returns length of data after the commit 8729b1ae2cbd ("misc: Update read() and write() methods to return bytes xfered"): raise a error when the result is not the expected length. Fixes: 658fde8a36ff ("board: stm32mp1: stboard: lock the OTP after programming") Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- board/st/common/cmd_stboard.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/st/common/cmd_stboard.c b/board/st/common/cmd_stboard.c index 2fba383168..c1ecd643b0 100644 --- a/board/st/common/cmd_stboard.c +++ b/board/st/common/cmd_stboard.c @@ -91,14 +91,14 @@ static int do_stboard(struct cmd_tbl *cmdtp, int flag, int argc, ret = misc_read(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD), &otp, sizeof(otp)); - if (ret < 0) { + if (ret != sizeof(otp)) { puts("OTP read error"); return CMD_RET_FAILURE; } ret = misc_read(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD), &lock, sizeof(lock)); - if (ret < 0) { + if (ret != sizeof(lock)) { puts("LOCK read error"); return CMD_RET_FAILURE; } @@ -172,7 +172,7 @@ static int do_stboard(struct cmd_tbl *cmdtp, int flag, int argc, ret = misc_write(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD), &otp, sizeof(otp)); - if (ret < 0) { + if (ret != sizeof(otp)) { puts("BOARD programming error\n"); return CMD_RET_FAILURE; } @@ -181,7 +181,7 @@ static int do_stboard(struct cmd_tbl *cmdtp, int flag, int argc, otp = 1; ret = misc_write(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD), &otp, sizeof(otp)); - if (ret < 0) { + if (ret != sizeof(otp)) { puts("BOARD lock error\n"); return CMD_RET_FAILURE; } -- 2.25.1

2 2

[PATCH] video: stm32: stm32_ltdc: fix the check of return value of clk_set_rate()
by Patrick Delaunay 15 Mar '22

15 Mar '22

From: Gabriel Fernandez <gabriel.fernandez(a)foss.st.com> The clk_set_rate() function returns rate as an 'ulong' not an 'int' and rate > 0 by default. This patch avoids to display the associated warning when the set rate function returns the new frequency. Fixes: aeaf330649e8 ("video: stm32: stm32_ltdc: add bridge to display controller") Signed-off-by: Gabriel Fernandez <gabriel.fernandez(a)foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/video/stm32/stm32_ltdc.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index 87e5fd54d9..e741e74739 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -338,6 +338,7 @@ static int stm32_ltdc_probe(struct udevice *dev) struct display_timing timings; struct clk pclk; struct reset_ctl rst; + ulong rate; int ret; priv->regs = (void *)dev_read_addr(dev); @@ -375,13 +376,13 @@ static int stm32_ltdc_probe(struct udevice *dev) } } - ret = clk_set_rate(&pclk, timings.pixelclock.typ); - if (ret) - dev_warn(dev, "fail to set pixel clock %d hz\n", - timings.pixelclock.typ); + rate = clk_set_rate(&pclk, timings.pixelclock.typ); + if (IS_ERR_VALUE(rate)) + dev_warn(dev, "fail to set pixel clock %d hz, ret=%ld\n", + timings.pixelclock.typ, rate); dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n", - timings.pixelclock.typ, clk_get_rate(&pclk)); + timings.pixelclock.typ, rate); ret = reset_get_by_index(dev, 0, &rst); if (ret) { -- 2.25.1

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