December 2022 - U-Boot

[PATCH 00/18] Add USB on SAM9X60, SAMA7G5 and SAMA5D2 boards
by Sergiu Moga 07 Dec '22

07 Dec '22

This series of patches is meant to add support for USB Mass Storage on SAM9X60, SAMA7G5 and SAMA5D2 boards and register ohci-at91 driver into Driver Model. In order for this to be achieved, the respective DT nodes have been added, the USB clock has been registered into CCF and the required defconfigs have been added to the boards' defconfig. What is more, in order for the VBUS to stay enabled, a `child_pre_probe` method has been added to overcome the DM core disabling it in `usb_scan_device`: when the generic `device_probe` method is called, the pinctrl is processed once again, undoing whatever changes have been made in our driver's probe method. In order to enable USB on SAMA7G5 the addition of RSTC and USB 2.0 PHY drivers were required. Cristian Birsan (2): ARM: at91: add sama7 SFR definitions usb: ohci-at91: Add `ohci_t` field in `ohci_at91_priv` Sergiu Moga (16): ARM: dts: sam9x60ek: Add OHCI and EHCI DT nodes clk: at91: Add support for sam9x60 USB clock clk: at91: sam9x60: Register the required clocks for USB clk: at91: sam9x60: Add initial setup of UPLL and USBCK rates usb: ohci-at91: Enable OHCI functionality and register into DM configs: at91: sam9x60ek: Add required configs for the USB command dt-bindings: reset: add sama7g5 definitions dt-bindings: clk: at91: Define additional UTMI related clocks ARM: dts: at91: sama7: Add USB related DT nodes reset: at91: Add reset driver for basic assert/deassert operations phy: at91: Add support for the USB 2.0 PHY's of SAMA7 usb: ohci-at91: Add USB PHY functionality configs: at91: sama7: Enable USB and RESET functionality ARM: dts: at91: sama5d2_icp: Add pinctrl nodes for USB related DT nodes ARM: dts: at91: sama5d27_wlsom1_ek: Add pinctrl nodes for USB DT nodes configs: at91: sama5d2: Enable OHCI/EHCI related configs arch/arm/dts/at91-sama5d27_wlsom1_ek.dts | 25 ++ arch/arm/dts/at91-sama5d2_icp.dts | 22 ++ arch/arm/dts/at91-sama7g5ek.dts | 34 +++ arch/arm/dts/sam9x60.dtsi | 18 ++ arch/arm/dts/sam9x60ek.dts | 21 ++ arch/arm/dts/sama7g5.dtsi | 73 ++++++ arch/arm/mach-at91/include/mach/sama7-sfr.h | 59 +++++ configs/sam9x60ek_mmc_defconfig | 10 + configs/sam9x60ek_nandflash_defconfig | 10 + configs/sam9x60ek_qspiflash_defconfig | 10 + configs/sama5d27_som1_ek_mmc1_defconfig | 5 + configs/sama5d27_som1_ek_mmc_defconfig | 5 + configs/sama5d27_som1_ek_qspiflash_defconfig | 5 + configs/sama5d27_wlsom1_ek_mmc_defconfig | 6 + .../sama5d27_wlsom1_ek_qspiflash_defconfig | 5 + configs/sama5d2_icp_mmc_defconfig | 9 + configs/sama5d2_icp_qspiflash_defconfig | 9 + configs/sama5d2_ptc_ek_mmc_defconfig | 5 + configs/sama5d2_ptc_ek_nandflash_defconfig | 5 + configs/sama5d2_xplained_emmc_defconfig | 5 + configs/sama5d2_xplained_mmc_defconfig | 5 + configs/sama5d2_xplained_qspiflash_defconfig | 5 + configs/sama5d2_xplained_spiflash_defconfig | 5 + configs/sama7g5ek_mmc1_defconfig | 13 ++ configs/sama7g5ek_mmc_defconfig | 13 ++ drivers/clk/at91/Kconfig | 7 + drivers/clk/at91/Makefile | 1 + drivers/clk/at91/clk-sam9x60-usb.c | 156 +++++++++++++ drivers/clk/at91/pmc.h | 11 + drivers/clk/at91/sam9x60.c | 99 +++++++- drivers/phy/Kconfig | 10 + drivers/phy/Makefile | 1 + drivers/phy/phy-sama7-usb.c | 92 ++++++++ drivers/phy/phy-sama7-utmi-clk.c | 202 +++++++++++++++++ drivers/reset/Kconfig | 8 + drivers/reset/Makefile | 1 + drivers/reset/reset-at91.c | 143 ++++++++++++ drivers/sysreset/sysreset_at91.c | 10 +- drivers/usb/host/ohci-at91.c | 214 ++++++++++++++++++ include/dt-bindings/clk/at91.h | 5 + include/dt-bindings/reset/sama7g5-reset.h | 10 + 41 files changed, 1342 insertions(+), 10 deletions(-) create mode 100644 arch/arm/mach-at91/include/mach/sama7-sfr.h create mode 100644 drivers/clk/at91/clk-sam9x60-usb.c create mode 100644 drivers/phy/phy-sama7-usb.c create mode 100644 drivers/phy/phy-sama7-utmi-clk.c create mode 100644 drivers/reset/reset-at91.c create mode 100644 include/dt-bindings/reset/sama7g5-reset.h -- 2.34.1

2 19

Gitlab CI: "build all 32bit ARM platforms" can't be completed due to timeout
by Patrice CHOTARD 07 Dec '22

07 Dec '22

Hi All Just to notice that 3 times in a raw, "build all 32bit ARM platforms" can't be completed due to 1 hour timeout, we got the following execution status : ERROR: Job failed: execution took longer than 1h0m0s seconds see : https://source.denx.de/u-boot/custodians/u-boot-stm/-/jobs/539133 https://source.denx.de/u-boot/custodians/u-boot-stm/-/jobs/539132 https://source.denx.de/u-boot/custodians/u-boot-stm/-/jobs/539078 Is it possible to extend this timeout to 1h30min ? Thanks Patrice

2 1

[PATCH] CI: Reduce aarch64 catchall job matches
by Tom Rini 07 Dec '22

07 Dec '22

The aarch64 catch-all job is getting close to the hard time limit in Azure for the free tier. Move i.MX9 boards to the i.MX8 job and move amlogic entirely to its own job. This brings us down from 85 boards to 51 boards and so should be safe for a while. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- .azure-pipelines.yml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index d31b183ba68f..d70798d33cac 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -447,6 +447,8 @@ stages: matrix: arc_microblaze_xtensa: BUILDMAN: "arc microblaze xtensa" + amlogic: + BUILDMAN: "amlogic" arm11_arm7_arm920t_arm946es: BUILDMAN: "arm11 arm7 arm920t arm946es" arm926ejs: @@ -477,8 +479,8 @@ stages: BUILDMAN: "mx6 -x boundary,engicam,freescale,technexion,toradex" imx: BUILDMAN: "mx -x mx6,freescale,technexion,toradex" - imx8: - BUILDMAN: "imx8" + imx8_imx9: + BUILDMAN: "imx8,imx9" keystone2_keystone3: BUILDMAN: "k2 k3" sandbox_asan: @@ -532,7 +534,7 @@ stages: uniphier: BUILDMAN: "uniphier" aarch64_catch_all: - BUILDMAN: "aarch64 -x bcm,imx8,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq" + BUILDMAN: "aarch64 -x amlogic,bcm,imx8,imx9,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq" rockchip: BUILDMAN: "rk" renesas: -- 2.25.1

1 0

[PATCH 1/6] buildman: Fetch 12.2.0 toolchains by default
by Tom Rini 07 Dec '22

07 Dec '22

Update the toolchain list to be first 12.2.0 and second 11.1.0 and that's it. Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- tools/buildman/toolchain.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index fea40ba2151a..38b0dea8c709 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -498,7 +498,7 @@ class Toolchains: if arch == 'aarch64': arch = 'arm64' base = 'https://www.kernel.org/pub/tools/crosstool/files/bin' - versions = ['11.1.0', '9.2.0', '7.3.0', '6.4.0', '4.9.4'] + versions = ['12.2.0', '11.1.0'] links = [] for version in versions: url = '%s/%s/%s/' % (base, arch, version) -- 2.25.1

3 16

[PATCH 1/1] powerpc: fix fdt_fixup_liodn_tbl_fman()
by Heinrich Schuchardt 07 Dec '22

07 Dec '22

Builiding with GCC 12.2 fails: arch/powerpc/cpu/mpc85xx/liodn.c: In function 'fdt_fixup_liodn_tbl_fman': arch/powerpc/cpu/mpc85xx/liodn.c:340:35: error: the comparison will always evaluate as 'false' for the address of 'compat' will never be NULL [-Werror=address] 340 | if (tbl[i].compat == NULL) | Remove the superfluous check. Fixes: 97a8d010e029 ("net/fman: Support both new and legacy FMan Compatibles") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- arch/powerpc/cpu/mpc85xx/liodn.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index a084002494..2d55916841 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -337,9 +337,6 @@ static void fdt_fixup_liodn_tbl_fman(void *blob, for (i = 0; i < sz; i++) { int off; - if (tbl[i].compat == NULL) - continue; - /* Try the new compatible first. * If the node is missing, try the old. */ -- 2.37.2

3 4

[PATCH v5 0/3] Add riscv semihosting support in u-boot
by Kautuk Consul 07 Dec '22

07 Dec '22

Semihosting is a mechanism that enables code running on a target to communicate and use the Input/Output facilities on a host computer that is running a debugger. This patchset adds support for semihosting in u-boot for RISCV64 targets. CHANGES since v4: - Check arch dependencies for SEMIHOSTING as well as SPL_SEMIHOSTING config options as per Sean's comment. - arch/riscv/lib/interrupts.c: Check for post and pre instructions of the ebreak statement whether they are as per the RISCV semihosting specification. Only then do a disable_semihosting and epc += 4 and return. Compilation and test commands for SPL and S-mode configurations ================================================================= U-Boot S-mode on QEMU virt ---------------------------- // Compilation of S-mode u-boot ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_smode_defconfig make // Run riscv 64-bit u-boot with opensbi on qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\ u-boot/u-boot.bin U-Boot SPL on QEMU virt ------------------------ // Compilation of u-boot-spl ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_spl_defconfig make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin // Run 64-bit u-boot-spl in qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ u-boot/spl/u-boot-spl.bin -device\ loader,file=u-boot/u-boot.itb,addr=0x80200000 Kautuk Consul (3): lib: Add common semihosting library arch/riscv: add semihosting support for RISC-V board: qemu-riscv: enable semihosting arch/arm/Kconfig | 46 ------- arch/arm/lib/semihosting.c | 181 +------------------------- arch/riscv/include/asm/spl.h | 1 + arch/riscv/lib/Makefile | 2 + arch/riscv/lib/interrupts.c | 25 ++++ arch/riscv/lib/semihosting.c | 24 ++++ configs/qemu-riscv32_defconfig | 4 + configs/qemu-riscv32_smode_defconfig | 4 + configs/qemu-riscv32_spl_defconfig | 7 + configs/qemu-riscv64_defconfig | 4 + configs/qemu-riscv64_smode_defconfig | 4 + configs/qemu-riscv64_spl_defconfig | 7 + include/semihosting.h | 11 ++ lib/Kconfig | 47 +++++++ lib/Makefile | 2 + lib/semihosting.c | 186 +++++++++++++++++++++++++++ 16 files changed, 329 insertions(+), 226 deletions(-) create mode 100644 arch/riscv/lib/semihosting.c create mode 100644 lib/semihosting.c -- 2.34.1

4 26

[PATCH v6 0/3] Add riscv semihosting support in u-boot
by Kautuk Consul 07 Dec '22

07 Dec '22

Semihosting is a mechanism that enables code running on a target to communicate and use the Input/Output facilities on a host computer that is running a debugger. This patchset adds support for semihosting in u-boot for RISCV64 targets. CHANGES since v5: - Removed patch 3/3: default enablement of semihosting removed for the qemu-riscv64 targets due to failure of the CI test-cases. This is happening due to the qemu version and some commits currently not taken into qemu latest version. - Added patch 3/3: Added a 3rd patch which adds a dependency on SPL_SEMIHOSTING for the SPL_FS_LOAD_PAYLOAD_NAME config option. This will remove the need for the user to enable any of the SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS config options for SPL_SEMIHOSTING compilations. Compilation and test commands for SPL and S-mode configurations ================================================================= U-Boot S-mode on QEMU virt ---------------------------- // Compilation of S-mode u-boot ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_smode_defconfig make // Run riscv 64-bit u-boot with opensbi on qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\ u-boot/u-boot.bin -semihosting-config enable=on U-Boot SPL on QEMU virt ------------------------ // Compilation of u-boot-spl ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_spl_defconfig make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin // Run 64-bit u-boot-spl in qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ u-boot/spl/u-boot-spl.bin -device\ loader,file=u-boot/u-boot.itb,addr=0x80200000 -semihosting-config enable=on Kautuk Consul (3): lib: Add common semihosting library arch/riscv: add semihosting support for RISC-V common/spl/Kconfig: add dependency on SPL_SEMIHOSTING for SPL payload arch/arm/Kconfig | 46 --------- arch/arm/lib/semihosting.c | 181 +--------------------------------- arch/riscv/include/asm/spl.h | 1 + arch/riscv/lib/Makefile | 2 + arch/riscv/lib/interrupts.c | 25 +++++ arch/riscv/lib/semihosting.c | 24 +++++ common/spl/Kconfig | 2 +- include/semihosting.h | 11 +++ lib/Kconfig | 47 +++++++++ lib/Makefile | 2 + lib/semihosting.c | 186 +++++++++++++++++++++++++++++++++++ 11 files changed, 300 insertions(+), 227 deletions(-) create mode 100644 arch/riscv/lib/semihosting.c create mode 100644 lib/semihosting.c -- 2.34.1

1 3

[PATCH v3 0/5] miscellaneous fixes of eficonfig
by Masahisa Kojima 07 Dec '22

07 Dec '22

This series includes bugfix, refactoring and documentation updates. Masahisa Kojima (5): eficonfig: fix going one directory up issue eficonfig: use u16_strsize() to get u16 string buffer size efi_loader: utility function to check the variable name is "Boot####" eficonfig: use efi_get_next_variable_name_int() doc:eficonfig: add description for UEFI Secure Boot Configuration cmd/eficonfig.c | 146 +++++++++++++++++++++++++++++------- cmd/efidebug.c | 23 +----- doc/usage/cmd/eficonfig.rst | 22 ++++++ include/efi_loader.h | 1 + lib/efi_loader/efi_helper.c | 33 ++++++++ 5 files changed, 176 insertions(+), 49 deletions(-) -- 2.17.1

3 12

[PATCH 1/1] mvebu: fix end-of-array check
by Derek LaHousse 07 Dec '22

07 Dec '22

Properly seek the end of default_environment variables. The current algorithm overwrites from the second variable. This replacement finds the end of the array of strings. Stomped variables include "board", "soc", "loadaddr". These can be seen on a "env default -a" after patch, but they are not seen with a version before the patch. Signed-off-by: Derek LaHousse <derek(a)seaofdirac.org> --- board/Marvell/mvebu_armada-37xx/board.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index c6ecc323bb..ac29ac5b95 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -100,8 +100,11 @@ int board_late_init(void) return 0; /* Find free buffer in default_environment[] for new variables */ - while (*ptr != '\0' && *(ptr+1) != '\0') ptr++; - ptr += 2; + if (*ptr != '\0') { // Defending against empty default env + while ((i = strlen(ptr)) != 0) { + ptr += i + 1; + } + } /* * Ensure that 'env default -a' does not erase permanent MAC addresses -- 2.30.2

5 10

[PATCH] ARM: dts: aspeed: add Meta greatlakes board (AST2600)
by Delphine CC Chiu 07 Dec '22

07 Dec '22

Add initial version of device tree for Meta Greatlakes BMC which is equipped with Aspeed AST2600 BMC SoC. Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu(a)Wiwynn.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/ast2600-greatlakes.dts | 191 ++++++++++++++++++++++++++ configs/ast2600_openbmc_spl_defconfig | 1 + 3 files changed, 193 insertions(+) create mode 100644 arch/arm/dts/ast2600-greatlakes.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6c34b83336..c9cb54cddd 100755 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -686,6 +686,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ ast2600-evb.dtb \ ast2600-dcscm.dtb \ ast2600-fpga.dtb \ + ast2600-greatlakes.dtb \ ast2600-intel.dtb \ ast2600-ncsi.dtb \ ast2600-p10bmc.dtb \ diff --git a/arch/arm/dts/ast2600-greatlakes.dts b/arch/arm/dts/ast2600-greatlakes.dts new file mode 100644 index 0000000000..94caf295da --- /dev/null +++ b/arch/arm/dts/ast2600-greatlakes.dts @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2022 Meta Platforms Inc. +/dts-v1/; + +#include "ast2600-u-boot.dtsi" + +/ { + model = "Facebook Greatlakes BMC"; + compatible = "facebook,greatlakes-bmc", "aspeed,ast2600"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + stdout-path = &uart5; + }; + + aliases { + spi0 = &fmc; + ethernet3 = &mac3; + }; + + cpus { + cpu@0 { + clock-frequency = <800000000>; + }; + cpu@1 { + clock-frequency = <800000000>; + }; + }; +}; + +&uart5 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&sdrammc { + clock-frequency = <400000000>; +}; + +&wdt1 { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&wdt3 { + status = "okay"; +}; + +&mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio4_default>; + #address-cells = <1>; + #size-cells = <0>; + ethphy3: ethernet-phy@3 { + reg = <0>; + }; +}; + +&mac3 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&ethphy3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; +}; + +&fmc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fmcquad_default>; +}; + +&gpio0 { + status = "okay"; + line_148 { + gpio-hog; + gpios = <148 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc-slot1-isolated-enabled"; + }; + line_149 { + gpio-hog; + gpios = <149 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc-slot2-isolated-enabled"; + }; + line_150 { + gpio-hog; + gpios = <150 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc-slot3-isolated-enabled"; + }; + line_151 { + gpio-hog; + gpios = <151 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc-slot4-isolated-enabled"; + }; +}; + +&i2c0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; +}; + +&i2c1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_default>; +}; + +&i2c2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; +}; + +&i2c3 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; +}; + +&i2c4 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; +}; + +&i2c5 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; +}; + +&i2c6 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; +}; + +&i2c7 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; +}; + +&i2c8 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; +}; + +&scu { + mac0-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; + mac1-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; + mac2-clk-delay = <0x08 0x04 + 0x08 0x04 + 0x08 0x04>; + mac3-clk-delay = <0x08 0x04 + 0x08 0x04 + 0x08 0x04>; +}; + +&hace { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/configs/ast2600_openbmc_spl_defconfig b/configs/ast2600_openbmc_spl_defconfig index 95d7651b8e..efd683570f 100644 --- a/configs/ast2600_openbmc_spl_defconfig +++ b/configs/ast2600_openbmc_spl_defconfig @@ -100,6 +100,7 @@ CONFIG_ASPEED_ACRY=y CONFIG_DM_GPIO=y CONFIG_SPL_GPIO_HOG=y CONFIG_ASPEED_GPIO=y +CONFIG_GPIO_HOG=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_ASPEED=y CONFIG_MISC=y -- 2.17.1

1 0