November 2022 - U-Boot

[PATCH v2 0/5] Add ARMv8 CE sha1/sha256 support
by Loic Poulain 08 Feb '23

08 Feb '23

This series adds support for the SHA-1 and SHA-256 Secure Hash Algorithm for CPUs that have support of the ARM v8 Crypto Extensions. It Improves speed of integrity & signature checking procedures. V2: - Add cover letter & sha256 support. - Kconfig default 'y' only if SHA1 and SHA256 selected Loic Poulain (5): lib: sha1: Add support for hardware specific sha1_process sha1: Fix digest state size/type armv8 SHA-1 using ARMv8 Crypto Extensions: lib: sha256: Add support for hardware specific sha256_process armv8 SHA-256 using ARMv8 Crypto Extensions arch/arm/cpu/armv8/Kconfig | 15 ++++ arch/arm/cpu/armv8/Makefile | 2 + arch/arm/cpu/armv8/sha1_ce_core.S | 132 +++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/sha1_ce_glue.c | 21 ++++++ arch/arm/cpu/armv8/sha256_ce_core.S | 134 ++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/sha256_ce_glue.c | 21 ++++++ include/u-boot/sha1.h | 2 +- lib/sha1.c | 26 +++++-- lib/sha256.c | 26 +++++-- 9 files changed, 364 insertions(+), 15 deletions(-) create mode 100644 arch/arm/cpu/armv8/sha1_ce_core.S create mode 100644 arch/arm/cpu/armv8/sha1_ce_glue.c create mode 100644 arch/arm/cpu/armv8/sha256_ce_core.S create mode 100644 arch/arm/cpu/armv8/sha256_ce_glue.c -- 2.7.4

3 22

[PATCH v9 0/8] Add MV88E6xxx DSA driver and use on gwventana
by Tim Harvey 03 Feb '23

03 Feb '23

This series adds a DSA driver for the MV88E6xxx based on drivers/net/phy/mv88e61xx and uses it in the gwventana_gw5904_defconfig. The hope is that the other three boards that use the MV88E61xx driver can move to this as well eventually so that we can remove the non-dm driver and the 4 Kconfig options it requires. The MV88E6xxx has an MDIO interface thus DM_MDIO must be used so support for a UCLASS_MDIO driver is added to the fec_mxc ethernet driver in a way that allows a fallback to the previous non DM_MDIO case as there are many boards out there using this driver that define DM_MDIO but do not have the required dt props for a DM_MDIO driver which would cause a regression. Additionally some other patches are here suggested by Vladimir: - ensure MDIO children are scanned on post-bind is needed - sanity check DSA driver required ops are present - allow DSA drivers to not require xmit/recv functions - remove unecessary xmit/recv functions from ksz9477 driver v9: - fix regression in dsa xmit() logic for patch 4: net: dsa: allow rcv() and xmit() to be optional v8: - en remove energy-detect low-power mode config - add phy-mode internal dt prop to phy ports v7: - rebase on master - update commit short msg (s/MV88E61xx/MV88E6xxx) - replace inline smi_cmd* with macros using logical operators - replace bitfield_replace with logical operators for readibility - removed some unused register definitions - config switch based SERDES mode once in probe vs port_enable - rework port_enable to clean up and: - enable energy-detect for all non fixed PHY ports - configure RGMII delays based on interface type - add Vladimir's rb tag to patch 8 v6: - update commit messages - squash accidently change to mv88e6xxx driver into previous patch - remove unused dt label for cpu port - removed unnecessary semicolon - update commit msg (s/MV88E61xx/MV88E6xxx) - remove GbE from commit msg and Kconfig desc - squash accidental change from patch 7 into patch 6 - added error print on failure to read switch id - mv88e6xxx_probe: - check for switch enabled - remove unused variable enabled - remove unnecessary call to dsa_set_tagging - port_probe: - new function to configure phy features by calling phy_config - port_enable: - only enable energy-detect sensing on phy ports - add phy/cmode verification mistmatch warning - remove mv88e6xxx_fixed_port_setup() - always force link up for fixed ports - always set SERDES mode regardless of cpu port - remove unnecessary setting of CPUDEST - port_disable: - remove pointless error check - removed unnecessary priv data for mdio controller - fix indentation - change variable name for clarity v5: - fix typo in defconfig update - added support for MV88E6320 - added Fabio's rb tag v4: - use standard Linux internal MDIO dt structure - use PHY_FIXED_ID define - rename to mv88e6xxx - sort includes alphabetically - remove dsa term from function names - reduce indentation level and remove unecessary code in of probe_mdio function - rename pdev to mdev to represent mdio device v3: - fix mdios node in dt - add Vladimir's rb tag's v2: - added Ramon's rb tag's to first two patches - add patches for dsa-uclass to sanity check ops and make xmit/recv optional - fec: fix fallback for non conforming DM_MDIO dts - mv88e61xx: - rebase on v2022.07-rc2 (use ofnode_get_phy_node) - remove unused commented out fields from struct - remove unused PORT_MASK macro - remove phy from priv struct name - refactor code from original drivers/net/phy/mv88e61xx with suggestions from review to consolidate some functions into mv88e61xx_dsa_port_enable - remove unecessary skiping of disabling of CPU port - remove unecessary dev_set_parent_priv - remove unnecessary static init flag - replace debug with a dev_warn if switch device-id unsupported - remove unnecessary xmit/recv functions as we rely on the fact that only a single port is active instead of mangling packets Tested on a Gateworks GW5904 which has a Marvell 88E6176 switch hanging off the IMX6 FEC. Best Regards, Tim Tim Harvey (8): net: mdio-uclass: scan for dm mdio children on post-bind net: dsa: move cpu port probe to dsa_post_probe net: dsa: ensure dsa driver has proper ops net: dsa: allow rcv() and xmit() to be optional net: ksz9477: remove unnecessary xmit and recv functions net: fec: add support for DM_MDIO net: add MV88E6xxx DSA driver board: gw_ventana: enable MV88E61XX DSA support arch/arm/dts/imx6qdl-gw5904.dtsi | 36 +- board/gateworks/gw_ventana/gw_ventana.c | 50 +- configs/gwventana_gw5904_defconfig | 7 +- drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/fec_mxc.c | 90 ++- drivers/net/ksz9477.c | 23 - drivers/net/mv88e6xxx.c | 755 ++++++++++++++++++++++++ net/dsa-uclass.c | 56 +- net/mdio-uclass.c | 4 + 10 files changed, 953 insertions(+), 76 deletions(-) create mode 100644 drivers/net/mv88e6xxx.c -- 2.25.1

3 14

[PATCH v2 1/2] udoo_neo: Move to DM for REGULATOR/PMIC/I2C drivers
by Peter Robinson 03 Feb '23

03 Feb '23

This moves over the PMIC power init to DM and the associated i2c and regulator bits. Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> --- Changes in v2: - Fix spelling mistake - Drop unneeded DM_MMC - Drop dangling comment in udoo_neo.h board/udoo/neo/neo.c | 139 +++---------------------------------- configs/udoo_neo_defconfig | 9 ++- include/configs/udoo_neo.h | 7 -- 3 files changed, 14 insertions(+), 141 deletions(-) diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c index 5e40583ab43..9e2a66996c4 100644 --- a/board/udoo/neo/neo.c +++ b/board/udoo/neo/neo.c @@ -51,11 +51,6 @@ enum { PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) @@ -83,135 +78,25 @@ int dram_init(void) return 0; } -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, - .gp = IMX_GPIO_NR(1, 0), - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, - .gp = IMX_GPIO_NR(1, 1), - }, -}; -#endif - -#if CONFIG_IS_ENABLED(POWER_LEGACY) int power_init_board(void) { - struct pmic *p; - int ret; - unsigned int reg, rev_id; - - ret = power_pfuze3000_init(PFUZE3000_I2C_BUS); - if (ret) - return ret; - - p = pmic_get("PFUZE3000"); - ret = pmic_probe(p); - if (ret) - return ret; + struct udevice *dev; + int ret, dev_id, rev_id; - pmic_reg_read(p, PFUZE3000_DEVICEID, &reg); - pmic_reg_read(p, PFUZE3000_REVID, &rev_id); - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); - - /* disable Low Power Mode during standby mode */ - pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg); - reg |= 0x1; - ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); - if (ret) + ret = pmic_get("pfuze3000@8", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) return ret; - ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc); - if (ret) - return ret; + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc); - if (ret) - return ret; - - ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc); - if (ret) - return ret; - - ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc); - if (ret) - return ret; - - /* set SW1A standby voltage 0.975V */ - pmic_reg_read(p, PFUZE3000_SW1ASTBY, &reg); - reg &= ~0x3f; - reg |= PFUZE3000_SW1AB_SETP(9750); - ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); - if (ret) - return ret; - - /* set SW1B standby voltage 0.975V */ - pmic_reg_read(p, PFUZE3000_SW1BSTBY, &reg); - reg &= ~0x3f; - reg |= PFUZE3000_SW1AB_SETP(9750); - ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); - if (ret) - return ret; - - /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE3000_SW1ACONF, &reg); - reg &= ~0xc0; - reg |= 0x40; - ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg); - if (ret) - return ret; - - /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE3000_SW1BCONF, &reg); - reg &= ~0xc0; - reg |= 0x40; - ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg); - if (ret) - return ret; - - /* set VDD_ARM_IN to 1.350V */ - pmic_reg_read(p, PFUZE3000_SW1AVOLT, &reg); - reg &= ~0x3f; - reg |= PFUZE3000_SW1AB_SETP(13500); - ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg); - if (ret) - return ret; - - /* set VDD_SOC_IN to 1.350V */ - pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg); - reg &= ~0x3f; - reg |= PFUZE3000_SW1AB_SETP(13500); - ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); - if (ret) - return ret; - - /* set DDR_1_5V to 1.350V */ - pmic_reg_read(p, PFUZE3000_SW3VOLT, &reg); - reg &= ~0x0f; - reg |= PFUZE3000_SW3_SETP(13500); - ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg); - if (ret) - return ret; - - /* set VGEN2_1V5 to 1.5V */ - pmic_reg_read(p, PFUZE3000_VLDO2CTL, &reg); - reg &= ~0x0f; - reg |= PFUZE3000_VLDO_SETP(15000); - /* enable */ - reg |= 0x10; - ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg); - if (ret) - return ret; + pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); return 0; } -#endif static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -294,10 +179,6 @@ int board_init(void) gpio_request(IMX_GPIO_NR(4, 16), "ncp692"); gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); -#endif - setup_fec(); return 0; diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 8ae9fa57f03..341ee4671db 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_MX6SX=y CONFIG_TARGET_UDOO_NEO=y -CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_DM_I2C=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6sx-udoo-neo-basic" CONFIG_SPL_TEXT_BASE=0x00908000 @@ -43,8 +43,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y @@ -55,11 +53,12 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y -CONFIG_POWER_LEGACY=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_ANATOP=y -CONFIG_POWER_I2C=y +CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index e30b6cc82d8..70d78031523 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -55,17 +55,10 @@ #include <config_distro_bootcmd.h> -/* Miscellaneous configurable options */ - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* PMIC */ -#define CONFIG_POWER_PFUZE3000 -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 -#define PFUZE3000_I2C_BUS 0 - #endif /* __CONFIG_H */ -- 2.38.1

3 5

[PATCH] imx8m: Select BINMAN via SoC level
by Fabio Estevam 03 Feb '23

03 Feb '23

From: Fabio Estevam <festevam(a)denx.de> Since all imx8m boards have been converted to use binman, select binman via SoC level rather than making the selection for each board. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- arch/arm/mach-imx/imx8m/Kconfig | 33 +-------------------------------- 1 file changed, 1 insertion(+), 32 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 8cd7c7a8dd8b..c7a272ec18f5 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -2,6 +2,7 @@ if ARCH_IMX8M config IMX8M bool + select BINMAN select HAS_CAAM select ROM_UNIFIED_SECTIONS @@ -31,13 +32,11 @@ choice config TARGET_IMX8MQ_CM bool "Ronetix iMX8MQ-CM SoM" - select BINMAN select IMX8MQ select IMX8M_LPDDR4 config TARGET_IMX8MQ_EVK bool "imx8mq_evk" - select BINMAN select IMX8MQ select IMX8M_LPDDR4 select FSL_CAAM @@ -46,20 +45,17 @@ config TARGET_IMX8MQ_EVK config TARGET_IMX8MQ_PHANBELL bool "imx8mq_phanbell" - select BINMAN select IMX8MQ select IMX8M_LPDDR4 config TARGET_IMX8MM_DATA_MODUL_EDM_SBC bool "Data Modul eDM SBC i.MX8M Mini" - select BINMAN select IMX8MM select IMX8M_LPDDR4 select SUPPORT_SPL config TARGET_IMX8MM_EVK bool "imx8mm LPDDR4 EVK board" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 @@ -69,7 +65,6 @@ config TARGET_IMX8MM_EVK config TARGET_IMX8MM_ICORE_MX8MM bool "Engicam i.Core MX8M Mini SOM" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 @@ -88,14 +83,12 @@ config TARGET_IMX8MM_ICORE_MX8MM config TARGET_IMX8MM_MX8MENLO bool "Support i.MX8M Mini MX8Menlo board based on Toradex Verdin SoM" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_IMX8MM_VENICE bool "Support Gateworks Venice iMX8M Mini module" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 @@ -104,7 +97,6 @@ config TARGET_IMX8MM_VENICE config TARGET_KONTRON_MX8MM bool "Kontron Electronics N80xx" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 @@ -114,21 +106,18 @@ config TARGET_KONTRON_MX8MM config TARGET_IMX8MN_BSH_SMM_S2 bool "imx8mn-bsh-smm-s2" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_DDR3L config TARGET_IMX8MN_BSH_SMM_S2PRO bool "imx8mn-bsh-smm-s2pro" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_DDR3L config TARGET_IMX8MN_EVK bool "imx8mn LPDDR4 EVK board" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 @@ -137,7 +126,6 @@ config TARGET_IMX8MN_EVK config TARGET_IMX8MN_DDR4_EVK bool "imx8mn DDR4 EVK board" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_DDR4 @@ -146,7 +134,6 @@ config TARGET_IMX8MN_DDR4_EVK config TARGET_IMX8MN_VENICE bool "Support Gateworks Venice iMX8M Nano module" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 @@ -155,14 +142,12 @@ config TARGET_IMX8MN_VENICE config TARGET_IMX8MP_DH_DHCOM_PDK2 bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus" - select BINMAN select IMX8MP select IMX8M_LPDDR4 select SUPPORT_SPL config TARGET_IMX8MP_ICORE_MX8MP bool "Engicam i.Core MX8M Plus SOM" - select BINMAN select IMX8MP select IMX8M_LPDDR4 select SUPPORT_SPL @@ -176,7 +161,6 @@ config TARGET_IMX8MP_ICORE_MX8MP config TARGET_IMX8MP_EVK bool "imx8mp LPDDR4 EVK board" - select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 @@ -186,7 +170,6 @@ config TARGET_IMX8MP_EVK config TARGET_IMX8MP_VENICE bool "Support Gateworks Venice iMX8M Plus module" - select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 @@ -195,68 +178,58 @@ config TARGET_IMX8MP_VENICE config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" - select BINMAN select IMX8MQ select IMX8M_LPDDR4 config TARGET_IMX8MN_VAR_SOM bool "imx8mn_var_som" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_DDR4 config TARGET_KONTRON_PITX_IMX8M bool "Support Kontron pITX-imx8m" - select BINMAN select IMX8MQ select IMX8M_LPDDR4 config TARGET_VERDIN_IMX8MM bool "Support Toradex Verdin iMX8M Mini module" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_VERDIN_IMX8MP bool "Support Toradex Verdin iMX8M Plus module" - select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_IMX8MM_BEACON bool "imx8mm Beacon Embedded devkit" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_IMX8MN_BEACON bool "imx8mn Beacon Embedded devkit" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_PHYCORE_IMX8MM bool "PHYTEC PHYCORE i.MX8MM" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_PHYCORE_IMX8MP bool "PHYTEC PHYCORE i.MX8MP" - select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_IMX8MM_CL_IOT_GATE bool "CompuLab iot-gate-imx8" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 @@ -264,7 +237,6 @@ config TARGET_IMX8MM_CL_IOT_GATE config TARGET_IMX8MM_CL_IOT_GATE_OPTEE bool "CompuLab iot-gate-imx8 with optee support" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 @@ -272,21 +244,18 @@ config TARGET_IMX8MM_CL_IOT_GATE_OPTEE config TARGET_IMX8MP_RSB3720A1_4G bool "Support i.MX8MP RSB3720A1 4G" - select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_IMX8MP_RSB3720A1_6G bool "Support i.MX8MP RSB3720A1 6G" - select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_LIBREM5 bool "Purism Librem5 Phone" - select BINMAN select IMX8MQ select SUPPORT_SPL select IMX8M_LPDDR4 -- 2.25.1

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[PATCH] RFC: nvedit: support doing one (extra) expansion of the value in "env set"
by Rasmus Villemoes 02 Feb '23

02 Feb '23

Currently, there's no way to fetch the value of an environment variable whose name is stored in some other variable, or generated from such - in non-working pseudo-code, ${${varname}} ${array${index}} This forces some scripts to needlessly duplicate logic and hardcode assumptions. For example, in an A/B scheme with three variables BOOT_ORDER # Either "A B" or "B A" depending on which slot was last updated BOOT_A_LEFT # 0..3 BOOT_B_LEFT # 0..3 when one needs to determine the slot to boot from, one does something like setenv found for slot in $BOOT_ORDER ; do if test "x$found" != "x" ; then # work around lack of break elif test "x$slot" = "xA" ; then if test $BOOT_A_LEFT -gt 0 ; then setexpr BOOT_A_LEFT $BOOT_A_LEFT - 1 setenv found A setenv bootargs ${bootargs_A} setenv ubivol ${ubivol_A} # more setup based on A fi elif test "x$slot" = "xB" ; then if test $BOOT_B_LEFT -gt 0 ; then # the same ... fi fi done This is already bad enough, but extending that to A/B/C is tedious and prone to copy-pastos. So this is an attempt at allowing one to do "env set -E var value1 value2" with the effect that, of course, normal variable expansion happens on the command line, the valueX are joined with spaces as usual, and then one more pass is done over that string replacing occurrences of ${foo}. The above would become setenv found for slot in $BOOT_ORDER ; do if test "x$found" != "x" ; then # work around lack of break else env set -E boot_left "\${BOOT_${slot}_LEFT}" if test $boot_left -gt 0 ; then setexpr BOOT_${slot}_LEFT $boot_left - 1 env set found $slot env set -E bootargs "\${bootargs_${slot}}" env set -E ubivol "\${ubivol_${slot}}" fi fi done I'm pleasantly surprised it was that easy to implement, but of course I'm cheating a bit (cli_simple_process_macros is only available if CONFIG_CMDLINE, though I think cli_simple.o could be unconditionally built and then link-time GC should get rid of the excess functions). This has been lightly tested in the sandbox. I'll add some proper unit tests, update the help texts and try to handle the Kconfig issue if this is something that might be accepted. Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- cmd/nvedit.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 81d94cd193..ff6ffcb674 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -224,7 +224,7 @@ DONE: */ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) { - int i, len; + int i, len, expand = 0; char *name, *value, *s; struct env_entry e, *ep; @@ -244,6 +244,9 @@ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) case 'f': /* force */ env_flag |= H_FORCE; break; + case 'E': + expand = 1; + break; default: return CMD_RET_USAGE; } @@ -287,6 +290,18 @@ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) if (s != value) *--s = '\0'; + if (expand) { + char *expanded = malloc(CONFIG_SYS_CBSIZE); + + if (expanded == NULL) { + printf("## Can't malloc %d bytes\n", CONFIG_SYS_CBSIZE); + free(value); + return 1; + } + cli_simple_process_macros(value, expanded); + free(value); + value = expanded; + } e.key = name; e.data = value; hsearch_r(e, ENV_ENTER, &ep, &env_htab, env_flag); -- 2.23.0

5 20

[PATCH 1/2] imx: imx8mm-beacon: Enable FlexSPI in U-Boot
by Adam Ford 01 Feb '23

01 Feb '23

In order to use the FlexSPI interface in U-Boot, configure the alias to make spi0 point to flexspi. With that enabled, sf probe detects the QSPI part as: SF: Detected n25q256ax1 with page size 256 Bytes, erase size 4 KiB, total 32 MiB Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi index 00ac413f36..4f5b9cd23c 100644 --- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi @@ -6,6 +6,10 @@ #include "imx8mm-u-boot.dtsi" / { + aliases { + spi0 = &flexspi; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; -- 2.34.1

2 4

[PATCH 00/11] imx: convert to DM_SERIAL
by Peng Fan (OSS) 01 Feb '23

01 Feb '23

From: Peng Fan <peng.fan(a)nxp.com> This patchset is to convert mx6ull/z_evk, mx6sl[l]evk, mx6sxsbareauto, mx6sabreauto, mx6sabresd to DM_SERIAL Patch 1 is a fix found when testing mx6sllevk Peng Fan (11): imx: implement get_effective_memsize imx: mx6ull_14x14_evk: select DM_SERIAL imx: mx6ulz: select DM_SERIAL imx: mx6ull/z_14x14_evk: clean up UART iomux imx: mx6sllevk: correct pmic name imx: mx6sllevk: select DM_SERIAL imx: mx6slevk: select DM_SERIAL imx: mx6ul_evk: select DM_SERIAL imx: mx6sxsabreauto: select DM_SERIAL imx: mx6sabreauto_defconfig: select DM_SERIAL imx: mx6sabresd: select DM_SERIAL arch/arm/dts/imx6sll-evk-u-boot.dtsi | 8 ++++++++ arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi | 4 ++++ arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi | 8 ++++++++ arch/arm/dts/imx6ulz-14x14-evk-u-boot.dtsi | 8 ++++++++ arch/arm/mach-imx/cache.c | 14 ++++++++++++++ board/freescale/mx6sllevk/mx6sllevk.c | 18 +----------------- .../freescale/mx6sxsabreauto/mx6sxsabreauto.c | 16 ---------------- board/freescale/mx6ullevk/mx6ullevk.c | 16 ---------------- configs/mx6sabreauto_defconfig | 1 + configs/mx6sabresd_defconfig | 1 + configs/mx6slevk_defconfig | 1 + configs/mx6slevk_spinor_defconfig | 1 + configs/mx6slevk_spl_defconfig | 1 + configs/mx6sllevk_defconfig | 1 + configs/mx6sllevk_plugin_defconfig | 1 + configs/mx6sxsabreauto_defconfig | 1 + configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + configs/mx6ull_14x14_evk_defconfig | 1 + configs/mx6ull_14x14_evk_plugin_defconfig | 1 + configs/mx6ulz_14x14_evk_defconfig | 1 + 21 files changed, 56 insertions(+), 49 deletions(-) create mode 100644 arch/arm/dts/imx6sll-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ulz-14x14-evk-u-boot.dtsi -- 2.36.0

9 42

[PATCH 0/2] board: gateworks: venice: poll I2C to wait for GSC
by Tim Harvey 31 Jan '23

31 Jan '23

The first patch brings the dts up to date with upstream Linux commits. The second patch implements polling the I2C lines to wait for the Gateworks System Controller to be ready before reading the board EEPROM. Tim Harvey (2): arm: dts: imx8m*-venice-*: add I2C GPIO bus recovery support board: gateworks: venice: poll I2C lines to wait for GSC firmware arch/arm/dts/imx8mm-venice-gw700x.dtsi | 24 +++++++++++-- arch/arm/dts/imx8mm-venice-gw7901.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mm-venice-gw7902.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mm-venice-gw7903.dts | 36 +++++++++++++++++-- arch/arm/dts/imx8mm-venice-gw7904.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mm-venice-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-venice.dts | 12 ++++++- arch/arm/dts/imx8mn-venice-gw7902.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mn-venice-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mn-venice.dts | 12 ++++++- arch/arm/dts/imx8mp-venice-gw74xx.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mp-venice-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mp-venice.dts | 12 ++++++- board/gateworks/venice/spl.c | 39 +++++++++++++-------- 14 files changed, 345 insertions(+), 42 deletions(-) -- 2.25.1

3 8

[PATCH] configs: imx8m: Prepare imx8m-beacon boards for HAB support
by Adam Ford 31 Jan '23

31 Jan '23

In order to enable HAB, FSL_CAAM, ARCH_MISC_INIT and SPL_CRYPTO should be enabled in Kconfig like other i.MX8M boards. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index a0715e8091..eadb2234b0 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -233,6 +233,9 @@ config TARGET_IMX8MM_BEACON select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_IMX8MN_BEACON bool "imx8mn Beacon Embedded devkit" @@ -240,6 +243,9 @@ config TARGET_IMX8MN_BEACON select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_PHYCORE_IMX8MM bool "PHYTEC PHYCORE i.MX8MM" -- 2.34.1

2 1

[PATCH] arm64: dts: imx8m{m, n}-venice-gw7902: add gpio pins for new board revision
by Tim Harvey 31 Jan '23

31 Jan '23

Add gpio pins present on new board revision: * LTE modem support (imx8mm-gw7902 only) - lte_pwr# - lte_rst - lte_int * M2 power enable - m2_pwr_en * off-board 4.0V supply - vdd_4p0_en Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi | 14 ++++++++++++++ arch/arm/dts/imx8mm-venice-gw7902.dts | 12 ++++++++---- arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi | 14 ++++++++++++++ arch/arm/dts/imx8mn-venice-gw7902.dts | 8 ++++---- 4 files changed, 40 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi index f21e46b12dd7..d58a7d14b631 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi @@ -6,6 +6,13 @@ #include "imx8mm-venice-u-boot.dtsi" &gpio1 { + m2pwren { + gpio-hog; + output-low; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "m2_pwren"; + }; + m2rst { gpio-hog; output-low; @@ -96,6 +103,13 @@ line-name = "app_gpio1"; }; + vdd4p0en { + gpio-hog; + output-low; + gpios = <22 GPIO_ACTIVE_HIGH>; + line-name = "vdd_4p0_en"; + }; + uart1rs485 { gpio-hog; output-low; diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts index 31f4c735fe4f..921bffae0cc9 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902.dts +++ b/arch/arm/dts/imx8mm-venice-gw7902.dts @@ -261,7 +261,7 @@ &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -283,7 +283,8 @@ &gpio4 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", - "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485", + "lte_pwr#", "lte_rst", "lte_int", "", + "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485", "", "uart1_term", "uart1_half", "app_gpio2", "mipi_gpio1", "", "", ""; }; @@ -738,14 +739,19 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */ + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ @@ -779,8 +785,6 @@ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 - MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 >; }; diff --git a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi index 17e6828c79f8..10656ce903a5 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi @@ -6,6 +6,13 @@ #include "imx8mn-venice-u-boot.dtsi" &gpio1 { + m2pwren { + gpio-hog; + output-low; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "m2_pwren"; + }; + m2rst { gpio-hog; output-low; @@ -54,6 +61,13 @@ line-name = "app_gpio1"; }; + vdd4p0en { + gpio-hog; + output-low; + gpios = <22 GPIO_ACTIVE_HIGH>; + line-name = "vdd_4p0_en"; + }; + uart1rs485 { gpio-hog; output-low; diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts index dd4302ac1de4..029ccdbee7d5 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902.dts +++ b/arch/arm/dts/imx8mn-venice-gw7902.dts @@ -256,7 +256,7 @@ &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -278,7 +278,7 @@ &gpio4 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "app_gpio1", "", "uart1_rs485", + "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485", "", "uart1_term", "uart1_half", "app_gpio2", "mipi_gpio1", "", "", ""; }; @@ -689,10 +689,12 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ @@ -726,8 +728,6 @@ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 - MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 >; }; -- 2.25.1

2 1