October 2022 - U-Boot

[PATCH] tests: Build correct sandbox configuration on 32bit
by Michal Suchanek 01 Mar '23

01 Mar '23

Currently sandbox configuration defautls to 64bit and there is no automation for building 32bit sandbox on 32bit hosts. cpp does not know about target specification, code needs to be compiled to determine integer width. Add a test program that prints the integer width, and a make target that aligns the sandbox configuration with the result. Signed-off-by: Michal Suchanek <msuchanek(a)suse.de> --- Makefile | 6 ++++++ doc/arch/sandbox.rst | 16 +++++++++++----- test/py/conftest.py | 1 + tools/Makefile | 2 ++ tools/bits-per-long.c | 14 ++++++++++++++ 5 files changed, 34 insertions(+), 5 deletions(-) create mode 100644 tools/bits-per-long.c diff --git a/Makefile b/Makefile index 3866cc62f9..e5463573f3 100644 --- a/Makefile +++ b/Makefile @@ -2166,6 +2166,12 @@ tools-all: envtools tools ; cross_tools: export CROSS_BUILD_TOOLS=y cross_tools: tools ; +PHONY += set_host_bits +set_host_bits: tools + $(Q)sed -i -e /CONFIG_HOST_$$($(objtree)/tools/bits-per-long)BIT/d $(KCONFIG_CONFIG) + $(Q)sed -i -E -e "s/CONFIG_HOST_(..)BIT=y/# CONFIG_HOST_\1BIT is not set/" $(KCONFIG_CONFIG) + $(Q)echo CONFIG_HOST_$$($(objtree)/tools/bits-per-long)BIT=y >> $(KCONFIG_CONFIG) + .PHONY : CHANGELOG CHANGELOG: git log --no-merges U-Boot-1_1_5.. | \ diff --git a/doc/arch/sandbox.rst b/doc/arch/sandbox.rst index 068d4a3be4..d751205eba 100644 --- a/doc/arch/sandbox.rst +++ b/doc/arch/sandbox.rst @@ -33,9 +33,11 @@ machines. There are two versions of the sandbox: One using 32-bit-wide integers, and one using 64-bit-wide integers. The 32-bit version can be build and run on either -32 or 64-bit hosts by either selecting or deselecting CONFIG_SANDBOX_32BIT; by -default, the sandbox it built for a 32-bit host. The sandbox using 64-bit-wide -integers can only be built on 64-bit hosts. +32 or 64-bit hosts by either selecting or deselecting HOST_64BIT; by +default, the sandbox it built for a 64-bit host. The sandbox using 64-bit-wide +integers can only be built on 64-bit hosts. There is no automation for ensuring +32bit build on 32bit hosts - use ``make set_host_bits`` to adjust the sandbox +config. Note that standalone/API support is not available at present. @@ -51,7 +53,9 @@ Basic Operation To run sandbox U-Boot use something like:: - make sandbox_defconfig all + make sandbox_defconfig + make set_host_bits + make all ./u-boot Note: If you get errors about 'sdl-config: Command not found' you may need to @@ -59,7 +63,9 @@ install libsdl2.0-dev or similar to get SDL support. Alternatively you can build sandbox without SDL (i.e. no display/keyboard support) by removing the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using:: - make sandbox_defconfig all NO_SDL=1 + make sandbox_defconfig + make set_host_bits + make all NO_SDL=1 ./u-boot U-Boot will start on your computer, showing a sandbox emulation of the serial diff --git a/test/py/conftest.py b/test/py/conftest.py index 304e93164a..3d1fd6883a 100644 --- a/test/py/conftest.py +++ b/test/py/conftest.py @@ -104,6 +104,7 @@ def run_build(config, source_dir, build_dir, board_type, log): o_opt = '' cmds = ( ['make', o_opt, '-s', board_type + '_defconfig'], + ['make', o_opt, '-s', 'set_host_bits'], ['make', o_opt, '-s', '-j{}'.format(os.cpu_count())], ) name = 'make' diff --git a/tools/Makefile b/tools/Makefile index 34a1aa7a8b..d6b585953d 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -68,6 +68,8 @@ HOSTCFLAGS_img2srec.o := -pedantic hostprogs-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes HOSTCFLAGS_xway-swap-bytes.o := -pedantic +hostprogs-y += bits-per-long + hostprogs-y += mkenvimage mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o diff --git a/tools/bits-per-long.c b/tools/bits-per-long.c new file mode 100644 index 0000000000..7630e1623f --- /dev/null +++ b/tools/bits-per-long.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <stdio.h> + +int main(int argc, char **argv) +{ + unsigned long testvar = ~0UL; + unsigned int i; + + for (i = 0; testvar; i++, testvar >>= 1) + ; + + return printf("%u\n", i); +} + -- 2.37.3

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[PATCH v1 00/11] rockchip fixes and extend rk3568 support
by Peter Geis 27 Feb '23

27 Feb '23

to: Simon Glass <sjg(a)chromium.org> to: Philipp Tomsich <philipp.tomsich(a)vrull.eu> to: Kever Yang <kever.yang(a)rock-chips.com> to: Lukasz Majewski <lukma(a)denx.de> to: Sean Anderson <seanga2(a)gmail.com> to: Peng Fan <peng.fan(a)nxp.com> to: Jaehoon Chung <jh80.chung(a)samsung.com> to: Heiko Stübner <heiko(a)sntech.de> cc: u-boot(a)lists.denx.de Good Evening, The following is a few patches for rockchip mainline u-boot support. Patches 1-3 are fixes for the rk3568 reset handler, rockchip emmc dma to sram, and building the rockchip-sfc driver. Patch 4 adds a sanity check for the minimum sfc frequency. Patch 5 and 6 add adc support to spl and enable the rockchip recovery handler in spl, before attempting to load u-boot. Patch 7 enables rk3568 spl bootrom device detection. Patch 8 enables automatic clock gating and other power saving features on rk3568, which solves the chip running hotter compared to downstream. Patch 9 and 10 move the dwc3 platform data to the chip specific code and enable dwc3 otg support on rk3568. Patch 11 is an RFC patch for fixing ram detection on rk3568. Downstream goes about this a different way, where they implemented a special library to handle this. Please review and *especially test* patch 11. Very Respectfully, Peter Geis Peter Geis (11): clk: rockchip: rk3568: fix reset handler mmc: sdhci: allow disabling sdma in spl spi: rockchip-sfc: fix building rockchip-sfc spi: rockchip-sfc: sanity check minimum freq spl: support adc drivers in spl rockchip: handle bootrom recovery mode in spl rockchip: rk3568: add boot device detection rockchip: rk3568: enable automatic clock gating rockchip: move dwc3 config to chip specific handler rockchip: rk3568: add dwc3 otg support [RFC] rockchip: rk356x: attempt to fix ram detection arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/Makefile | 6 +- arch/arm/mach-rockchip/board.c | 24 ------ arch/arm/mach-rockchip/boot_mode.c | 4 +- arch/arm/mach-rockchip/rk3399/rk3399.c | 29 +++++++ arch/arm/mach-rockchip/rk3568/rk3568.c | 112 +++++++++++++++++++++++++ arch/arm/mach-rockchip/sdram.c | 19 +++-- common/board_f.c | 7 ++ common/spl/Kconfig | 5 ++ drivers/Makefile | 1 + drivers/clk/rockchip/clk_rk3568.c | 2 + drivers/mmc/Kconfig | 7 ++ drivers/mmc/sdhci.c | 6 +- drivers/spi/rockchip_sfc.c | 6 ++ include/configs/rk3568_common.h | 5 ++ 15 files changed, 197 insertions(+), 37 deletions(-) -- 2.25.1

7 43

[RFC PATCH v1 0/9] Renesas RZ/N1 SoC initial support
by Ralph Siemsen 22 Feb '23

22 Feb '23

The RZ/N1 is a family of SoC devices from Renesas [1], featuring ARM Cortex-A7 and/or Cortex-M3 CPU, industrial ethernet protocols, integrated Ethernet switch, and numerous peripherals. This is a first step in upstreaming support for the RZ/N1 family. Currently it contains just enough to boot to the u-boot prompt. Additional patches will follow to support flash, SD, USB, Ethernet, etc. At this point, I am looking for general feedback about the overall direction and structure. I'm aware of several checkpatch warnings, and some TODO/FIXME items, which will be addressed. This work is based on a vendor-supplied u-boot 2017.01 tree [2], which supports several eval boards, none of which I have access to. Instead development has been done on a Schneider LCES2 board, which is fairly similar to the Renesas RZ/N1D-DB Demo board. The patches are currently against v2022.10-rc2. [1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-… [2] https://github.com/renesas-rz/rzn1_u-boot/tree/rzn1-stable Michel Pollet (1): tools: Add tool to create Renesas SPKG images Ralph Siemsen (8): ARM: armv7: add non-SPL enable for Cortex SMPEN clk: renesas: prepare for non-RCAR clock drivers clk: renesas: add R906G032 driver pinctrl: renesas: add R906G032 driver ram: cadence: add driver for Cadence EDAC dts: basic devicetree for Renesas RZ/N1 SoC ARM: rzn1: basic support for Renesas RZ/N1 SoC board: schneider: add LCES board support arch/arm/Kconfig | 17 + arch/arm/Makefile | 1 + arch/arm/cpu/armv7/Kconfig | 5 + arch/arm/dts/r9a06g032-rzn1d400-lces.dts | 50 ++ arch/arm/dts/r9a06g032.dtsi | 225 ++++++ arch/arm/mach-rzn1/Kconfig | 32 + arch/arm/mach-rzn1/Makefile | 3 + arch/arm/mach-rzn1/cpu_info.c | 20 + board/schneider/lces/Kconfig | 12 + board/schneider/lces/Makefile | 3 + board/schneider/lces/ddr_timing.c | 140 ++++ .../lces/jedec_ddr3_2g_x16_1333h_500_cl8.h | 399 ++++++++++ board/schneider/lces/lces.c | 41 + configs/lces_defconfig | 26 + drivers/clk/renesas/Kconfig | 8 +- drivers/clk/renesas/Makefile | 6 +- drivers/clk/renesas/r9a06g032-clocks.c | 734 ++++++++++++++++++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/renesas/Kconfig | 7 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pinctrl-rzn1.c | 398 ++++++++++ drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 2 + drivers/ram/cadence/Kconfig | 24 + drivers/ram/cadence/Makefile | 1 + drivers/ram/cadence/ddr_async.c | 295 +++++++ drivers/ram/cadence/ddr_ctrl.c | 414 ++++++++++ drivers/ram/cadence/ddr_ctrl.h | 172 ++++ include/configs/lces.h | 22 + include/dt-bindings/clock/r9a06g032-sysctrl.h | 148 ++++ include/dt-bindings/pinctrl/rzn1-pinctrl.h | 141 ++++ tools/Makefile | 2 + tools/spkg_header.h | 49 ++ tools/spkg_utility.c | 306 ++++++++ 34 files changed, 3702 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/r9a06g032-rzn1d400-lces.dts create mode 100644 arch/arm/dts/r9a06g032.dtsi create mode 100644 arch/arm/mach-rzn1/Kconfig create mode 100644 arch/arm/mach-rzn1/Makefile create mode 100644 arch/arm/mach-rzn1/cpu_info.c create mode 100644 board/schneider/lces/Kconfig create mode 100644 board/schneider/lces/Makefile create mode 100644 board/schneider/lces/ddr_timing.c create mode 100644 board/schneider/lces/jedec_ddr3_2g_x16_1333h_500_cl8.h create mode 100644 board/schneider/lces/lces.c create mode 100644 configs/lces_defconfig create mode 100644 drivers/clk/renesas/r9a06g032-clocks.c create mode 100644 drivers/pinctrl/renesas/pinctrl-rzn1.c create mode 100644 drivers/ram/cadence/Kconfig create mode 100644 drivers/ram/cadence/Makefile create mode 100644 drivers/ram/cadence/ddr_async.c create mode 100644 drivers/ram/cadence/ddr_ctrl.c create mode 100644 drivers/ram/cadence/ddr_ctrl.h create mode 100644 include/configs/lces.h create mode 100644 include/dt-bindings/clock/r9a06g032-sysctrl.h create mode 100644 include/dt-bindings/pinctrl/rzn1-pinctrl.h create mode 100644 tools/spkg_header.h create mode 100644 tools/spkg_utility.c -- 2.25.1

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[PATCH] arm: dts: rockchip: rk3399: nanopi-r4s: Provide smbios sysinfo
by Christian Kohlschütter 22 Feb '23

22 Feb '23

Provide human-readable manufacturer and product names for the FriendlyELEC NanoPi R4S. Enable CONFIG_SYSINFO and CONFIG_SYSINFO_SMBIOS by default. Signed-off-by: Christian Kohlschütter <christian(a)kohlschutter.com> --- arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi | 22 ++++++++++++++++++++++ configs/nanopi-r4s-rk3399_defconfig | 2 ++ 2 files changed, 24 insertions(+) diff --git a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi index cd1642527b..69800cc368 100644 --- a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi @@ -14,3 +14,25 @@ #include "rk3399-nanopi4-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi" + +/ { + smbios { + compatible = "u-boot,sysinfo-smbios"; + + smbios { + system { + manufacturer = "FriendlyELEC"; + product = "NanoPi R4S"; + }; + + baseboard { + manufacturer = "FriendlyELEC"; + product = "NanoPi R4S"; + }; + + chassis { + manufacturer = "FriendlyELEC"; + }; + }; + }; +}; diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index dd2579d2e0..502f007e6e 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -75,3 +75,5 @@ CONFIG_MISC=y CONFIG_MISC_INIT_R=y CONFIG_ROCKCHIP_EFUSE=y CONFIG_ROCKCHIP_OTP=y +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y -- 2.36.2

3 8

[PATCH 0/3] Introduce new sign binman's option
by Ivan Mikhaylov 18 Feb '23

18 Feb '23

From: Ivan Mikhaylov <ivan.mikhaylov(a)siemens.com> This patch introduces prototype of new sign binman's option. Enhancing the sign procedure, as example: mkimage -G privateky -r -o sha256,rsa4096 -F fit.fit binman replace -i flash.bin -f fit.fit fit into: binman sign -i flash.bin -k privatekey -a sha256,rsa4096 -f fit.fit fit It works with extracted FIT container and image, which provides key signing and replacing FIT container in directed image. Also, I'll add additional enhancement in future to this procedure with skipping on FIT container and providing extract->sign->replace in whole instead of sign->replace with documentation update and test as well. As example: binman sign -i flash.bin -k privatekey -a sha256,rsa4096 -f fit Ivan Mikhaylov (3): binman: add sign option for binman binman: add documentation for binman sign option binman: add test for sign option tools/binman/binman.rst | 10 +++++ tools/binman/cmdline.py | 13 ++++++ tools/binman/control.py | 26 +++++++++++- tools/binman/ftest.py | 42 +++++++++++++++++++ tools/binman/test/225_fit_sign.dts | 67 ++++++++++++++++++++++++++++++ 5 files changed, 157 insertions(+), 1 deletion(-) create mode 100644 tools/binman/test/225_fit_sign.dts -- 2.35.1

4 24

bind/unbind command not working for usb_ether
by Tim Harvey 15 Feb '23

15 Feb '23

Greetings, I'm trying to understand how to use the U-Boot bind command to bind the usb_ether driver to the usb class to register a USB ethernet gadget network device as referenced in: commit 02291d83fdaaf ("doc: add bind/unbind command documentation") commit 49c752c93a78 ("cmd: Add bind/unbind commands to bind a device to a driver from the command line") I have enabled: CONFIG_DM_USB=y CONFIG_USB_GADGET=y CONFIG_USB_ETHER=y However the 'usb_ether' driver is never registered and thus doesn't appear in a 'dm tree' list and can't be bound to the usb controller. With the help of Heiko I've found two ways to get the usb_ether driver to register: dt-way: - add of match in ether.c: diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 63d552bc8b..8e2a05a5af 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -2690,10 +2690,16 @@ int usb_ether_init(void) return 0; } +static const struct udevice_id usb_ether_ids[] = { + { .compatible = "gadget,usb_ether" }, + { } +}; + U_BOOT_DRIVER(eth_usb) = { .name = "usb_ether", .id = UCLASS_ETH, .probe = usb_eth_probe, + .of_match = usb_ether_ids, .ops = &usb_eth_ops, .priv_auto_alloc_size = sizeof(struct ether_priv), .platdata_auto_alloc_size = sizeof(struct eth_pdata), - then add it directly in your board u-boot.dts: +&usbotg1 { + usb_ether0 { + compatible = "gadget,usb_ether"; + status = "okay"; + }; +}; The non-dt way: - bind it manually in board code with: { struct udevice *dev; struct udevice *usb_dev; int ret; ret = uclass_first_device(UCLASS_USB, &usb_dev); if (!usb_dev || ret) printf("%s: No USB device found\n", __func__); ret = device_bind_driver(usb_dev, "usb_ether", "usb_ether", &dev); if (!dev || ret) printf("%s: usb - not able to bind usb_ether device\n", __func__); } - Note that this is the same code from usb_ether_init() but with UCLASS_USB instead of UCLASS_USB_GADGET_GENERIC What is the intended way to bind the usb_ether gadget device at runtime? Additionally Heiko found that once bound and usb_ether is registered as a network device using a network command like ping/tftpboot calls usb_setup_ehci_gadget() which removes the USB driver ... and so also the child usb ethernet gadget device then re-probes only the usb driver and not the gadget thus fails. I compared this to how the 'ums' command works and that also removes the usb driver and child nodes but because ums isn't a gadget driver it doesn't get removed and works. Best Regards, Tim

5 12

[PATCH v2] riscv: cancel the limitation that NR_CPUS is less than or equal to 32
by Xiang W 13 Feb '23

13 Feb '23

Various specifications of riscv allow the number of hart to be greater than 32. The limit of 32 is determined by gd->arch.available_harts. We can eliminate this limitation through bitmaps. Currently, the number of hart is limited to 4095, and 4095 is the limit of the RISC-V Advanced Core Local Interruptor Specification. Test on sifive unmatched. Signed-off-by: Xiang W <wxjstz(a)126.com> --- Changes since v1: * When NR_CPUS is very large, the value of GD_AVAILABLE_HARTS will overflow the immediate range of ld/lw. This patch fixes this problem arch/riscv/Kconfig | 4 ++-- arch/riscv/cpu/start.S | 21 ++++++++++++++++----- arch/riscv/include/asm/global_data.h | 4 +++- arch/riscv/lib/smp.c | 2 +- 4 files changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ba29e70acf..7b9c7f5bca 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -220,8 +220,8 @@ config SPL_SMP all, single processor machines. config NR_CPUS - int "Maximum number of CPUs (2-32)" - range 2 32 + int "Maximum number of CPUs (2-4095)" + range 2 4095 depends on SMP || SPL_SMP default 8 help diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 76850ec9be..92f3b78f29 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -166,11 +166,22 @@ wait_for_gd_init: mv gp, s0 /* register available harts in the available_harts mask */ - li t1, 1 - sll t1, t1, tp - LREG t2, GD_AVAILABLE_HARTS(gp) - or t2, t2, t1 - SREG t2, GD_AVAILABLE_HARTS(gp) + li t1, GD_AVAILABLE_HARTS + add t1, t1, gp + LREG t1, 0(t1) +#if defined(CONFIG_ARCH_RV64I) + srli t2, tp, 6 + slli t2, t2, 3 +#elif defined(CONFIG_ARCH_RV32I) + srli t2, tp, 5 + slli t2, t2, 2 +#endif + add t1, t1, t2 + LREG t2, 0(t1) + li t3, 1 + sll t3, t3, tp + or t2, t2, t3 + SREG t2, 0(t1) amoswap.w.rl zero, zero, 0(t0) diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 095484a635..6de2ee0b25 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -10,9 +10,11 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include <config.h> #include <asm/smp.h> #include <asm/u-boot.h> #include <compiler.h> +#include <linux/bitops.h> /* Architecture-specific global data */ struct arch_global_data { @@ -28,7 +30,7 @@ struct arch_global_data { struct ipi_data ipi[CONFIG_NR_CPUS]; #endif #ifndef CONFIG_XIP - ulong available_harts; + ulong available_harts[BITS_TO_LONGS(CONFIG_NR_CPUS)]; #endif }; diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ba992100ad..e8e391fd41 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -47,7 +47,7 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) #ifndef CONFIG_XIP /* skip if hart is not available */ - if (!(gd->arch.available_harts & (1 << reg))) + if (!test_bit(reg, gd->arch.available_harts)) continue; #endif -- 2.30.2

3 8

[PATCH v2 0/5] Add ARMv8 CE sha1/sha256 support
by Loic Poulain 08 Feb '23

08 Feb '23

This series adds support for the SHA-1 and SHA-256 Secure Hash Algorithm for CPUs that have support of the ARM v8 Crypto Extensions. It Improves speed of integrity & signature checking procedures. V2: - Add cover letter & sha256 support. - Kconfig default 'y' only if SHA1 and SHA256 selected Loic Poulain (5): lib: sha1: Add support for hardware specific sha1_process sha1: Fix digest state size/type armv8 SHA-1 using ARMv8 Crypto Extensions: lib: sha256: Add support for hardware specific sha256_process armv8 SHA-256 using ARMv8 Crypto Extensions arch/arm/cpu/armv8/Kconfig | 15 ++++ arch/arm/cpu/armv8/Makefile | 2 + arch/arm/cpu/armv8/sha1_ce_core.S | 132 +++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/sha1_ce_glue.c | 21 ++++++ arch/arm/cpu/armv8/sha256_ce_core.S | 134 ++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/sha256_ce_glue.c | 21 ++++++ include/u-boot/sha1.h | 2 +- lib/sha1.c | 26 +++++-- lib/sha256.c | 26 +++++-- 9 files changed, 364 insertions(+), 15 deletions(-) create mode 100644 arch/arm/cpu/armv8/sha1_ce_core.S create mode 100644 arch/arm/cpu/armv8/sha1_ce_glue.c create mode 100644 arch/arm/cpu/armv8/sha256_ce_core.S create mode 100644 arch/arm/cpu/armv8/sha256_ce_glue.c -- 2.7.4

3 22

[PATCH] imx8m: Select BINMAN via SoC level
by Fabio Estevam 03 Feb '23

03 Feb '23

From: Fabio Estevam <festevam(a)denx.de> Since all imx8m boards have been converted to use binman, select binman via SoC level rather than making the selection for each board. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- arch/arm/mach-imx/imx8m/Kconfig | 33 +-------------------------------- 1 file changed, 1 insertion(+), 32 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 8cd7c7a8dd8b..c7a272ec18f5 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -2,6 +2,7 @@ if ARCH_IMX8M config IMX8M bool + select BINMAN select HAS_CAAM select ROM_UNIFIED_SECTIONS @@ -31,13 +32,11 @@ choice config TARGET_IMX8MQ_CM bool "Ronetix iMX8MQ-CM SoM" - select BINMAN select IMX8MQ select IMX8M_LPDDR4 config TARGET_IMX8MQ_EVK bool "imx8mq_evk" - select BINMAN select IMX8MQ select IMX8M_LPDDR4 select FSL_CAAM @@ -46,20 +45,17 @@ config TARGET_IMX8MQ_EVK config TARGET_IMX8MQ_PHANBELL bool "imx8mq_phanbell" - select BINMAN select IMX8MQ select IMX8M_LPDDR4 config TARGET_IMX8MM_DATA_MODUL_EDM_SBC bool "Data Modul eDM SBC i.MX8M Mini" - select BINMAN select IMX8MM select IMX8M_LPDDR4 select SUPPORT_SPL config TARGET_IMX8MM_EVK bool "imx8mm LPDDR4 EVK board" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 @@ -69,7 +65,6 @@ config TARGET_IMX8MM_EVK config TARGET_IMX8MM_ICORE_MX8MM bool "Engicam i.Core MX8M Mini SOM" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 @@ -88,14 +83,12 @@ config TARGET_IMX8MM_ICORE_MX8MM config TARGET_IMX8MM_MX8MENLO bool "Support i.MX8M Mini MX8Menlo board based on Toradex Verdin SoM" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_IMX8MM_VENICE bool "Support Gateworks Venice iMX8M Mini module" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 @@ -104,7 +97,6 @@ config TARGET_IMX8MM_VENICE config TARGET_KONTRON_MX8MM bool "Kontron Electronics N80xx" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 @@ -114,21 +106,18 @@ config TARGET_KONTRON_MX8MM config TARGET_IMX8MN_BSH_SMM_S2 bool "imx8mn-bsh-smm-s2" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_DDR3L config TARGET_IMX8MN_BSH_SMM_S2PRO bool "imx8mn-bsh-smm-s2pro" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_DDR3L config TARGET_IMX8MN_EVK bool "imx8mn LPDDR4 EVK board" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 @@ -137,7 +126,6 @@ config TARGET_IMX8MN_EVK config TARGET_IMX8MN_DDR4_EVK bool "imx8mn DDR4 EVK board" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_DDR4 @@ -146,7 +134,6 @@ config TARGET_IMX8MN_DDR4_EVK config TARGET_IMX8MN_VENICE bool "Support Gateworks Venice iMX8M Nano module" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 @@ -155,14 +142,12 @@ config TARGET_IMX8MN_VENICE config TARGET_IMX8MP_DH_DHCOM_PDK2 bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus" - select BINMAN select IMX8MP select IMX8M_LPDDR4 select SUPPORT_SPL config TARGET_IMX8MP_ICORE_MX8MP bool "Engicam i.Core MX8M Plus SOM" - select BINMAN select IMX8MP select IMX8M_LPDDR4 select SUPPORT_SPL @@ -176,7 +161,6 @@ config TARGET_IMX8MP_ICORE_MX8MP config TARGET_IMX8MP_EVK bool "imx8mp LPDDR4 EVK board" - select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 @@ -186,7 +170,6 @@ config TARGET_IMX8MP_EVK config TARGET_IMX8MP_VENICE bool "Support Gateworks Venice iMX8M Plus module" - select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 @@ -195,68 +178,58 @@ config TARGET_IMX8MP_VENICE config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" - select BINMAN select IMX8MQ select IMX8M_LPDDR4 config TARGET_IMX8MN_VAR_SOM bool "imx8mn_var_som" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_DDR4 config TARGET_KONTRON_PITX_IMX8M bool "Support Kontron pITX-imx8m" - select BINMAN select IMX8MQ select IMX8M_LPDDR4 config TARGET_VERDIN_IMX8MM bool "Support Toradex Verdin iMX8M Mini module" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_VERDIN_IMX8MP bool "Support Toradex Verdin iMX8M Plus module" - select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_IMX8MM_BEACON bool "imx8mm Beacon Embedded devkit" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_IMX8MN_BEACON bool "imx8mn Beacon Embedded devkit" - select BINMAN select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_PHYCORE_IMX8MM bool "PHYTEC PHYCORE i.MX8MM" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_PHYCORE_IMX8MP bool "PHYTEC PHYCORE i.MX8MP" - select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_IMX8MM_CL_IOT_GATE bool "CompuLab iot-gate-imx8" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 @@ -264,7 +237,6 @@ config TARGET_IMX8MM_CL_IOT_GATE config TARGET_IMX8MM_CL_IOT_GATE_OPTEE bool "CompuLab iot-gate-imx8 with optee support" - select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 @@ -272,21 +244,18 @@ config TARGET_IMX8MM_CL_IOT_GATE_OPTEE config TARGET_IMX8MP_RSB3720A1_4G bool "Support i.MX8MP RSB3720A1 4G" - select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_IMX8MP_RSB3720A1_6G bool "Support i.MX8MP RSB3720A1 6G" - select BINMAN select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 config TARGET_LIBREM5 bool "Purism Librem5 Phone" - select BINMAN select IMX8MQ select SUPPORT_SPL select IMX8M_LPDDR4 -- 2.25.1

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[PATCH] RFC: nvedit: support doing one (extra) expansion of the value in "env set"
by Rasmus Villemoes 02 Feb '23

02 Feb '23

Currently, there's no way to fetch the value of an environment variable whose name is stored in some other variable, or generated from such - in non-working pseudo-code, ${${varname}} ${array${index}} This forces some scripts to needlessly duplicate logic and hardcode assumptions. For example, in an A/B scheme with three variables BOOT_ORDER # Either "A B" or "B A" depending on which slot was last updated BOOT_A_LEFT # 0..3 BOOT_B_LEFT # 0..3 when one needs to determine the slot to boot from, one does something like setenv found for slot in $BOOT_ORDER ; do if test "x$found" != "x" ; then # work around lack of break elif test "x$slot" = "xA" ; then if test $BOOT_A_LEFT -gt 0 ; then setexpr BOOT_A_LEFT $BOOT_A_LEFT - 1 setenv found A setenv bootargs ${bootargs_A} setenv ubivol ${ubivol_A} # more setup based on A fi elif test "x$slot" = "xB" ; then if test $BOOT_B_LEFT -gt 0 ; then # the same ... fi fi done This is already bad enough, but extending that to A/B/C is tedious and prone to copy-pastos. So this is an attempt at allowing one to do "env set -E var value1 value2" with the effect that, of course, normal variable expansion happens on the command line, the valueX are joined with spaces as usual, and then one more pass is done over that string replacing occurrences of ${foo}. The above would become setenv found for slot in $BOOT_ORDER ; do if test "x$found" != "x" ; then # work around lack of break else env set -E boot_left "\${BOOT_${slot}_LEFT}" if test $boot_left -gt 0 ; then setexpr BOOT_${slot}_LEFT $boot_left - 1 env set found $slot env set -E bootargs "\${bootargs_${slot}}" env set -E ubivol "\${ubivol_${slot}}" fi fi done I'm pleasantly surprised it was that easy to implement, but of course I'm cheating a bit (cli_simple_process_macros is only available if CONFIG_CMDLINE, though I think cli_simple.o could be unconditionally built and then link-time GC should get rid of the excess functions). This has been lightly tested in the sandbox. I'll add some proper unit tests, update the help texts and try to handle the Kconfig issue if this is something that might be accepted. Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- cmd/nvedit.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 81d94cd193..ff6ffcb674 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -224,7 +224,7 @@ DONE: */ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) { - int i, len; + int i, len, expand = 0; char *name, *value, *s; struct env_entry e, *ep; @@ -244,6 +244,9 @@ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) case 'f': /* force */ env_flag |= H_FORCE; break; + case 'E': + expand = 1; + break; default: return CMD_RET_USAGE; } @@ -287,6 +290,18 @@ static int _do_env_set(int flag, int argc, char * const argv[], int env_flag) if (s != value) *--s = '\0'; + if (expand) { + char *expanded = malloc(CONFIG_SYS_CBSIZE); + + if (expanded == NULL) { + printf("## Can't malloc %d bytes\n", CONFIG_SYS_CBSIZE); + free(value); + return 1; + } + cli_simple_process_macros(value, expanded); + free(value); + value = expanded; + } e.key = name; e.data = value; hsearch_r(e, ENV_ENTER, &ep, &env_htab, env_flag); -- 2.23.0

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