September 2021 - U-Boot

[ANN] U-Boot v2021.10-rc4 released
by Tom Rini 18 Sep '21

18 Sep '21

Hey all, Alright, I'm a day late, but, here's v2021.10-rc4. We've had a few regressions pop up of late, unfortunately. I've pushed the fix for (what I believe are) existing FIT images showing a problem where we calculated the crc32 wrong. And we're just now starting to figure out the proper fix for a problem that was introduced late in v2021.07 with SPI buses not being configured in the right mode (or in Linux Kernel terms, spi-cpha/spi-cpol being set on platforms where that's not correct). In terms of a changelog, git log --merges v2021.10-rc3..v2021.10-rc4 contains what I've pulled but as always, better PR messages and tags will provide better results here. We should be releasing on October 4th, 2021 as expected. Thanks all! -- Tom

4 5

[PATCH V2] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge
by Nishanth Menon 18 Sep '21

18 Sep '21

From: Roger Quadros <rogerq(a)ti.com> NB0 is bridge to SRAM and NB1 is bridge to DDR. To ensure that SRAM transfers are not stalled due to delays during DDR refreshes, SRAM traffic should be higher priority (threadmap=2) than DDR traffic (threadmap=0). This fixup is critical to provide deterministic access latency to MSMC from ICSSG, it applies to all AM65 silicon revisions and is due to incorrect reset values (has no erratum id) and statically setting things up should be done independent of usecases and board. This specific style of Northbridge configuration is specific only to AM65x devices, follow-on K3 devices have different data prioritization schemes (ASEL and the like) and hence the fixup applies purely to AM65x. Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in case of SR1 devices, on SR2 devices, lockups were not observed so far but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower throughput. Signed-off-by: Roger Quadros <rogerq(a)ti.com> Acked-by: Andrew F. Davis <afd(a)ti.com> Acked-by: Tomi Valkeinen <tomi.valkeinen(a)ti.com> Acked-by: Benoit Parrot <bparrot(a)ti.com> [Jan: rebased, dropped used define, extended commit log] Signed-off-by: Jan Kiszka <jan.kiszka(a)siemens.com> [Nishanth: Provide relevant context in the commit message] Signed-off-by: Nishanth Menon<nm(a)ti.com> --- Changes in V2: * rebase (Thanks Jan) * Updated commit message. V1: https://patchwork.ozlabs.org/project/uboot/patch/20200130080503.28657-1-rog… arch/arm/mach-k3/am6_init.c | 15 +++++++++++++++ arch/arm/mach-k3/include/mach/am6_hardware.h | 6 ++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 425b3f93c865..ffb7aaded2e7 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -151,6 +151,19 @@ int fdtdec_board_setup(const void *fdt_blob) return fixup_usb_boot(); } #endif + +static void setup_am654_navss_northbridge(void) +{ + /* + * NB0 is bridge to SRAM and NB1 is bridge to DDR. + * To ensure that SRAM transfers are not stalled due to + * delays during DDR refreshes, SRAM traffic should be higher + * priority (threadmap=2) than DDR traffic (threadmap=0). + */ + writel(0x2, NAVSS0_NBSS_NB0_CFG_BASE + NAVSS_NBSS_THREADMAP); + writel(0x0, NAVSS0_NBSS_NB1_CFG_BASE + NAVSS_NBSS_THREADMAP); +} + void board_init_f(ulong dummy) { #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS) @@ -168,6 +181,8 @@ void board_init_f(ulong dummy) /* Make all control module registers accessible */ ctrl_mmr_unlock(); + setup_am654_navss_northbridge(); + #ifdef CONFIG_CPU_V7R disable_linefill_optimization(); setup_k3_mpu_regions(); diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index 1908a13f0ff2..f533e22e0617 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -52,4 +52,10 @@ /* MCU SCRATCHPAD usage */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE +/* NAVSS Northbridge config */ +#define NAVSS0_NBSS_NB0_CFG_BASE 0x03802000 +#define NAVSS0_NBSS_NB1_CFG_BASE 0x03803000 + +#define NAVSS_NBSS_THREADMAP 0x10 + #endif /* __ASM_ARCH_AM6_HARDWARE_H */ -- 2.32.0

2 1

[PATCH v2 0/5] arm: mach-k3: Fixes for j721e/j7200 clock data and drivers
by Dave Gerlach 18 Sep '21

18 Sep '21

Hi, This is v2 of series with fixes for TI j721e and j7200 platforms data and also some fixes for TI clock drivers that make use of this data. Updates are to patch 3 to address comments from Lokesh and Suman. Patch 3 now contains a note with contact for issues with autogenerated files, http->https in URLs, and an extra blank line before first header. As with v1, all fixes are related to PLL post dividers reporting the wrong frequency, and now the new frequencies for below clocks match what registers are actually configured for. Clock: Old Frequency -> New Frequency ----------------------------------------- postdiv2_16fft_main_0_hsdivout6_clk: 66666667 -> 200000000 postdiv2_16fft_main_1_hsdivout5_clk: 320000000 -> 960000000 postdiv2_16fft_main_1_hsdivout7_clk: 320000000 -> 960000000 Regards, Dave [v1] https://patchwork.ozlabs.org/project/uboot/list/?series=257518 Dave Gerlach (2): arm: mach-k3: Add note to auto-generated files clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write Suman Anna (3): arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks clk: ti: k3: Update driver to account for divider flags arch/arm/mach-k3/j7200/clk-data.c | 91 ++++++++++++----------- arch/arm/mach-k3/j7200/dev-data.c | 6 +- arch/arm/mach-k3/j721e/clk-data.c | 117 ++++++++++++++++-------------- arch/arm/mach-k3/j721e/dev-data.c | 6 +- drivers/clk/ti/clk-k3-pll.c | 13 +++- drivers/clk/ti/clk-k3.c | 4 +- include/k3-clk.h | 30 ++++---- 7 files changed, 149 insertions(+), 118 deletions(-) -- 2.28.0

2 10

[PATCH 0/2] Minor misc. cleanups for TI K3 SoCs
by Suman Anna 18 Sep '21

18 Sep '21

Hi Lokesh, The following are two minor cleanups/fixes that I ran into while doing some development work on a newer SoC due to different Kconfig symbols. Following is the patch summary: - Patch #1 makes the ti_sci_protocol.h self-contained when CONFIG_TI_SCI_PROTOCOL is not defined. - Patch #2 defines a release_resources_for_core_shutdown() stub. This function is used in the common code, but yet is expected to be implemented in a SoC-specific source file. regards Suman Suman Anna (2): firmware: ti_sci: Include linux/err.h in ti_sci_protocol.h arm: mach-k3: common: Add a release_resources_for_core_shutdown() stub arch/arm/mach-k3/common.c | 5 +++++ include/linux/soc/ti/ti_sci_protocol.h | 4 +++- 2 files changed, 8 insertions(+), 1 deletion(-) -- 2.32.0

3 6

[PATCH 0/2] arm: mach-k3: Fix corruption of device manager firmware
by Nishanth Menon 18 Sep '21

18 Sep '21

The following series takes care of two problems: a) A potential race when R5 (boot processor) is parsing and loading DM firmware elf sections way slower than A53 executing. b) We load the FIT image to the same address as the elf sections. See [1] as example. NOTE: Though, in theory, the Device Manager's linker file could be constructed such as to avoid the overlap address, there is no guarentee of implicit assumptions and the fact that DM's firmware can be combined with additional functionality could result in unexpected behavior as well. To prevent this, lets just have explicit load address and sequencing. Nishanth Menon (2): arm: mach-k3: common: Make sure firmware sections are loaded prior to armv8 startup tools: k3_fit_atf: Change DM load address to avoid conflict arch/arm/mach-k3/common.c | 30 ++++++++++++++++++------------ tools/k3_fit_atf.sh | 4 ++-- 2 files changed, 20 insertions(+), 14 deletions(-) [1] $ arm-none-linux-gnueabihf-readelf -S ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f There are 39 section headers, starting at offset 0x2aa98: Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .freertosrst[...] PROGBITS 41010000 000038 000040 00 AX 0 0 8 [ 2] .bootCode PROGBITS 41010a60 000a98 000118 00 AX 0 0 8 [ 3] .startupCode PROGBITS 41010410 000448 000338 00 AX 0 0 8 [ 4] .startupData PROGBITS 41010748 000780 000318 00 A 0 0 8 [ 5] .text.hwi PROGBITS 41010040 000078 0003d0 00 AX 0 0 8 [ 6] .text.cache NOBITS 41010410 02a680 000000 00 AX 0 0 8 [ 7] .text.mpu NOBITS 41010410 02a680 000000 00 AX 0 0 8 [ 8] .text.boot NOBITS 41010410 02a680 000000 00 AX 0 0 8 [ 9] .text PROGBITS a05b8fb0 002000 016340 00 AX 0 0 8 [10] .const PROGBITS a05cf2f0 018340 00c470 00 A 0 0 8 [11] .cinit PROGBITS a0581400 001100 000818 00 A 0 0 8 [12] .bss NOBITS a0582000 002000 036faa 00 WA 0 0 8192 [13] .far NOBITS 00000000 000000 000000 00 0 0 4 [14] .data NOBITS a05db780 024800 008100 00 WA 0 0 128 [15] .sysmem NOBITS 00000000 000000 000000 00 0 0 1 [16] .data_buffer NOBITS 00000000 02a680 000000 00 WA 0 0 128 [17] .bss.devgroup* NOBITS a05e9700 02a680 0011f8 00 WA 0 0 4 [18] .const.devgroup* PROGBITS a05e3880 024800 004710 00 A 0 0 4 [19] .boardcfg_data PROGBITS a05e8000 028f80 001700 00 A 0 0 128 [20] .benchmark_buffer NOBITS 00000000 000000 000000 00 0 0 8 [21] ipc_data_buffer NOBITS a0400000 001100 181400 00 WA 0 0 128 [22] .resource_table PROGBITS a0180000 001000 00008c 00 A 0 0 4096 [23] .tracebuf NOBITS a0100000 000c00 080000 00 WA 0 0 1024 [24] .stack NOBITS a0ffc000 02a680 004000 00 WA 0 0 8 [25] .irqStack NOBITS a0ffae00 02a880 001000 00 A 0 0 4 [26] .fiqStack NOBITS a0ffbe00 02b880 000100 00 A 0 0 4 [27] .abortStack NOBITS a0ffbf00 02b980 000100 00 A 0 0 4 [28] .undStack NOBITS a0ffac00 02a680 000100 00 A 0 0 4 [29] .svcStack NOBITS a0ffad00 02a780 000100 00 A 0 0 4 [30] .TI.noinit NOBITS 00000000 000000 000000 00 0 0 4 [31] .TI.persistent NOBITS 00000000 000000 000000 00 0 0 128 [32] __llvm_prf_cnts NOBITS a0400000 02a680 000000 00 A 0 0 4 [33] Veneer$$CMSE NOBITS 00000000 000000 000000 00 0 0 1 [34] .ARM.attributes ARM_ATTRIBUTES 00000000 02a680 00005b 00 0 0 0 [35] .symtab SYMTAB 00000000 02a6dc 000030 10 37 1 0 [36] .TI.section.flags PROGBITS 00000000 02a70c 000020 00 0 0 0 [37] .strtab STRTAB 00000000 02a72c 000014 01 S 0 0 0 [38] .shstrtab STRTAB 00000000 02a740 0001b6 01 S 0 0 0 -- 2.32.0

2 4

IMX8MM fsl_esdhc_imx UHS/HS200/HS400 not working?
by Tim Harvey 17 Sep '21

17 Sep '21

Greetings, Can anyone confirm if IMX8MM UHS/HS200/HS400 is working for them? I had this working in my U-Boot v2021.01 imx8mm-veice branch but it seems to not work in U-Boot master or v2021.07. I know there was a lot of back and forth on this... perhaps I missed something. I haven't been able to bisect yet as I had a lot of patches on top of my v2021.01 branch. Best regards, Tim

1 1

[PATCH] riscv: Fix setting no-map in reserved memory nodes
by Samuel Holland 17 Sep '21

17 Sep '21

The no-map property is wrongly skipped if a no-map reserved memory node follows one without that property. Fix this by not remembering the absence of a no-map property across loop iterations. Fixes: d4ea649f179a ("riscv: Provide a mechanism to fix DT for reserved memory") Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- arch/riscv/lib/fdt_fixup.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index f636b284497..61cf8935269 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -31,7 +31,6 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst) fdt_addr_t addr; fdt_size_t size; int offset, node, err, rmem_offset; - bool nomap = true; char basename[32] = {0}; int bname_len; int max_len = sizeof(basename); @@ -81,9 +80,7 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst) log_err("failed to add reserved memory: %d\n", err); return err; } - if (!fdt_getprop(src, node, "no-map", NULL)) - nomap = false; - if (nomap) { + if (fdt_getprop(src, node, "no-map", NULL)) { rmem_offset = fdt_node_offset_by_phandle(dst, phandle); fdt_setprop_empty(dst, rmem_offset, "no-map"); } -- 2.31.1

3 2

[RFC 0/2] mtd: Support slc-mode for Toshiba TC58TEG5DCLTA00
by Chris Morgan 17 Sep '21

17 Sep '21

From: Chris Morgan <macromorgan(a)hotmail.com> Add support for slc-mode implemented in Linux for the Toshiba TC58TEG5DCLTA00 NAND flash found on the NTC CHIP. This requires the addition of a paired-pages scheme, a new parameter for MTD partitions of slc-mode, and setting the correct paired-pages scheme for the TC58TEG5DCLTA00 flash chip. I will likely need some help making sure this is consistent with the quality expected of upstream, as well as solving some remaining issues (such as ubifs partitions not working with slc-mode set). Signed-off-by: Chris Morgan <macromorgan(a)hotmail.com> Chris Morgan (2): mtd: Add partial support for Linux slc-mode for MLC NAND mtd: Add pairing info for Toshiba TC58TEG5DCLTA00 NAND drivers/mtd/mtdcore.c | 320 ++++++++++++++++++++++++++++--- drivers/mtd/mtdpart.c | 7 + drivers/mtd/nand/raw/nand_base.c | 59 ++++++ include/linux/mtd/mtd.h | 126 ++++++++++++ include/linux/mtd/partitions.h | 2 + include/mtd/mtd-abi.h | 1 + 6 files changed, 491 insertions(+), 24 deletions(-) -- 2.30.2

1 2

[PATCH 00/17] RFC: Split configs between U-Boot proper and SPL builds
by Simon Glass 17 Sep '21

17 Sep '21

At present a single .config file is used to configure the build for all phases, with SPL phases having a SPL_ or TPL_ prefix on each CONFIG to indicate which build it controls. So, for example, we have CONFIG_MISC and CONFIG_SPL_MISC to control the inclusion of MISC drivers in each phase. >From this .config a few other files are generated (by the kconfig tool) for use with make and from C code (auto.conf and autoconf.h). This all works well but is a bit ugly in places, for example requiring the use of a SPL_TPL_ macro in Makefiles to distinguish between options intended for SPL and U-Boot proper. In discussions with trini the idea came up of creating separate config files for each type of build. So instead of using SPL_ or TPL_ prefixes, each build includes its own files with the config it needs. This series takes a pass at implementing this. It makes only minor changes to the existing Kconfig files, to make things work, but updates the kconfig tool to output seperate files for each phase. These changes may need reworking to send upstream. With this series, SPL_TPL_ resolves to an empty value, so it is possible to drop this macro. This cannot be applied as is. Any ad-hoc CONFIG options break the logic in this series, since these are not processed by the kconfig tool. A special xSPL_TPL_ macro is added to show this problem. A run indicative of the current state (without the last patch, which breaks everything) is here: https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/9135 Once CONFIG migration is completed, something along these lines can be applied. Simon Glass (17): env: Avoid checking ENV_IS_IN when env disabled x86: Fix qemu condition for arch_cpu_init() acpi: Add a Kconfig for SPL cmd: Add an SPL Kconfig for CMDLINE and HUSH cros_ec: Add SPL Kconfigs for cros_ec features power: Add SPL Kconfig for sandbox pmc emulator test: Add SPL Kconfig for compression tests sandbox: Enable MISC support for the SPL build serial: Tidy up the Makefile condition for DM_SERIAL virtio: Add SPL Kconfig for virtio kconfig: Refactor code into separate writer functions kconfig: Support writing separate SPL files Makefile: Include the config for the phase being built Makefile: Use empty SPL_ and SPL_TPL_ vars Makefile: Support ad-hoc COMFIX_SPL_IMAGE_SIZE et al kconfig: Update CONFIG_IS_ENABLED() for split files kconfig: Add a new CONFIG() macro Makefile | 11 +- arch/x86/cpu/qemu/qemu.c | 2 +- cmd/Kconfig | 10 ++ cmd/nvedit.c | 2 + configs/sandbox_noinst_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + drivers/core/Kconfig | 5 + drivers/i2c/Kconfig | 10 ++ drivers/power/acpi_pmc/Kconfig | 5 + drivers/serial/Makefile | 2 +- drivers/virtio/Kconfig | 6 + include/linux/kconfig.h | 91 +++------- scripts/Kbuild.include | 17 +- scripts/Makefile.build | 10 +- scripts/Makefile.spl | 33 +++- scripts/kconfig/conf.c | 4 + scripts/kconfig/confdata.c | 286 ++++++++++++++++++++++++++++--- scripts/kconfig/expr.h | 9 + scripts/kconfig/lkc.h | 9 + test/Kconfig | 5 + 20 files changed, 408 insertions(+), 111 deletions(-) -- 2.33.0.309.g3052b89438-goog

1 17

[PATCH] distro_bootcmd: change the default dtb search path to include default kernel dtbs directory
by Qu Wenruo 17 Sep '21

17 Sep '21

When booting using U-boot -> systemd-boot (EFI payload) -> kernel on RK3399, systemd-boot by some bug can't execute its "devicetree" key correctly to load its proper dtb from files. In that case, it will use fallback dtb from U-boot, which can be out-of-date, and on RK3399, even the latest U-boot contains out-of-date dtb which can cause problems like invalid opp tables. And for systemd-boot, it doesn't provide any board specific dtb, but completely relies on the EFI environment provided by U-boot, thus if we can't find a good dtb, the fallback one will be used anyway. So this patch will workaround the problem by appending common linux dtbs directory to the existing "efi_dtb_prefixes" so that for systemd-boot it can use the existing fdt and boot properly. Signed-off-by: Qu Wenruo <wqu(a)suse.com> --- include/config_distro_bootcmd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 2627c2a6a541..4ec87483eb65 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -151,7 +151,7 @@ "load ${devtype} ${devnum}:${distro_bootpart} " \ "${fdt_addr_r} ${prefix}${efi_fdtfile}\0" \ \ - "efi_dtb_prefixes=/ /dtb/ /dtb/current/\0" \ + "efi_dtb_prefixes=/ /dtb/ /dtb/current/ /dtbs/ /dtbs/current/\0" \ "scan_dev_for_efi=" \ "setenv efi_fdtfile ${fdtfile}; " \ BOOTENV_EFI_SET_FDTFILE_FALLBACK \ -- 2.33.0

3 4