September 2021 - U-Boot

[PATCH 1/1] phy: marvell: cp110: Support SATA invert polarity
by Denis Odintsov 27 Sep '21

27 Sep '21

In commit b24bb99d cp110 configuration initially done in u-boot was removed and delegated to atf firmware as smc call. That commit didn't account for later introduced in d13b740c SATA invert polarity support. This patch adds support of passing SATA invert polarity flags to atf firmware during the smc call. Signed-off-by: Denis Odintsov <shiva(a)mail.ru> Cc: Baruch Siach <baruch(a)tkos.co.il> Cc: Rabeeh Khoury <rabeeh(a)solid-run.com> Cc: Stefan Roese <sr(a)denx.de> --- drivers/phy/marvell/comphy_cp110.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 418318d12f..4fe2dfcdd1 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -36,6 +36,10 @@ DECLARE_GLOBAL_DATA_PTR; (COMPHY_CALLER_UBOOT | ((pcie_width) << 18) | \ ((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds)) +/* Invert polarity are bits 1-0 of the mode */ +#define COMPHY_FW_SATA_FORMAT(mode, invert) \ + ((invert) | COMPHY_FW_MODE_FORMAT(mode)) + #define COMPHY_SATA_MODE 0x1 #define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */ #define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */ @@ -607,7 +611,8 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, break; case COMPHY_TYPE_SATA0: case COMPHY_TYPE_SATA1: - mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE); + mode = COMPHY_FW_SATA_FORMAT(COMPHY_SATA_MODE, + serdes_map[lane].invert); ret = comphy_sata_power_up(lane, hpipe_base_addr, comphy_base_addr, ptr_chip_cfg->cp_index, -- 2.33.0

2 2

[PATCH v3 0/4] Add octal DTR support for Macronix flash
by JaimeLiao 27 Sep '21

27 Sep '21

This series add support for Macronix octal DTR flash, add second time Softreset with "INVERT" command extension type and follow linux kernel to enable 4byte opcode when possible. v3: Add flag SPI_NOR_CMD_EXT_INVERT to seperate command extension types. replace CONFIG_SPI_FLASH_MACRONIX with SPI_FLASH_MACRONIX_OCTAL for spi_nor_macronix_octal_dtr_enable function. v2: add ret checking for write enable in spi_nor_macronix_octal_dtr_enable function. JaimeLiao (4): mtd: spi-nor: macronix: add support for Macronix Octal mtd: spi-nor-core: Adding different type of command extension in Soft Reset mtd: spi-nor-core: set 4byte opcode when possible mtd: spi-nor-core: Add support for Macronix Octal flash drivers/mtd/spi/Kconfig | 13 +++++ drivers/mtd/spi/spi-nor-core.c | 94 +++++++++++++++++++++++++++++++++- drivers/mtd/spi/spi-nor-ids.c | 22 +++++++- include/linux/mtd/spi-nor.h | 13 ++++- 4 files changed, 138 insertions(+), 4 deletions(-) -- 2.17.1

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[PATCH 1/8] arm: socfpga: vining: Drop meaningless comment
by Marek Vasut 27 Sep '21

27 Sep '21

The comment is no longer meaningful due to DT conversion, drop it. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Tien Fong Chee <tien.fong.chee(a)intel.com> --- include/configs/socfpga_vining_fpga.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 06976d804c7..38a77535893 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -17,8 +17,6 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* Extra Environment */ #define CONFIG_HOSTNAME "socfpga_vining_fpga" -- 2.33.0

2 15

DM_VIDEO migration
by Simon Glass 26 Sep '21

26 Sep '21

Hi Anatolij, It looks like it is well past time to complete the DM_VIDEO migration and drop the old code. There are still a few drivers left. Are you looking at this? I could perhaps send an initial patch to remove a few. Regards, Simon

3 5

[PATCH 00/12] dm: Expand of-platdata support to GPIOs and clean up
by Simon Glass 26 Sep '21

26 Sep '21

The of-platdata feature allows driver model to be used in SPL without the overhead of a devicetree. The relevant parts of the devicetree are converted to C by the dtoc tool. So far of-platdata supports various drivers but not enough to support the am335x boards. This series adds GPIO support to of-platdata, via a gpio_request_by_phandle() function which looks up GPIOs from the of-platdata information. It also tidies up the existing clock support and finishes off irq support. Finally it includes a new OF_REAL symbol to control whether a devicetree is actually available at runtime. This allows some simplification of the #ifdef logic. For am335x, the cpsw driver uses several devicetree subnodes. For this to work with dtoc it needs to be converted to separate drivers for each subnode, each with a compatible string. Simon Glass (12): treewide: fdt: Move fdt_get_config_... to ofnode_conf_read... fdt: Create a new OF_REAL Kconfig treewide: Simply conditions with the new OF_REAL treewide: Use OF_REAL instead of !OF_PLATDATA mmc: nds32: ftsdc010: Convert to livetree treewide: Try to avoid the preprocessor with OF_REAL fdt: Update Makefile rules with the new OF_REAL Kconfig dm: Add comments to dt-structs contents clk: Rename clk_get_by_driver_info() dm: doc: Add a note about of-platdata header files irq: Tidy up of-platdata irq support dm: gpio: Add of-platdata support Makefile | 7 +- arch/arm/mach-rockchip/rk3188/rk3188.c | 4 +- arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 2 +- arch/arm/mach-rockchip/rk3568/syscon_rk3568.c | 2 +- arch/sandbox/dts/sandbox.dtsi | 21 +++++- arch/sandbox/dts/test.dts | 3 + arch/sandbox/include/asm/irq.h | 20 ++++++ arch/x86/cpu/apollolake/hostbridge.c | 4 +- arch/x86/cpu/apollolake/lpc.c | 2 +- arch/x86/cpu/apollolake/pch.c | 2 +- arch/x86/cpu/apollolake/pmc.c | 4 +- arch/x86/cpu/apollolake/uart.c | 2 +- arch/x86/cpu/coreboot/coreboot.c | 5 +- arch/x86/cpu/intel_common/itss.c | 2 +- arch/x86/cpu/intel_common/p2sb.c | 24 +++---- arch/x86/lib/lpc-uclass.c | 2 +- arch/x86/lib/tpl.c | 2 +- board/dhelectronics/dh_stm32mp1/board.c | 5 +- board/firefly/firefly-rk3288/firefly-rk3288.c | 4 +- board/google/chromebook_coral/coral.c | 2 +- board/sandbox/sandbox.c | 5 +- board/st/stm32mp1/stm32mp1.c | 5 +- common/autoboot.c | 8 +-- common/board_r.c | 4 +- common/cli.c | 7 +- common/spl/spl.c | 2 +- common/spl/spl_spi.c | 12 ++-- configs/sandbox_noinst_defconfig | 2 + configs/sandbox_spl_defconfig | 2 + disk/part_efi.c | 8 +-- doc/develop/driver-model/of-plat.rst | 32 +++++++-- doc/device-tree-bindings/config.txt | 4 +- drivers/clk/clk-uclass.c | 15 ++-- drivers/clk/clk_fixed_factor.c | 18 ++--- drivers/clk/clk_fixed_rate.c | 7 +- drivers/clk/rockchip/clk_px30.c | 4 +- drivers/clk/rockchip/clk_rk3188.c | 8 +-- drivers/clk/rockchip/clk_rk3288.c | 10 +-- drivers/clk/rockchip/clk_rk3308.c | 4 +- drivers/clk/rockchip/clk_rk3368.c | 10 +-- drivers/clk/rockchip/clk_rk3399.c | 20 +++--- drivers/core/device.c | 4 +- drivers/core/fdtaddr.c | 2 +- drivers/core/lists.c | 2 +- drivers/core/ofnode.c | 33 +++++++++ drivers/core/root.c | 4 +- drivers/core/simple-bus.c | 2 +- drivers/core/syscon-uclass.c | 2 +- drivers/core/uclass.c | 2 +- drivers/core/util.c | 2 +- drivers/firmware/firmware-uclass.c | 2 +- drivers/gpio/Makefile | 4 +- drivers/gpio/gpio-uclass.c | 28 +++++++- drivers/gpio/intel_gpio.c | 2 +- drivers/gpio/mxs_gpio.c | 4 +- drivers/gpio/omap_gpio.c | 4 +- drivers/gpio/sandbox.c | 14 ++-- drivers/gpio/sandbox_test.c | 21 ++++++ drivers/i2c/i2c-emul-uclass.c | 2 +- drivers/i2c/i2c-uclass.c | 10 +-- drivers/i2c/omap24xx_i2c.c | 4 +- drivers/misc/Makefile | 2 +- drivers/misc/cros_ec.c | 2 +- drivers/misc/irq-uclass.c | 10 ++- drivers/misc/irq_sandbox.c | 15 +--- drivers/misc/irq_sandbox_test.c | 22 ++++++ drivers/misc/misc-uclass.c | 2 +- drivers/misc/p2sb-uclass.c | 20 +++--- drivers/mmc/fsl_esdhc_imx.c | 17 ++--- drivers/mmc/ftsdc010_mci.c | 45 ++++++------ drivers/mmc/mxsmmc.c | 4 +- drivers/mmc/omap_hsmmc.c | 6 +- drivers/mmc/rockchip_dw_mmc.c | 8 ++- drivers/mmc/rockchip_sdhci.c | 14 ++-- drivers/pch/pch-uclass.c | 2 +- drivers/pinctrl/intel/pinctrl_apl.c | 4 +- drivers/pinctrl/nxp/pinctrl-mxs.c | 2 +- drivers/pinctrl/pinctrl-qe-io.c | 2 +- drivers/pinctrl/pinctrl-uclass.c | 2 +- drivers/pinctrl/rockchip/pinctrl-px30.c | 2 +- drivers/pinctrl/rockchip/pinctrl-rk3036.c | 2 +- drivers/pinctrl/rockchip/pinctrl-rk3128.c | 2 +- drivers/pinctrl/rockchip/pinctrl-rk3188.c | 2 +- drivers/pinctrl/rockchip/pinctrl-rk322x.c | 2 +- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 2 +- drivers/pinctrl/rockchip/pinctrl-rk3308.c | 2 +- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 2 +- drivers/pinctrl/rockchip/pinctrl-rk3368.c | 2 +- drivers/pinctrl/rockchip/pinctrl-rk3399.c | 2 +- drivers/pinctrl/rockchip/pinctrl-rv1108.c | 2 +- drivers/power/domain/power-domain-uclass.c | 4 +- drivers/ram/rockchip/dmc-rk3368.c | 12 ++-- drivers/ram/rockchip/sdram_rk3188.c | 5 +- drivers/ram/rockchip/sdram_rk322x.c | 5 +- drivers/ram/rockchip/sdram_rk3288.c | 5 +- drivers/ram/rockchip/sdram_rk3328.c | 4 +- drivers/ram/rockchip/sdram_rk3399.c | 9 +-- drivers/rtc/rtc-uclass.c | 2 +- drivers/serial/ns16550.c | 8 +-- drivers/serial/sandbox.c | 2 +- drivers/serial/serial_mt7620.c | 4 +- drivers/serial/serial_omap.c | 6 +- drivers/spi/cf_spi.c | 4 +- drivers/spi/davinci_spi.c | 4 +- drivers/spi/fsl_espi.c | 4 +- drivers/spi/ich.c | 6 +- drivers/spi/mxs_spi.c | 4 +- drivers/spi/omap3_spi.c | 4 +- drivers/spi/pl022_spi.c | 4 +- drivers/spi/rk_spi.c | 38 +++++------ drivers/spi/spi-uclass.c | 14 ++-- drivers/sysreset/sysreset_sandbox.c | 2 +- drivers/timer/rockchip_timer.c | 16 ++--- drivers/timer/timer-uclass.c | 68 ++++++++++--------- drivers/timer/tsc_timer.c | 2 +- drivers/tpm/tpm-uclass.c | 2 +- drivers/video/cfb_console.c | 4 +- drivers/video/exynos/exynos_mipi_dsi.c | 4 +- drivers/watchdog/wdt-uclass.c | 2 +- dts/Kconfig | 29 +++++++- env/mmc.c | 5 +- include/asm-generic/gpio.h | 5 ++ include/clk.h | 35 ++++++++-- include/dm/device.h | 12 ++-- include/dm/ofnode.h | 37 ++++++++++ include/dt-structs.h | 27 ++++++++ include/fdtdec.h | 33 --------- include/irq.h | 29 ++++++++ include/power-domain.h | 6 +- lib/Makefile | 5 +- lib/fdtdec.c | 44 ------------ scripts/Makefile.spl | 9 +-- test/dm/of_platdata.c | 65 ++++++++++++++++-- test/dm/ofnode.c | 15 ++++ tools/dtoc/dtb_platdata.py | 1 + 135 files changed, 783 insertions(+), 477 deletions(-) create mode 100644 arch/sandbox/include/asm/irq.h create mode 100644 drivers/gpio/sandbox_test.c create mode 100644 drivers/misc/irq_sandbox_test.c -- 2.32.0.605.g8dce9f2422-goog

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[PATCH u-boot] dm: pci: Fix handling of errors when scanning device
by Marek Behún 26 Sep '21

26 Sep '21

From: Pali Rohár <pali(a)kernel.org> Some PCIe controller's read_config() method support indicating error directly via return value, but some cannot distinguish all-ones (or all-zeros) read response from an error. The current code in pci_bind_bus_devices() interprets all-ones / all-zeros in PCI_VENDOR_ID register as "nothing connected", and continues the cycle, but an error returned via return value breaks the cycle. This is wrong for the PCIe controllers which return this error via return value. Handle all errors when reading PCI_VENDOR_ID the same way. This fixes enumeration of PCI devices for example when there is a PCI bridge connected behind another PCI bridge and not all ports are connected to a device, and the controller (for example Aardvark) translates the UR error (Unsupported Request) as -EOPNOTSUPP. Signed-off-by: Pali Rohár <pali(a)kernel.org> Signed-off-by: Marek Behún <marek.behun(a)nic.cz> --- drivers/pci/pci-uclass.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index ce2eb5da2c..4d0e938fe5 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -856,10 +856,7 @@ int pci_bind_bus_devices(struct udevice *bus) /* Check only the first access, we don't expect problems */ ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor, PCI_SIZE_16); - if (ret) - goto error; - - if (vendor == 0xffff || vendor == 0x0000) + if (ret || vendor == 0xffff || vendor == 0x0000) continue; pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE, @@ -940,10 +937,6 @@ int pci_bind_bus_devices(struct udevice *bus) } return 0; -error: - printf("Cannot read bus configuration: %d\n", ret); - - return ret; } static void decode_regions(struct pci_controller *hose, ofnode parent_node, -- 2.32.0

6 6

[PATCH] fdt_support.h: Remove duplicated declarations
by Bin Meng 26 Sep '21

26 Sep '21

There are two duplicated declarations for ft_cpu_setup() and ft_pci_setup(). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- include/fdt_support.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/fdt_support.h b/include/fdt_support.h index f6f46bb8e9..72a5b90c97 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -203,8 +203,6 @@ char *board_fdt_chosen_bootargs(void); * called at the end of the image_setup_libfdt() is to do that convertion. */ void ft_board_setup_ex(void *blob, struct bd_info *bd); -void ft_cpu_setup(void *blob, struct bd_info *bd); -void ft_pci_setup(void *blob, struct bd_info *bd); /** * Add system-specific data to the FDT before booting the OS. -- 2.25.1

3 2

[PATCH] fs: fat: check for buffer size before reading blocks
by Oleksandr Suvorov 26 Sep '21

26 Sep '21

From: Ricardo Salveti <ricardo(a)foundries.io> This patch optimizes the commit mentioned below by avoiding running a set of commands which useless in the case when size < mydata->sect_size and idx would be 0. Fixes: 5b3ddb17ba ("fs/fat/fat.c: Do not perform zero block reads if there are no blocks left") Signed-off-by: Ricardo Salveti <ricardo(a)foundries.io> Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov(a)foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov(a)foundries.io> --- fs/fat/fat.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 7021138b987..4a509755442 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -275,14 +275,10 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) buffer += mydata->sect_size; size -= mydata->sect_size; } - } else { + } else if (size >= mydata->sect_size) { __u32 idx; - idx = size / mydata->sect_size; - if (idx == 0) - ret = 0; - else - ret = disk_read(startsect, idx, buffer); + ret = disk_read(startsect, idx, buffer); if (ret != idx) { debug("Error reading data (got %d)\n", ret); return -1; -- 2.31.1

3 2

[PATCH 3/6 v2] pinctrl: qcom: add pinctrl and gpio drivers for SDM845 SoC
by dsankouski＠gmail.com 26 Sep '21

26 Sep '21

From: Dzmitry Sankouski <dsankouski(a)gmail.com> Signed-off-by: Dzmitry Sankouski <dsankouski(a)gmail.com> Cc: Ramon Fried <rfried.dev(a)gmail.com> Cc: Tom Rini <trini(a)konsulko.com> Cc: Stephan Gerhold <stephan(a)gerhold.net> --- Changes for v2: - Add __section(".data") for pin_name variable. arch/arm/mach-snapdragon/pinctrl-sdm845.c | 44 +++++++++++++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 + arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 + drivers/gpio/msm_gpio.c | 1 + drivers/gpio/pm8916_gpio.c | 8 ++-- 5 files changed, 52 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-snapdragon/pinctrl-sdm845.c diff --git a/arch/arm/mach-snapdragon/pinctrl-sdm845.c b/arch/arm/mach-snapdragon/pinctrl-sdm845.c new file mode 100644 index 0000000000..40f2f012fa --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-sdm845.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm SDM845 pinctrl + * + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski(a)gmail.com> + * + */ + +#include "pinctrl-snapdragon.h" +#include <common.h> + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"qup9", 1}, + {"gpio", 0}, +}; + +static const char *sdm845_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sdm845_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; +} + +static unsigned int sdm845_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data sdm845_data = { + .pin_count = 150, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sdm845_get_function_name, + .get_function_mux = sdm845_get_function_mux, + .get_pin_name = sdm845_get_pin_name, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index e6b87c3573..c0ed943036 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -116,6 +116,7 @@ static struct pinctrl_ops msm_pinctrl_ops = { static const struct udevice_id msm_pinctrl_ids[] = { { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data }, { .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data }, + { .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data }, { } }; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h index 61d466f4d8..ea524312a0 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h @@ -27,5 +27,6 @@ struct pinctrl_function { extern struct msm_pinctrl_data apq8016_data; extern struct msm_pinctrl_data apq8096_data; +extern struct msm_pinctrl_data sdm845_data; #endif diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index e1ff84c1c0..a3c3cd7824 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -120,6 +120,7 @@ static const struct udevice_id msm_gpio_ids[] = { { .compatible = "qcom,msm8916-pinctrl" }, { .compatible = "qcom,apq8016-pinctrl" }, { .compatible = "qcom,ipq4019-pinctrl" }, + { .compatible = "qcom,sdm845-pinctrl" }, { } }; diff --git a/drivers/gpio/pm8916_gpio.c b/drivers/gpio/pm8916_gpio.c index 40b0f2578b..7ad95784a8 100644 --- a/drivers/gpio/pm8916_gpio.c +++ b/drivers/gpio/pm8916_gpio.c @@ -202,6 +202,7 @@ static int pm8916_gpio_of_to_plat(struct udevice *dev) static const struct udevice_id pm8916_gpio_ids[] = { { .compatible = "qcom,pm8916-gpio" }, { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ + { .compatible = "qcom,pm8998-gpio" }, { } }; @@ -266,7 +267,7 @@ static int pm8941_pwrkey_probe(struct udevice *dev) return log_msg_ret("bad type", -ENXIO); reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE); - if (reg != 0x1) + if ((reg & 0x5) == 0) return log_msg_ret("bad subtype", -ENXIO); return 0; @@ -287,11 +288,12 @@ static int pm8941_pwrkey_of_to_plat(struct udevice *dev) static const struct udevice_id pm8941_pwrkey_ids[] = { { .compatible = "qcom,pm8916-pwrkey" }, { .compatible = "qcom,pm8994-pwrkey" }, + { .compatible = "qcom,pm8998-pwrkey" }, { } }; -U_BOOT_DRIVER(pwrkey_pm8941) = { - .name = "pwrkey_pm8916", +U_BOOT_DRIVER(pwrkey_pm89xx) = { + .name = "pwrkey_pm89xx", .id = UCLASS_GPIO, .of_match = pm8941_pwrkey_ids, .of_to_plat = pm8941_pwrkey_of_to_plat, -- 2.20.1

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Radax failed to boot - how to recover the board.
by Anand Moon 26 Sep '21

26 Sep '21

Hi Kever / Jagan, I have Radxa N10 RK3399pro model B 6 GB ram, (4 GB +2GB NPU). When I tried to boot via micro sd card it booted with stock android u-boot, but this u-boot was not enabled all 4BG memory in total. So I tried to replace the image with the latest u-boot. Now when I flash the u-boot to eMMC (onboard) with the latest u-boot it failed to boot. see below. Please help me recover the board, I cannot reset the board via the reset button or nor is it entering the u-boot command prompt. Please advise me on how to proceed.on recovery off the board? Thanks -Anand As per the Radax wiki page the DRAM 6GB 64bit dual channel LPDDR3@1866Mb/s, So I have modified the code as below. $ git diff arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi index 7c66e1145a..08266bb3ac 100644 --- a/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi +++ b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi @@ -4,7 +4,7 @@ */ #include "rk3399pro-u-boot.dtsi" -#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" Boot failed ...not able to recover the. U-Boot TPL 2021.10-rc4-00055-g8284d6f838-dirty (Sep 26 2021 - 20:29:22) Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256 stride Trying to boot from&{{▒▒{kk Returning to boot ROM... U,Boot SPL 2021.10-rc4-00055-g8284d6f838-dirty (Sep 26 2021 - 20:29:22 +0530) Trying to boot from MMC1 Card did not respond to voltage select! : -110 spl: mmc init failed with error: -95 SPL: failed to boot from all boot deviceC ### ERROR ### Please RESET the board ###

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