September 2021 - U-Boot

[PATCH 0/2] TSEC Ethernet driver phy-mode changes
by Vladimir Oltean 28 Sep '21

28 Sep '21

Make the Freescale/NXP TSEC driver listen to the phy-mode or phy-connection-type OF property. Currently there is an attempt to auto-determine the PHY mode, only do that if the phy-mode string is not specified. Also, be compatible with phy-mode, right now the driver only parses phy-connection-type, both both are equivalent. Vladimir Oltean (2): net: tsec: only call tsec_get_interface as fallback to DT-specified PHY mode net: tsec: read the phy-mode property as fallback to phy-connection-type drivers/net/tsec.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) -- 2.25.1

3 6

[PATCH 0/4] phy-mode cleanup
by Vladimir Oltean 28 Sep '21

28 Sep '21

Michael Walle did an excellent job in starting the process of bringing U-Boot and Linux device tree bindings in sync for the NXP LS1028A: https://patchwork.ozlabs.org/project/uboot/cover/20210902164558.1920849-1-m… but there still are some hairy issues which need to be addressed head on, and which Michael said he'd rather leave for NXP to do, so here we are /shrug/ NXP LS1028A has 2 Ethernet controllers: drivers/net/fsl_enetc.c for the endpoint ports and DSA master drivers/net/mscc_eswitch/felix_switch.c for the switch ports but in fact, the MAC-side Physical Coding Sublayer (PCS) device used for translating the MAC layer data into a serial bit stream is the same kind between the enetc and the switch, as well as the same kind as the PCS used in the other NXP SoCs (those based on DPAA1 and those based on DPAA2). So most of the conclusions we draw about the LS1028A PCS apply equally to the other NXP SoCs from the family. There are 3 general directions in this patch series: - the "sgmii-2500" idea was rejected in Linux due to the inability to explain what it is. Linux has standardized on "2500base-x" as a way to describe both fiber ports and MAC-to-PHY links. Convert the NXP devices to use the phy-mode accepted in Linux. - the "xfi" phy-mode was rejected in Linux because it is an electrical standard covering more than a single SERDES protocol. For Ethernet things were standardized as "10gbase-r" which describes the 64b/66b coding scheme used there (the "R" in 10GBase-R). - the "xgmii" phy-mode is pretty much bogus, there are no NXP devices with this pinout. This pretty much stems from the idea that the device tree should describe an internal set of wires between the MAC and the PCS (the much speculated semantic difference between "phy-mode" and "phy-connection-type"), which it should not. Even though I'm pretty sure that no NXP devices have an external pinout of XGMII, I have only replaced this usage in the LS1028A networking drivers, because I am not completely sure of all the implications my changes would have in the DPAA1 and DPAA2 drivers. Vladimir Oltean (4): net: replace the "xfi" phy-mode with "10gbase-r" net: freescale: replace usage of phy-mode = "sgmii-2500" with "2500base-x" net: enetc: remove support for "xgmii" phy-mode net: dsa: felix: remove "xgmii" phy-mode arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- .../cpu/armv8/fsl-layerscape/doc/README.soc | 8 +++---- .../cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 2 +- .../dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi | 2 +- .../dts/fsl-ls1028a-qds-7777-sch-30841.dtsi | 8 +++---- .../dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi | 4 ++-- .../dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi | 2 +- .../dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi | 2 +- arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi | 4 ++-- arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi | 4 ++-- arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi | 16 +++++++------- arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 16 +++++++------- arch/arm/dts/fsl-sch-30841.dtsi | 2 +- arch/arm/dts/fsl-sch-30842.dtsi | 2 +- board/Marvell/octeon_ebb7304/board.c | 6 ++--- board/freescale/ls1012aqds/eth.c | 4 ++-- board/freescale/ls1012aqds/ls1012aqds.c | 4 ++-- board/freescale/ls1012aqds/ls1012aqds_pfe.h | 2 +- board/freescale/ls1012ardb/eth.c | 4 ++-- board/freescale/ls1043aqds/README | 2 +- board/freescale/ls1043aqds/eth.c | 12 +++++----- board/freescale/ls1043ardb/README | 2 +- board/freescale/ls1043ardb/eth.c | 2 +- board/freescale/ls1046aqds/README | 2 +- board/freescale/ls1046aqds/eth.c | 8 +++---- board/freescale/ls1046ardb/README | 4 ++-- board/freescale/ls1046ardb/eth.c | 2 +- board/freescale/ls1088a/README | 4 ++-- board/freescale/ls1088a/eth_ls1088ardb.c | 6 ++--- board/freescale/ls2080aqds/README | 2 +- board/freescale/ls2080aqds/eth.c | 13 +++++------ board/freescale/ls2080ardb/README | 2 +- board/freescale/t102xrdb/README | 2 +- board/freescale/t102xrdb/eth_t102xrdb.c | 8 +++---- board/freescale/t208xqds/README | 18 +++++++-------- board/freescale/t208xqds/eth_t208xqds.c | 22 +++++++++---------- board/freescale/t208xqds/t208xqds.c | 8 +++---- board/freescale/t208xrdb/README | 4 ++-- board/freescale/t4rdb/eth.c | 2 +- doc/device-tree-bindings/net/ethernet.txt | 12 +++++++++- drivers/net/fm/b4860.c | 2 +- drivers/net/fm/eth.c | 10 ++++----- drivers/net/fm/ls1043.c | 4 ++-- drivers/net/fm/ls1046.c | 2 +- drivers/net/fm/memac.c | 6 ++--- drivers/net/fm/t1024.c | 2 +- drivers/net/fsl_enetc.c | 10 ++++----- drivers/net/mscc_eswitch/felix_switch.c | 7 +++--- drivers/net/pfe_eth/pfe_mdio.c | 4 ++-- drivers/net/phy/aquantia.c | 18 +++++++-------- include/phy.h | 2 +- include/phy_interface.h | 4 ++-- 52 files changed, 154 insertions(+), 148 deletions(-) -- 2.25.1

2 8

[PATCH] net: phy: genphy_init can be static
by Vladimir Oltean 28 Sep '21

28 Sep '21

To avoid a warning with W=1 about this function not having a previous prototype, declare it as static, because it is not used outside of this translation module. Signed-off-by: Vladimir Oltean <vladimir.oltean(a)nxp.com> --- drivers/net/phy/phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 69acb6946061..c9fc20855ba1 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -463,7 +463,7 @@ static struct phy_driver genphy_driver = { .shutdown = genphy_shutdown, }; -int genphy_init(void) +static int genphy_init(void) { return phy_register(&genphy_driver); } -- 2.25.1

3 2

[PATCH] board: ti: Add support for the AM335x GP EVM mini board
by Amjad Ouled-Ameur 28 Sep '21

28 Sep '21

From: Andreas Dannenberg <dannenberg(a)ti.com> This is not really a new board but rather a minimal bootloader solution for the AM335x GP EVM. In terms of interfaces, it only supports booting from MMC0 or UART0 and only activates a minimal set of drivers that are that are necessary to run the device such as DDR, I2C, and PMIC. The goal is to provide a bare minimum starting point to boot Linux for basing custom board-ports on. The limited complexity of this solution should make it easier to achieve a successful boot to U-Boot prompt vs. trying to pair down the full-featured multi-platform AM335x U-Boot available through am335x_evm_defconfig. Signed-off-by: Andreas Dannenberg <dannenberg(a)ti.com> [Amjad: fix checkpatch and compile warnings] Signed-off-by: Amjad Ouled-Ameur <aouledameur(a)baylibre.com> --- Tests: - This has been tested on Am335x platform, the board boots successfully to u-boot prompt and runs basic commands seamlessly, please find the logs here: [0] However, regarding the kernel boot test, this patch does not actually guaranteey that since its purpose is to mainly allow the user to achieve a successful boot to U-boot prompt. [0]: https://pastebin.com/ixQ2yB9n MAINTAINERS | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/am335x-bone-common.dtsi | 1 + arch/arm/dts/am335x-evm-mini.dts | 166 ++++++++++++++++++ arch/arm/mach-omap2/am33xx/Kconfig | 30 ++++ board/ti/am335x/Kconfig | 13 +- board/ti/am335x/Makefile | 6 +- board/ti/am335x/board_hs_mini.h | 19 ++ board/ti/am335x/board_mini.c | 249 +++++++++++++++++++++++++++ board/ti/am335x/board_mini.h | 44 +++++ board/ti/am335x/mux_mini.c | 109 ++++++++++++ configs/am335x_evm_mini_defconfig | 42 +++++ configs/am335x_hs_evm_mini_defconfig | 46 +++++ include/configs/am335x_evm_mini.h | 96 +++++++++++ 14 files changed, 820 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/am335x-evm-mini.dts create mode 100644 board/ti/am335x/board_hs_mini.h create mode 100644 board/ti/am335x/board_mini.c create mode 100644 board/ti/am335x/board_mini.h create mode 100644 board/ti/am335x/mux_mini.c create mode 100644 configs/am335x_evm_mini_defconfig create mode 100644 configs/am335x_hs_evm_mini_defconfig create mode 100644 include/configs/am335x_evm_mini.h diff --git a/MAINTAINERS b/MAINTAINERS index 5370b550648e..09b942acd109 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -492,6 +492,7 @@ F: arch/arm/mach-keystone/ F: arch/arm/mach-omap2/ F: arch/arm/include/asm/arch-omap*/ F: arch/arm/include/asm/ti-common/ +F: arch/arm/dts/am335x* F: board/ti/ F: drivers/dma/ti* F: drivers/firmware/ti_sci.* diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fc16a57e60b0..faf8f438bf29 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -360,6 +360,7 @@ dtb-$(CONFIG_AM33XX) += \ am335x-brsmarc1.dtb \ am335x-draco.dtb \ am335x-evm.dtb \ + am335x-evm-mini.dtb \ am335x-evmsk.dtb \ am335x-bonegreen.dtb \ am335x-icev2.dtb \ diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi index 35ec1a8df870..a87558686709 100644 --- a/arch/arm/dts/am335x-bone-common.dtsi +++ b/arch/arm/dts/am335x-bone-common.dtsi @@ -211,6 +211,7 @@ tps: tps@24 { reg = <0x24>; + #interrupt-cells = <1>; }; baseboard_eeprom: baseboard_eeprom@50 { diff --git a/arch/arm/dts/am335x-evm-mini.dts b/arch/arm/dts/am335x-evm-mini.dts new file mode 100644 index 000000000000..f45da0fd3f6f --- /dev/null +++ b/arch/arm/dts/am335x-evm-mini.dts @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "TI AM335x EVM MINI"; + compatible = "ti,am335x-evm-mini", "ti,am335x-evm", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&am33xx_pinmux { + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; +}; + +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 4268419b166b..296559a00c15 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -63,6 +63,36 @@ config TARGET_AM335X_EVM to write software and develop hardware around an AM335x processor subsystem. +config TARGET_AM335X_EVM_MINI + bool "Support am335x_evm_mini" + select BOARD_LATE_INIT + select DM + select DM_GPIO + select DM_SERIAL + imply CMD_DM + imply SPL_DM + imply SPL_DM_SEQ_ALIAS + imply SPL_ENV_SUPPORT + imply SPL_FS_EXT4 + imply SPL_FS_FAT + imply SPL_GPIO_SUPPORT + imply SPL_I2C_SUPPORT + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_MMC_SUPPORT + imply SPL_OF_LIBFDT + imply SPL_POWER_SUPPORT + imply SPL_SEPARATE_BSS + imply SPL_SERIAL_SUPPORT + imply SPL_SYS_MALLOC_SIMPLE + imply SPL_YMODEM_SUPPORT + help + This option specifies support for the AM335x + GP and HS EVM development platforms using a minimal + system configuration, only supporting a small subset + of boot media and other features. + config TARGET_AM335X_BALTOS bool "Support am335x_baltos" select BOARD_LATE_INIT diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig index b66ca1a57982..333fce9caa59 100644 --- a/board/ti/am335x/Kconfig +++ b/board/ti/am335x/Kconfig @@ -1,4 +1,4 @@ -if TARGET_AM335X_EVM +if TARGET_AM335X_EVM || TARGET_AM335X_EVM_MINI config SYS_BOARD default "am335x" @@ -9,9 +9,20 @@ config SYS_VENDOR config SYS_SOC default "am33xx" +if TARGET_AM335X_EVM + config SYS_CONFIG_NAME default "am335x_evm" +endif + +if TARGET_AM335X_EVM_MINI + +config SYS_CONFIG_NAME + default "am335x_evm_mini" + +endif + config NOR bool "Support for NOR flash" help diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile index c34b9b1dd8a7..7b424734095a 100644 --- a/board/ti/am335x/Makefile +++ b/board/ti/am335x/Makefile @@ -5,7 +5,9 @@ # Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) -obj-y := mux.o +obj-$(CONFIG_TARGET_AM335X_EVM) := mux.o +obj-$(CONFIG_TARGET_AM335X_EVM_MINI) := mux_mini.o endif -obj-y += board.o +obj-$(CONFIG_TARGET_AM335X_EVM) += board.o +obj-$(CONFIG_TARGET_AM335X_EVM_MINI) += board_mini.o diff --git a/board/ti/am335x/board_hs_mini.h b/board/ti/am335x/board_hs_mini.h new file mode 100644 index 000000000000..e03ba141f286 --- /dev/null +++ b/board/ti/am335x/board_hs_mini.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * TI AM437x boards information header + * Derived from AM335x board. + * + * Copyright (C) 2020, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _BOARD_HS_H_ +#define _BOARD_HS_H_ + +#ifdef CONFIG_TI_SECURE_DEVICE +void board_fit_image_post_process(void **p_image, size_t *p_size) +{ + secure_boot_verify_image(p_image, p_size); +} +#endif + +#endif diff --git a/board/ti/am335x/board_mini.c b/board/ti/am335x/board_mini.c new file mode 100644 index 000000000000..94f0a2910be3 --- /dev/null +++ b/board/ti/am335x/board_mini.c @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Mini board functions for TI AM335X based boards + * + * Copyright (C) 2020, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <dm.h> +#include <env.h> +#include <errno.h> +#include <init.h> +#include <spl.h> +#include <serial.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/omap_common.h> +#include <asm/omap_sec_common.h> +#include <asm/omap_mmc.h> +#include <i2c.h> +#include <power/tps65910.h> +#include <env_internal.h> +#include <watchdog.h> +#include "board_mini.h" +#include "board_hs_mini.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct serial_device *default_serial_console(void) +{ + return &eserial1_device; +} + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static const struct ddr_data ddr3_evm_data = { + .datardsratio0 = MT41J512M8RH125_RD_DQS, + .datawdsratio0 = MT41J512M8RH125_WR_DQS, + .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, + .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_evm_cmd_ctrl_data = { + .cmd0csratio = MT41J512M8RH125_RATIO, + .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, + + .cmd1csratio = MT41J512M8RH125_RATIO, + .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, + + .cmd2csratio = MT41J512M8RH125_RATIO, + .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_evm_emif_reg_data = { + .sdram_config = MT41J512M8RH125_EMIF_SDCFG, + .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, + .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, + .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, + .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, + .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM, + .zq_config = MT41J512M8RH125_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + int ind = get_sys_clk_index(); + + return &dpll_ddr3_303MHz[ind]; +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + int ind = get_sys_clk_index(); + int freq = am335x_get_efuse_mpu_max_freq(cdev); + + switch (freq) { + case MPUPLL_M_1000: + return &dpll_mpu_opp[ind][5]; + case MPUPLL_M_800: + return &dpll_mpu_opp[ind][4]; + case MPUPLL_M_720: + return &dpll_mpu_opp[ind][3]; + case MPUPLL_M_600: + return &dpll_mpu_opp[ind][2]; + case MPUPLL_M_500: + return &dpll_mpu_opp100; + case MPUPLL_M_300: + return &dpll_mpu_opp[ind][0]; + } + + return &dpll_mpu_opp[ind][0]; +} + +void scale_vcores_generic(int freq) +{ + int sil_rev, mpu_vdd; + + /* + * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all + * MPU frequencies we support we use a CORE voltage of + * 1.10V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ + + if (IS_ENABLED(CONFIG_DM_I2C)) { + if (power_tps65910_init(0)) + return; + } else { + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) + return; + } + + /* + * Depending on MPU clock and PG we will need a different + * VDD to drive at that speed. + */ + sil_rev = readl(&cdev->deviceid) >> 28; + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq); + + /* Tell the TPS65910 to use i2c */ + tps65910_set_i2c_control(); + + /* First update MPU voltage. */ + if (tps65910_voltage_update(MPU, mpu_vdd)) + return; + + /* Second, update the CORE voltage. */ + if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0)) + return; +} + +void gpi2c_init(void) +{ + /* When needed to be invoked prior to BSS initialization */ + static bool first_time = true; + + if (first_time) { + enable_i2c0_pin_mux(); + if (!IS_ENABLED(CONFIG_DM_I2C)) + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE); + first_time = false; + } +} + +void scale_vcores(void) +{ + int freq; + + gpi2c_init(); + freq = am335x_get_efuse_mpu_max_freq(cdev); + scale_vcores_generic(freq); +} + +void set_uart_mux_conf(void) +{ + if (CONFIG_CONS_INDEX == 1) + enable_uart0_pin_mux(); + else if (CONFIG_CONS_INDEX == 2) + enable_uart1_pin_mux(); + else if (CONFIG_CONS_INDEX == 3) + enable_uart2_pin_mux(); + else if (CONFIG_CONS_INDEX == 4) + enable_uart3_pin_mux(); + else if (CONFIG_CONS_INDEX == 5) + enable_uart4_pin_mux(); + else if (CONFIG_CONS_INDEX == 6) + enable_uart5_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +const struct ctrl_ioregs ioregs_evm15 = { + .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, + .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + /* Configure for AM335x GP EVM v1.5 or later */ + config_ddr(303, &ioregs_evm15, &ddr3_evm_data, + &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); +} + +int ft_board_setup(void *fdt, struct bd_info **bd) +{ + return 0; +} + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + env_set("board_name", CONFIG_SYS_BOARD); + + /* + * Default FIT boot on HS devices. Non FIT images are not allowed + * on HS devices. + */ + if (get_device_type() == HS_DEVICE) + env_set("boot_fit", "1"); + } + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + return 0; +} + +static const struct omap_hsmmc_plat am335x_mmc0_platdata = { + .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE, + .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT, + .cfg.f_min = 400000, + .cfg.f_max = 52000000, + .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, + .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + +U_BOOT_DRVINFO(am335x_mmc0) = { + .name = "omap_hsmmc", + .plat = &am335x_mmc0_platdata, +}; diff --git a/board/ti/am335x/board_mini.h b/board/ti/am335x/board_mini.h new file mode 100644 index 000000000000..0fa1a8680027 --- /dev/null +++ b/board/ti/am335x/board_mini.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Mini AM335x boards information header + * + * Copyright (C) 2020, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/** + * AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and + * REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame + * Synchronization Lost errors. The values are the biggest that work + * reliably with offered video modes and the memory subsystem on the + * boards. These register have are briefly documented in "7.3.3.5.2 + * Command Starvation" section of AM335x TRM. The REG_COS_COUNT_1 and + * REG_COS_COUNT_2 do not have any effect on current versions of + * AM335x. + */ +#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK 0x00141414 +#define EMIF_OCP_CONFIG_AM335X_EVM 0x003d3d3d + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); + +#ifdef CONFIG_DM_I2C +#define i2c_init(speed, slaveaddr) +#define i2c_probe(chip) (NULL) +#endif + +#endif diff --git a/board/ti/am335x/mux_mini.c b/board/ti/am335x/mux_mini.c new file mode 100644 index 000000000000..b724198b9cdf --- /dev/null +++ b/board/ti/am335x/mux_mini.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board_mini.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ + {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ + {OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_6 */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_uart5_pin_mux(void) +{ + configure_module_pin_mux(uart5_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + /* Do board-specific muxes */ + configure_module_pin_mux(mmc0_pin_mux); +} diff --git a/configs/am335x_evm_mini_defconfig b/configs/am335x_evm_mini_defconfig new file mode 100644 index 000000000000..087d64d742d3 --- /dev/null +++ b/configs/am335x_evm_mini_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_COMMON_CMD_OPTIONS=y +CONFIG_DEFAULT_DEVICE_TREE="am335x-evm-mini" +CONFIG_AM33XX=y +CONFIG_TARGET_AM335X_EVM_MINI=y +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd" +CONFIG_LOGLEVEL=3 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_FIT_IMAGE_TINY=y +# CONFIG_SPL_FS_EXT4 is not set +CONFIG_SPL_I2C=y +# CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_POWER=y +# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set +CONFIG_CMD_SPL=y +# CONFIG_CMD_EEPROM is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_ENV_IS_NOWHERE=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_NET is not set +CONFIG_DM_I2C=y +CONFIG_MISC=y +# CONFIG_MMC_HW_PARTITIONING is not set +CONFIG_MMC_OMAP_HS=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_DYNAMIC_CRC_TABLE=y +CONFIG_RSA=y +CONFIG_LZO=y +# CONFIG_OF_LIBFDT_OVERLAY is not set diff --git a/configs/am335x_hs_evm_mini_defconfig b/configs/am335x_hs_evm_mini_defconfig new file mode 100644 index 000000000000..fe61d31e8bfc --- /dev/null +++ b/configs/am335x_hs_evm_mini_defconfig @@ -0,0 +1,46 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_ISW_ENTRY_ADDR=0x40300350 +CONFIG_TI_COMMON_CMD_OPTIONS=y +CONFIG_DEFAULT_DEVICE_TREE="am335x-evm-mini" +CONFIG_AM33XX=y +CONFIG_TARGET_AM335X_EVM_MINI=y +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd" +CONFIG_LOGLEVEL=3 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_FIT_IMAGE_TINY=y +# CONFIG_SPL_FS_EXT4 is not set +CONFIG_SPL_I2C=y +# CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_POWER=y +# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set +CONFIG_CMD_SPL=y +# CONFIG_CMD_EEPROM is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_ENV_IS_NOWHERE=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_NET is not set +CONFIG_DM_I2C=y +CONFIG_MISC=y +# CONFIG_MMC_HW_PARTITIONING is not set +CONFIG_MMC_OMAP_HS=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_DYNAMIC_CRC_TABLE=y +CONFIG_RSA=y +CONFIG_LZO=y +# CONFIG_OF_LIBFDT_OVERLAY is not set diff --git a/include/configs/am335x_evm_mini.h b/include/configs/am335x_evm_mini.h new file mode 100644 index 000000000000..f4c8dfe78e1a --- /dev/null +++ b/include/configs/am335x_evm_mini.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __CONFIG_AM335X_EVM_MINI_H +#define __CONFIG_AM335X_EVM_MINI_H + +#include <configs/ti_am335x_common.h> +#include <linux/sizes.h> + +#ifndef CONFIG_SPL_BUILD +# define CONFIG_TIMESTAMP +#endif + +#define CONFIG_SYS_BOOTM_LEN SZ_16M + +#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance "; "\ + "setenv bootpart " #instance ":2 ; "\ + "run mmcboot\0" + +#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) + +#include <config_distro_bootcmd.h> + +#ifndef CONFIG_SPL_BUILD +#include <environment/ti/mmc.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_FIT_TI_ARGS \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=undefined\0" \ + "console=ttyS0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=bootloader,start=384K,size=1792K," \ + "uuid=${uuid_gpt_bootloader};" \ + "name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \ + "optargs=\0" \ + "ramroot=/dev/ram0 rw\0" \ + "ramrootfstype=ext2\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ + "default_device_tree=am335x-evm.dtb\0" \ + "findfdt=" \ + "setenv name_fdt ${default_device_tree};" \ + "setenv fdtfile ${name_fdt}\0" \ + "init_console=" \ + "setenv console ttyS0,115200n8\0" \ + BOOTENV +#endif + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ + +/* PMIC support */ +#define CONFIG_POWER_TPS65910 + +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_MMC +#undef CONFIG_TIMER +#endif + +#endif /* ! __CONFIG_AM335X_EVM_MINI_H */ -- 2.25.1

2 1

[PATCH v2] cmd: ubi: add a command to swap volumes
by Ayoub Zaki 28 Sep '21

28 Sep '21

This commit adds the command ubi swap to swap an ubi volumes. The format of the command is: ubi swap <volume_a> <volume_b>. To enable this command, the option CMD_UBI_SWAPVOL must be selected. --- cmd/Kconfig | 8 ++++++++ cmd/ubi.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index ffef3cc76c..ae0edc9cb1 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -2381,6 +2381,14 @@ config CMD_UBI_RENAME Enable a "ubi" command to rename ubi volume: ubi rename <oldname> <newname> +config CMD_UBI_SWAPVOL + bool "Enable swap volumes" + depends on CMD_UBI + default n + help + Enable a "ubi" command to swap ubi volumes: + ubi swap <volume_a> <volume_b> + config CMD_UBIFS tristate "Enable UBIFS - Unsorted block images filesystem commands" depends on CMD_UBI diff --git a/cmd/ubi.c b/cmd/ubi.c index fe8ac58bac..43cb3c26a2 100644 --- a/cmd/ubi.c +++ b/cmd/ubi.c @@ -289,6 +289,54 @@ static int ubi_rename_vol(char *oldname, char *newname) return ubi_rename_volumes(ubi, &list); } +static int ubi_swap_vol(char *volume_a, char *volume_b) +{ + struct ubi_volume *vol_a, *vol_b; + struct ubi_rename_entry a, b; + struct ubi_volume_desc desc_a, desc_b; + struct list_head list; + + vol_a = ubi_find_volume(volume_a); + if (!vol_a) { + printf("%s: volume %s doesn't exist\n", __func__, volume_a); + return ENODEV; + } + + vol_b = ubi_find_volume(volume_b); + if (!vol_b) { + printf("%s: volume %s doesn't exist\n", __func__, volume_a); + return ENODEV; + } + + printf("Swap UBI volumes: %s - %s\n", volume_a, volume_b); + + if (ubi->ro_mode) { + printf("%s: ubi device is in read-only mode\n", __func__); + return EROFS; + } + + a.new_name_len = strlen(volume_a); + strcpy(a.new_name, volume_a); + a.remove = 0; + desc_a.vol = vol_b; + desc_a.mode = 0; + a.desc = &desc_a; + + b.new_name_len = strlen(volume_b); + strcpy(b.new_name, volume_b); + b.remove = 0; + desc_b.vol = vol_a; + desc_b.mode = 0; + b.desc = &desc_b; + + INIT_LIST_HEAD(&a.list); + INIT_LIST_HEAD(&b.list); + INIT_LIST_HEAD(&list); + list_add(&a.list, &list); + list_add(&b.list, &list); + return ubi_rename_volumes(ubi, &list); +} + static int ubi_volume_continue_write(char *volume, void *buf, size_t size) { int err = 1; @@ -645,6 +693,9 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (IS_ENABLED(CONFIG_CMD_UBI_RENAME) && !strncmp(argv[1], "rename", 6)) return ubi_rename_vol(argv[2], argv[3]); + if (IS_ENABLED(CONFIG_CMD_UBI_SWAPVOL) && !strncmp(argv[1], "swap", 4)) + return ubi_swap_vol(argv[2], argv[3]); + if (strncmp(argv[1], "skipcheck", 9) == 0) { /* E.g., change skip_check flag */ if (argc == 4) { @@ -735,6 +786,9 @@ U_BOOT_CMD( " - Remove volume\n" #if IS_ENABLED(CONFIG_CMD_UBI_RENAME) "ubi rename oldname newname\n" +#endif +#if IS_ENABLED(CONFIG_CMD_UBI_SWAPVOL) + "ubi swap volume_a volume_b\n" #endif "ubi skipcheck volume on/off - Set or clear skip_check flag in volume header\n" "[Legends]\n" -- 2.17.1

3 2

GSuit limit for recipients
by Oleksandr Suvorov 28 Sep '21

28 Sep '21

Dear community, This weekend I tried to post (using patman) a patch set that should have been sent to 120 recipients (a lot of files were changed). I've got an error from the Gmail SMTP server: 4.5.3 Your message has too many recipients. For more information regarding 4.5.3 Google's sending limits, please visit: 4.5.3 https://support.google.com/mail/?p=TooManyRecipientsError e1sm1539543ljp.114 - gsmtp The doc says there is a limit for recipients - 100 per message. All my emails are hosted by Gmail/G-suit. I think I'm not the first who faced such an issue. Could you share your tricks or best practices on how to post patch sets with more than 100 recipients without changing an e-mail provider? Thanks in advance for your help! -- Best regards, Oleksandr Suvorov Software Engineer T: +380 63 8489656 E: oleksandr.suvorov(a)foundries.io W: www.foundries.io

2 2

S25HS512 not functional with u-boot 2021.10.rc3
by Harkirat Virk 28 Sep '21

28 Sep '21

I have a custom board using imx6ul and Spansion S25HS512T Flash. On the current version of u-boot (2021.10.rc3) and I am guessing even previous ones the Spansion flash is not functioning => sf probe drivers/core/uclass.c:325-uclass_find_device_by_seq() 0 drivers/core/uclass.c:333-uclass_find_device_by_seq() - 0 'spi@21e0000' drivers/core/uclass.c:336-uclass_find_device_by_seq() - found drivers/spi/spi-uclass.c:282-spi_find_chip_select() fsl_qspi spi@21e0000: spi_find_chip_select: plat=9ef2bf60, cs=0 drivers/core/uclass.c:325-uclass_find_device_by_seq() 0 drivers/core/uclass.c:333-uclass_find_device_by_seq() - 0 'spi@21e0000' drivers/core/uclass.c:336-uclass_find_device_by_seq() - found drivers/spi/spi-uclass.c:282-spi_find_chip_select() fsl_qspi spi@21e0000: spi_find_chip_select: plat=9ef2bf60, cs=0 drivers/core/uclass.c:325-uclass_find_device_by_seq() 0 drivers/core/uclass.c:333-uclass_find_device_by_seq() - 0 'iomuxc@20e0000' drivers/core/uclass.c:336-uclass_find_device_by_seq() - found drivers/pinctrl/pinctrl-uclass.c:300-pinctrl_select_state_simple() jedec_spi_nor s25hs512t@0: set_state_simple op missing drivers/spi/fsl_qspi.c:464-fsl_qspi_prepare_lut() fsl_qspi spi@21e0000: CMD[9f] lutval[0:1c00049f 1:0 2:0 3:0] drivers/spi/spi-uclass.c:438- spi_get_bus_and_cs() spi_get_bus_and_cs: Error path, created=0, device 's25hs512t@0' Failed to initialize SPI flash at 0:0 (error -524) Result is the same with different modes and frequencies, bus and CS are correct My DTSI is &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; status = "okay"; flash0: s25hs512t@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spansion,s25hs512t", "jedec,spi-nor"; spi-max-frequency = <40000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; reg = <0>; spi-mode = <0>; m25p,fast-read; status = "okay"; /* some partition information*/ }; }; Defconfig has CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_SPANSION=y DM Tree => dm tree Class Index Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver thermal 0 [ ] imx_thermal |-- imx_thermal simple_bus 0 [ + ] simple_bus |-- soc simple_bus 1 [ + ] simple_bus | |-- aips-bus@2000000 simple_bus 2 [ + ] simple_bus | | |-- spba-bus@2000000 serial 0 [ + ] serial_mxc | | | `-- serial@2020000 gpio 0 [ ] gpio_mxc | | |-- gpio@209c000 gpio 1 [ ] gpio_mxc | | |-- gpio@20a0000 gpio 2 [ ] gpio_mxc | | |-- gpio@20a4000 gpio 3 [ ] gpio_mxc | | |-- gpio@20a8000 gpio 4 [ ] gpio_mxc | | |-- gpio@20ac000 simple_bus 3 [ ] simple_bus | | |-- anatop@20c8000 simple_bus 4 [ ] simple_bus | | |-- snvs@20cc000 pinctrl 0 [ + ] fsl_imx6q_iomuxc | | `-- iomuxc@20e0000 pinconfig 0 [ ] pinconfig | | |-- i2c1grp pinconfig 1 [ ] pinconfig | | |-- i2c2grp pinconfig 2 [ + ] pinconfig | | |-- qspigrp pinconfig 3 [ ] pinconfig | | |-- ledsgrp pinconfig 4 [ + ] pinconfig | | |-- uart1grp pinconfig 5 [ + ] pinconfig | | |-- usdhc2grp pinconfig 6 [ ] pinconfig | | `-- wdoggrp simple_bus 5 [ + ] simple_bus | `-- aips-bus@2100000 usb 0 [ ] ehci_mx6 | |-- usb@2184000 mmc 0 [ + ] fsl_esdhc | |-- usdhc@2194000 blk 0 [ ] mmc_blk | | `-- usdhc(a)2194000.blk i2c 0 [ ] i2c_mxc | |-- i2c@21a0000 i2c 1 [ ] i2c_mxc | |-- i2c@21a4000 spi 0 [ + ] fsl_qspi | `-- spi@21e0000 spi_flash 0 [ ] jedec_spi_nor | `-- s25hs512t@0 regulator 0 [ ] regulator_fixed |-- regulator-sd2-vmmc led 0 [ ] gpio_led `-- leds led 1 [ ] gpio_led |-- green led 2 [ ] gpio_led |-- red led 3 [ ] gpio_led `— amber I am unable to identify source of error returning -524 or why SPI Flash initialisation fails

3 2

[PATCH] board: ti: Add support for the AM437x GP EVM mini board
by Amjad Ouled-Ameur 28 Sep '21

28 Sep '21

From: Andreas Dannenberg <dannenberg(a)ti.com> This is not really a new board but rather a minimal bootloader solution for the AM437x GP EVM. In terms of interfaces, it only supports booting from MMC0 or UART0 and only activates a minimal set of drivers that are that are necessary to run the device such as DDR, I2C, and PMIC. The goal is to provide a bare minimum starting point to boot Linux for basing custom board-ports on. The limited complexity of this solution should make it easier to achieve a successful boot to U-Boot prompt vs. trying to pair down the full-featured multi-platform AM437x U-Boot available through am43xx_evm_defconfig. Signed-off-by: Andreas Dannenberg <dannenberg(a)ti.com> [Amjad: fix compile and checkpatch warnings] Signed-off-by: Amjad Ouled-Ameur <aouledameur(a)baylibre.com> --- Tests: - This has been tested on AM43xx platform, the board boots successfully to u-boot prompt and runs basic commands seamlessly, please find the logs here: [0] However, regarding the kernel boot test, sometimes it does boot correctly, sometimes it does not, but this patch does not actually guaranteey that since its purpose is to mainly allow the user to achieve a successful boot to U-boot prompt. [0]: https://pastebin.com/zmCsjQRT MAINTAINERS | 4 + arch/arm/dts/Makefile | 5 +- arch/arm/dts/am437x-gp-evm-mini.dts | 171 ++++++++++ arch/arm/mach-omap2/am33xx/Kconfig | 22 ++ board/ti/am43xx/Kconfig | 13 +- board/ti/am43xx/Makefile | 6 +- board/ti/am43xx/board_hs_mini.h | 27 ++ board/ti/am43xx/board_mini.c | 452 +++++++++++++++++++++++++++ board/ti/am43xx/board_mini.h | 28 ++ board/ti/am43xx/mux_mini.c | 53 ++++ configs/am43xx_evm_mini_defconfig | 39 +++ configs/am43xx_hs_evm_mini_defconfig | 47 +++ include/configs/am43xx_evm_mini.h | 120 +++++++ 13 files changed, 983 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/am437x-gp-evm-mini.dts create mode 100644 board/ti/am43xx/board_hs_mini.h create mode 100644 board/ti/am43xx/board_mini.c create mode 100644 board/ti/am43xx/board_mini.h create mode 100644 board/ti/am43xx/mux_mini.c create mode 100644 configs/am43xx_evm_mini_defconfig create mode 100644 configs/am43xx_hs_evm_mini_defconfig create mode 100644 include/configs/am43xx_evm_mini.h diff --git a/MAINTAINERS b/MAINTAINERS index 5370b550648e..0159be0e4673 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -492,6 +492,7 @@ F: arch/arm/mach-keystone/ F: arch/arm/mach-omap2/ F: arch/arm/include/asm/arch-omap*/ F: arch/arm/include/asm/ti-common/ +F: arch/arm/dts/am437x* F: board/ti/ F: drivers/dma/ti* F: drivers/firmware/ti_sci.* @@ -518,6 +519,7 @@ F: drivers/timer/omap-timer.c F: drivers/watchdog/omap_wdt.c F: include/linux/pruss_driver.h F: include/linux/soc/ti/ +F: include/configs/am43xx_evm_mini.h ARM U8500 M: Stephan Gerhold <stephan(a)gerhold.net> @@ -1134,6 +1136,8 @@ F: arch/arm/mach-k3/config_secure.mk F: configs/am335x_hs_evm_defconfig F: configs/am335x_hs_evm_uart_defconfig F: configs/am43xx_hs_evm_defconfig +F: configs/am43xx_evm_mini_defconfig +F: configs/am43xx_hs_evm_mini_defconfig F: configs/am57xx_hs_evm_defconfig F: configs/am57xx_hs_evm_usb_defconfig F: configs/dra7xx_hs_evm_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fc16a57e60b0..3b8c539a6272 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -375,7 +375,10 @@ dtb-$(CONFIG_AM33XX) += \ am335x-guardian.dtb \ am335x-wega-rdk.dtb \ am335x-regor-rdk.dtb -dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ +dtb-$(CONFIG_AM43XX) += \ + am437x-gp-evm.dtb \ + am437x-gp-evm-mini.dtb \ + am437x-sk-evm.dtb \ am43x-epos-evm.dtb \ am437x-idk-evm.dtb \ am4372-generic.dtb \ diff --git a/arch/arm/dts/am437x-gp-evm-mini.dts b/arch/arm/dts/am437x-gp-evm-mini.dts new file mode 100644 index 000000000000..07c93c47b638 --- /dev/null +++ b/arch/arm/dts/am437x-gp-evm-mini.dts @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/* AM437x GP EVM MINI */ + +/dts-v1/; + +#include "am4372.dtsi" +#include <dt-bindings/pinctrl/am43xx.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "TI AM437x GP EVM MINI"; + compatible = "ti,am437x-gp-evm-mini","ti,am437x-gp-evm","ti,am4372","ti,am43"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer2; + }; + + ocp { + u-boot,dm-spl; + }; + + vmmcsd_fixed: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + + vtt_fixed: fixedregulator-vtt { + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; + }; + + vmmcwl_fixed: fixedregulator-mmcwl { + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&am43xx_pinmux { + i2c0_pins: i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + + tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdcdc3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + u-boot,dm-spl; +}; + +&uart0 { + u-boot,dm-spl; +}; + +&i2c0 { + u-boot,dm-spl; +}; diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 4268419b166b..d21d042cf868 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -244,6 +244,28 @@ config TARGET_AM43XX_EVM to write software and develop hardware around an AM43xx processor subsystem. +config TARGET_AM43XX_EVM_MINI + bool "Support am43xx_evm_mini" + select BOARD_LATE_INIT + imply DM_I2C + imply SPL_ENV_SUPPORT + imply SPL_FS_EXT4 + imply SPL_FS_FAT + imply SPL_GPIO_SUPPORT + imply SPL_I2C_SUPPORT + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_MMC_SUPPORT + imply SPL_POWER_SUPPORT + imply SPL_SERIAL_SUPPORT + imply SPL_YMODEM_SUPPORT + help + This option specifies support for the AM43xx + GP and HS EVM development platforms using a minimal + system configuration, only supporting a small subset + of boot media and other features. + config TARGET_CM_T43 bool "Support cm_t43" diff --git a/board/ti/am43xx/Kconfig b/board/ti/am43xx/Kconfig index 9cb80cc3f1da..533e78cda916 100644 --- a/board/ti/am43xx/Kconfig +++ b/board/ti/am43xx/Kconfig @@ -1,4 +1,4 @@ -if TARGET_AM43XX_EVM +if TARGET_AM43XX_EVM || TARGET_AM43XX_EVM_MINI config SYS_BOARD default "am43xx" @@ -9,9 +9,20 @@ config SYS_VENDOR config SYS_SOC default "am33xx" +if TARGET_AM43XX_EVM + config SYS_CONFIG_NAME default "am43xx_evm" +endif + +if TARGET_AM43XX_EVM_MINI + +config SYS_CONFIG_NAME + default "am43xx_evm_mini" + +endif + source "board/ti/common/Kconfig" endif diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile index 60a11d8c04d2..b7606c304148 100644 --- a/board/ti/am43xx/Makefile +++ b/board/ti/am43xx/Makefile @@ -5,7 +5,9 @@ # Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) -obj-y := mux.o +obj-$(CONFIG_TARGET_AM43XX_EVM) := mux.o +obj-$(CONFIG_TARGET_AM43XX_EVM_MINI) := mux_mini.o endif -obj-y += board.o +obj-$(CONFIG_TARGET_AM43XX_EVM) += board.o +obj-$(CONFIG_TARGET_AM43XX_EVM_MINI) += board_mini.o diff --git a/board/ti/am43xx/board_hs_mini.h b/board/ti/am43xx/board_hs_mini.h new file mode 100644 index 000000000000..3804bfc81d54 --- /dev/null +++ b/board/ti/am43xx/board_hs_mini.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * TI AM437x boards information header + * Derived from AM335x board. + * + * Copyright (C) 2020, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _BOARD_HS_H_ +#define _BOARD_HS_H_ + +#ifdef CONFIG_TI_SECURE_DEVICE +void board_fit_image_post_process(const void *fit, int node, + void **p_image, size_t *p_size) +{ + secure_boot_verify_image(p_image, p_size); +} + +void board_tee_image_process(ulong tee_image, size_t tee_size) +{ + secure_tee_install((u32)tee_image); +} + +U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); +#endif + +#endif diff --git a/board/ti/am43xx/board_mini.c b/board/ti/am43xx/board_mini.c new file mode 100644 index 000000000000..7560274be088 --- /dev/null +++ b/board/ti/am43xx/board_mini.c @@ -0,0 +1,452 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Mini board functions for TI AM43XX based boards + * + * Copyright (C) 2020, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <eeprom.h> +#include <env.h> +#include <i2c.h> +#include <init.h> +#include <linux/errno.h> +#include <spl.h> +#include <usb.h> +#include <fdt_support.h> +#include <image.h> +#include <asm/omap_sec_common.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mux.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/gpio.h> +#include <asm/emif.h> +#include <asm/omap_common.h> +#include <power/pmic.h> +#include <power/tps65218.h> +#include "board_mini.h" +#include "board_hs_mini.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { + { /* 19.2 MHz */ + {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ + {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ + {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ + {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 24 MHz */ + {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 25 MHz */ + {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ + }, + { /* 26 MHz */ + {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ + {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ + {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ + {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ + {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ + {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ + }, +}; + +const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { + {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ + {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ + {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ + {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ +}; + +const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { + {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ + {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ + {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { + {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ + {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ + {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ + {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ +}; + +const struct dpll_params gp_evm_dpll_ddr = { + 50, 2, 1, -1, 2, -1, -1}; + +const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0xc163, +}; + +/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ +const struct emif_regs ddr3_emif_regs_400mhz_production = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x00048008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000066, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + if (!IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return &gp_evm_dpll_ddr; + return NULL; +} + +/* + * get_opp_offset: + * Returns the index for safest OPP of the device to boot. + * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. + * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. + * This data is read from dev_attribute register which is e-fused. + * A'1' in bit indicates OPP disabled and not available, a '0' indicates + * OPP available. Lowest OPP starts with min_off. So returning the + * bit with rightmost '0'. + */ +static int get_opp_offset(int max_off, int min_off) +{ + struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; + int opp, offset, i; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return 0; + + /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ + opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; + + for (i = max_off; i >= min_off; i--) { + offset = opp & (1 << i); + if (!offset) + return i; + } + + return min_off; +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + int opp; + u32 ind; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return NULL; + + opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); + ind = get_sys_clk_index(); + + return &dpll_mpu[ind][opp]; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + int ind; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return NULL; + + ind = get_sys_clk_index(); + + return &dpll_core[ind]; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + int ind; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return NULL; + + ind = get_sys_clk_index(); + + return &dpll_per[ind]; +} + +void scale_vcores_generic(u32 m) +{ + int mpu_vdd, ddr_volt; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + if (IS_ENABLED(CONFIG_DM_I2C)) { + if (power_tps65218_init(0)) + return; + } else { + if (i2c_probe(TPS65218_CHIP_PM)) + return; + } + + switch (m) { + case 1000: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; + break; + case 800: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; + break; + case 720: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; + break; + case 600: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; + break; + case 300: + mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; + break; + default: + puts("Unknown MPU clock, not scaling\n"); + return; + } + + /* Set DCDC1 (CORE) voltage to 1.1V */ + if (tps65218_voltage_update(TPS65218_DCDC1, + TPS65218_DCDC_VOLT_SEL_1100MV)) { + printf("%s failure\n", __func__); + return; + } + + /* Set DCDC2 (MPU) voltage */ + if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { + printf("%s failure\n", __func__); + return; + } + + ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV; + + /* Set DCDC3 (DDR) voltage */ + if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) { + printf("%s failure\n", __func__); + return; + } +} + +void gpi2c_init(void) +{ + /* When needed to be invoked prior to BSS initialization */ + static bool first_time = true; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + if (first_time) { + enable_i2c0_pin_mux(); + + if (!IS_ENABLED(CONFIG_DM_I2C)) + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE); + + first_time = false; + } +} + +void scale_vcores(void) +{ + const struct dpll_params *mpu_params; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + /* Ensure I2C is initialized for PMIC configuration */ + gpi2c_init(); + + /* Get the frequency */ + mpu_params = get_dpll_mpu_params(); + + scale_vcores_generic(mpu_params->m); +} + +void set_uart_mux_conf(void) +{ + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + enable_board_pin_mux(); +} + +static void enable_vtt_regulator(void) +{ + u32 temp; + + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + /* enable module */ + writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); + + /* enable output for GPIO5_7 */ + writel(GPIO_SETDATAOUT(7), + AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); + temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); + temp = temp & ~(GPIO_OE_ENABLE(7)); + writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); +} + +void sdram_init(void) +{ + if (IS_ENABLED(CONFIG_SKIP_LOWLEVEL_INIT)) + return; + + /* GP EVM has 1GB DDR3 connected to EMIF along with VTT regulator */ + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, + &ddr3_emif_regs_400mhz_production, 0); +} + +/* setup board specific PMIC */ +int power_init_board(void) +{ + int rc; + struct pmic *p = NULL; + + rc = power_tps65218_init(0); + if (rc) + goto done; + + if (!IS_ENABLED(CONFIG_DM_I2C)) { + p = pmic_get("TPS65218_PMIC"); + if (!p || pmic_probe(p)) + goto done; + } + + puts("PMIC: TPS65218\n"); + +done: + return 0; +} + +int board_init(void) +{ + struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; + u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, + modena_init0_bw_integer, modena_init0_watermark_0; + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + + /* + * Call this to initialize *ctrl again + */ + hw_data_init(); + + /* Clear all important bits for DSS errata that may need to be tweaked*/ + mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & + MREQPRIO_0_SAB_INIT0_MASK; + + mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; + + modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & + BW_LIMITER_BW_FRAC_MASK; + + modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & + BW_LIMITER_BW_INT_MASK; + + modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & + BW_LIMITER_BW_WATERMARK_MASK; + + /* Setting MReq Priority of the DSS*/ + mreqprio_0 |= 0x77; + + /* + * Set L3 Fast Configuration Register + * Limiting bandwidth for ARM core to 700 MBPS + */ + modena_init0_bw_fractional |= 0x10; + modena_init0_bw_integer |= 0x3; + + writel(mreqprio_0, &cdev->mreqprio_0); + writel(mreqprio_1, &cdev->mreqprio_1); + + writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); + writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); + writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); + + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_BOARD_LATE_INIT) && + IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + env_set("board_name", CONFIG_SYS_BOARD); + + /* + * Default FIT boot on HS devices. Non FIT images are not allowed + * on HS devices. + */ + if (get_device_type() == HS_DEVICE) + env_set("boot_fit", "1"); + } + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + if (IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)) + ft_cpu_setup(blob, bd); + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + return 0; +} + +int embedded_dtb_select(void) +{ + if (IS_ENABLED(CONFIG_DTB_RESELECT)) + do_board_detect(); + + return 0; +} diff --git a/board/ti/am43xx/board_mini.h b/board/ti/am43xx/board_mini.h new file mode 100644 index 000000000000..927057465cac --- /dev/null +++ b/board/ti/am43xx/board_mini.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * TI AM437x boards information header + * Derived from AM335x board. + * + * Copyright (C) 2020, Texas Instruments, Incorporated - http://www.ti.com/ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include <asm/arch/omap.h> + +#define DEV_ATTR_MAX_OFFSET 5 +#define DEV_ATTR_MIN_OFFSET 0 + +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); +void enable_i2c0_pin_mux(void); + +#ifdef CONFIG_DM_I2C +#define pmic_get(name) (NULL) +#define pmic_probe(p) (NULL) +#define i2c_init(speed, slaveaddr) +#define i2c_probe(chip) (NULL) +#endif + +#endif diff --git a/board/ti/am43xx/mux_mini.c b/board/ti/am43xx/mux_mini.c new file mode 100644 index 000000000000..1230248e3b29 --- /dev/null +++ b/board/ti/am43xx/mux_mini.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mux.h> +#include "board_mini.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */ + {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux gpio5_7_pin_mux[] = { + {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(gpio5_7_pin_mux); /* DDR VTT Enable */ +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} diff --git a/configs/am43xx_evm_mini_defconfig b/configs/am43xx_evm_mini_defconfig new file mode 100644 index 000000000000..451118cc2a21 --- /dev/null +++ b/configs/am43xx_evm_mini_defconfig @@ -0,0 +1,39 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_COMMON_CMD_OPTIONS=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm-mini" +CONFIG_AM43XX=y +CONFIG_TARGET_AM43XX_EVM_MINI=y +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_MISC_INIT_R is not set +CONFIG_SPL_I2C=y +# CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_POWER=y +CONFIG_CMD_SPL=y +CONFIG_CMD_SPL_WRITE_SIZE=0x40000 +# CONFIG_CMD_EEPROM is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_MISC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_DM_SERIAL=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y diff --git a/configs/am43xx_hs_evm_mini_defconfig b/configs/am43xx_hs_evm_mini_defconfig new file mode 100644 index 000000000000..97582c4d1b23 --- /dev/null +++ b/configs/am43xx_hs_evm_mini_defconfig @@ -0,0 +1,47 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_ISW_ENTRY_ADDR=0x403018e0 +CONFIG_TI_COMMON_CMD_OPTIONS=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm-mini" +CONFIG_AM43XX=y +CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000 +CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 +CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 +CONFIG_TARGET_AM43XX_EVM_MINI=y +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_MISC_INIT_R is not set +CONFIG_SPL_I2C=y +# CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_POWER=y +CONFIG_CMD_SPL=y +CONFIG_CMD_SPL_WRITE_SIZE=0x40000 +# CONFIG_CMD_EEPROM is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_MISC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_DM_SERIAL=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y diff --git a/include/configs/am43xx_evm_mini.h b/include/configs/am43xx_evm_mini.h new file mode 100644 index 000000000000..3f7c3e7c7fba --- /dev/null +++ b/include/configs/am43xx_evm_mini.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef __CONFIG_AM43XX_EVM_MINI_H +#define __CONFIG_AM43XX_EVM_MINI_H + +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ + +#include <asm/arch/omap.h> + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_CLK 48000000 +#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_SERIAL +#endif + +/* I2C Configuration */ +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* Power */ +#ifndef CONFIG_DM_I2C +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#endif +#define CONFIG_POWER_TPS65218 + +/* SPL defines. */ +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) + +/* Enabling L2 Cache */ +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x48242000 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * When building U-Boot such that there is no previous loader + * we need to call board_early_init_f. This is taken care of in + * s_init when we have SPL used. + */ + +/* Now bring in the rest of the common code. */ +#include <configs/ti_armv7_omap.h> + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ + +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_TIMER +#endif + +#ifndef CONFIG_SPL_BUILD +#include <environment/ti/mmc.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + DEFAULT_FIT_TI_ARGS \ + "fdtfile=undefined\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "console=ttyS0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ + "optargs=\0" \ + "ramroot=/dev/ram0 rw\0" \ + "ramrootfstype=ext2\0" \ + "usbargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${usbroot} " \ + "rootfstype=${usbrootfstype}\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \ + "default_device_tree=am437x-gp-evm.dtb\0" \ + "findfdt=" \ + "setenv name_fdt ${default_device_tree};" \ + "setenv fdtfile ${name_fdt}\0" + +#define CONFIG_BOOTCOMMAND \ + "if test ${boot_fit} -eq 1; then " \ + "run update_to_fit;" \ + "fi;" \ + "run findfdt;" \ + "run envboot;" \ + "run mmcboot;" + +#endif + +#if defined(CONFIG_TI_SECURE_DEVICE) +/* Avoid relocating onto firewalled area at end of DRAM */ +#define CONFIG_PRAM (64 * 1024) +#endif /* CONFIG_TI_SECURE_DEVICE */ + +#endif /* __CONFIG_AM43XX_EVM_MINI_H */ -- 2.25.1

1 0

[PATCH] ARM: omap3_logic: Cleanup usage of MUX_VAL
by Adam Ford 28 Sep '21

28 Sep '21

The macro called MUX_VAL generates a writel instruction with semicolon at the end. This table was written to use semicolons, however one was missed: MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */ Since the extra semicolon is unnecessary with the use of the macro, remove all of them. Suggested-by: Wolfgang Denk <wd(a)denx.de> Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h index 63c2141783..caa9876319 100644 --- a/board/logicpd/omap3som/omap3logic.h +++ b/board/logicpd/omap3som/omap3logic.h @@ -45,209 +45,209 @@ const omap3_sysinfo sysinfo = { */ void set_muxconf_regs(void) { - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*SDRC_CKE0*/ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /*SDRC_CKE1*/ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /*GPMC_nCS1*/ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /*GPMC_nCS2*/ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /*GPMC_nCS3*/ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); /*GPMC_nCS5*/ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)); /*GPMC_nCS6*/ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)); /*GPMC_nCS7*/ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); /*GPMC_CLK*/ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*GPMC_nADV_ALE*/ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*GPMC_nOE*/ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*GPMC_nWE*/ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*GPMC_nBE0_CLE*/ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); /*GPMC_nBE1*/ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*GPMC_nWP*/ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*GPMC_WAIT0*/ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /*GPMC_WAIT1*/ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)); /*GPMC_WAIT3*/ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M0)) /*GPMC_nCS6*/ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /*UART1_TX*/ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /*UART1_RTS*/ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /*UART1_CTS*/ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /*UART1_RX*/ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /*JTAG_EMU0*/ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /*JTAG_EMU1*/ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /*ETK_CLK*/ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /*ETK_CTL*/ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); /*ETK_D0*/ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); /*ETK_D1*/ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); /*ETK_D2*/ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); /*ETK_D3*/ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /*ETK_D4*/ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /*ETK_D5*/ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /*ETK_D6*/ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /*ETK_D7*/ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /*ETK_D8*/ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /*ETK_D9*/ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) /*ETK_CLK*/ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) /*ETK_CTL*/ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) /*ETK_D0*/ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) /*ETK_D1*/ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) /*ETK_D2*/ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) /*ETK_D3*/ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) /*ETK_D4*/ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) /*ETK_D5*/ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) /*ETK_D6*/ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) /*ETK_D7*/ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) /*ETK_D8*/ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) /*ETK_D9*/ #ifndef CONFIG_USB_EHCI_OMAP /* Torpedo does not use EHCI_OMAP */ - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /*ETK_D10*/ - MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /*ETK_D11*/ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /*ETK_D12*/ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /*ETK_D13*/ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /*ETK_D14*/ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /*ETK_D15*/ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) /*ETK_D10*/ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) /*ETK_D11*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) /*ETK_D12*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) /*ETK_D13*/ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) /*ETK_D14*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) /*ETK_D15*/ #endif - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /*d2d_mcad1*/ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /*d2d_mcad2*/ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /*d2d_mcad3*/ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /*d2d_mcad4*/ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /*d2d_mcad5*/ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /*d2d_mcad6*/ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /*d2d_mcad7*/ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /*d2d_mcad8*/ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /*d2d_mcad9*/ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /*d2d_mcad10*/ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /*d2d_mcad11*/ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /*d2d_mcad12*/ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /*d2d_mcad13*/ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /*d2d_mcad14*/ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /*d2d_mcad15*/ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /*d2d_mcad16*/ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /*d2d_mcad17*/ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /*d2d_mcad18*/ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /*d2d_mcad19*/ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /*d2d_mcad20*/ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /*d2d_mcad21*/ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /*d2d_mcad22*/ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /*d2d_mcad23*/ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /*d2d_mcad24*/ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /*d2d_mcad25*/ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /*d2d_mcad26*/ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /*d2d_mcad27*/ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /*d2d_mcad28*/ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /*d2d_mcad29*/ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /*d2d_mcad30*/ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /*d2d_mcad31*/ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /*d2d_mcad32*/ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /*d2d_mcad33*/ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /*d2d_mcad34*/ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /*d2d_mcad35*/ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /*d2d_mcad36*/ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /*d2d_clk26mi*/ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /*d2d_nrespwron*/ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /*d2d_nreswarm */ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /*d2d_arm9nirq */ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /*d2d_uma2p6fiq*/ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /*d2d_spint*/ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /*d2d_frint*/ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /*d2d_dmareq0*/ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /*d2d_dmareq1*/ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /*d2d_dmareq2*/ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /*d2d_dmareq3*/ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /*d2d_n3gtrst*/ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /*d2d_n3gtdi*/ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /*d2d_n3gtdo*/ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /*d2d_n3gtms*/ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /*d2d_n3gtck*/ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /*d2d_n3grtck*/ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /*d2d_mstdby*/ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /*d2d_swakeup*/ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /*d2d_idlereq*/ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /*d2d_idleack*/ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /*d2d_mwrite*/ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /*d2d_swrite*/ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /*d2d_mread*/ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /*d2d_sread*/ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_mbusflag*/ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /*d2d_sbusflag*/ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/ #ifdef CONFIG_USB_EHCI_OMAP /* SOM-LV Uses EHCI-OMAP */ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA0*/ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_DATA1*/ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /*HSUSB2_DATA2*/ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /*HSUSB2_DATA3*/ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA4*/ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA5*/ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /*HSUSB2_DATA6*/ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /*HSUSB2_DATA7*/ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*HSUSB2_DATA2*/ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*HSUSB2_DATA3*/ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA4*/ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA5*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*HSUSB2_DATA6*/ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA7*/ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_CLK*/ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)); /*HSUSB2_DIR*/ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)); /*HSUSB2_NXT*/ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/ #endif } -- 2.25.1

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[PATCH] i2c: rcar_i2c: Enable configuring SCL rise and fall times
by Adam Ford 28 Sep '21

28 Sep '21

The Linux i2c driver supports i2c-scl-rising-time-ns, and i2c-scl-falling-time-ns, but U-Boot uses hard-coded values for these values. Update the calculation by fetching them from the device tree if present and use the previous values as the default if they are missing. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c index 14bb6603d5..d9ece5e3a8 100644 --- a/drivers/i2c/rcar_i2c.c +++ b/drivers/i2c/rcar_i2c.c @@ -64,6 +64,8 @@ enum rcar_i2c_type { struct rcar_i2c_priv { void __iomem *base; struct clk clk; + u32 fall_ns; + u32 rise_ns; u32 intdelay; u32 icccr; enum rcar_i2c_type type; @@ -278,7 +280,7 @@ static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz) * = F[sum * ick / 1000000000] * = F[(ick / 1000000) * sum / 1000] */ - sum = 35 + 200 + priv->intdelay; + sum = priv->fall_ns + priv->rise_ns + priv->intdelay; round = (ick + 500000) / 1000000 * sum; round = (round + 500) / 1000; @@ -323,6 +325,10 @@ static int rcar_i2c_probe(struct udevice *dev) int ret; priv->base = dev_read_addr_ptr(dev); + priv->rise_ns = dev_read_u32_default(dev, + "i2c-scl-rising-time-ns", 200); + priv->fall_ns = dev_read_u32_default(dev, + "i2c-scl-falling-time-ns", 35); priv->intdelay = dev_read_u32_default(dev, "i2c-scl-internal-delay-ns", 5); priv->type = dev_get_driver_data(dev); -- 2.25.1

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