July 2021 - U-Boot

[PATCH] mpc8379erdb: enable DM_USB DM_PCI DM_ETH
by sinan＠writeme.com 07 Jul '21

07 Jul '21

From: Sinan Akman <sinan(a)writeme.com> Signed-off-by: Sinan Akman <sinan(a)writeme.com> --- arch/powerpc/cpu/mpc83xx/pci.c | 2 ++ arch/powerpc/dts/mpc8379erdb.dts | 52 +++++++++++++++++++++++++++++++ board/freescale/mpc837xerdb/mpc837xerdb.c | 11 ++++++- configs/MPC837XERDB_defconfig | 18 +++++------ 4 files changed, 73 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c index 5c289d0022..507ab3417b 100644 --- a/arch/powerpc/cpu/mpc83xx/pci.c +++ b/arch/powerpc/cpu/mpc83xx/pci.c @@ -27,6 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct pci_controller pci_hose[MAX_BUSES]; static int pci_num_buses; +#if !defined(CONFIG_DM_PCI) static void pci_init_bus(int bus, struct pci_region *reg) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; @@ -184,6 +185,7 @@ void mpc83xx_pcislave_unlock(int bus) hose->last_busno = pci_hose_scan(hose); } #endif +#endif /* CONFIG_DM_PCI */ #if defined(CONFIG_OF_LIBFDT) void ft_pci_setup(void *blob, struct bd_info *bd) diff --git a/arch/powerpc/dts/mpc8379erdb.dts b/arch/powerpc/dts/mpc8379erdb.dts index b1881b161c..2e7c8f103c 100644 --- a/arch/powerpc/dts/mpc8379erdb.dts +++ b/arch/powerpc/dts/mpc8379erdb.dts @@ -69,6 +69,58 @@ device_type = "ipic"; }; + usb@23000 { + compatible = "fsl-usb2-dr"; + reg = <0x23000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&ipic>; + interrupts = <38 0x8>; + phy_type = "ulpi"; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <32 0x8 33 0x8 34 0x8>; + phy-connection-type = "mii"; + interrupt-parent = <&ipic>; + fixed-link = <1 0 1000 0 0>; + phy-handle = <&phy>; + fsl,magic-packet; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-mdio"; + reg = <0x520 0x20>; + + phy: ethernet-phy@2 { + interrupt-parent = <&ipic>; + interrupts = <17 0x8>; + reg = <0x2>; + device_type = "ethernet-phy"; + }; + }; + }; + + pci0: pci@e0008300 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + reg = <0x0 0xe0008300 0x0 0x00000fff>; + compatible = "fsl,mpc837x-pci"; + clock-frequency = <0>; + }; + }; }; diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 624e92ef9c..66b3d9a465 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -176,7 +176,7 @@ int board_early_init_f(void) } #ifdef CONFIG_FSL_ESDHC -#if !(CONFIG_IS_ENABLED(DM_MMC)) +#if !(CONFIG_IS_ENABLED(DM_MMC) || CONFIG_IS_ENABLED(DM_USB)) int board_mmc_init(struct bd_info *bd) { struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; @@ -217,6 +217,15 @@ int misc_init_r(void) return rc; } +int board_late_init(void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; +#ifdef CONFIG_USB + clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x40000000); +#endif + return 0; +} + #if defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 63ce36d533..b6161ca072 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -147,7 +147,9 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" CONFIG_BOOTDELAY=6 +CONFIG_BOARD_LATE_INIT=y CONFIG_MISC_INIT_R=y +CONFIG_PCI_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y @@ -173,16 +175,14 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_RGMII=y +CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_PCI=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -- 2.14.5

2 1

[PULL] u-boot-network/network_master
by Ramon Fried 06 Jul '21

06 Jul '21

Hi Tom, Please pull the latest patches in u-boot-net tree. It contains scattered commits to the network tree. The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de: Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-net.git for you to fetch changes up to 036e3622bf8394ff229ea0d348aa9a9a60e2c27a: net: dwc_eth_qos: cosmetic: remove unused define EQOS_DESCRIPTOR_ALIGN (2021-07-06 05:22:41 +0300) ---------------------------------------------------------------- Andre Przywara (2): net: smc911x: Drop redundant CONFIG_SMC911X_16_BIT Kconfig symbol net: smc911x: Determine bus width at runtime Michael Walle (1): board: sl28: add DSA support for variant 2 Patrick Delaunay (1): net: dwc_eth_qos: cosmetic: remove unused define EQOS_DESCRIPTOR_ALIGN Radu Pirea (NXP OSS) (1): phy: add nxp tja1103 phy driver Tim Harvey (1): cmd: net: add a 'net list' command to list network devs Vladimir Oltean (7): arm: dts: ls1028a: enable the switch CPU port for the LS1028A-QDS arm: dts: ls1028a: enable internal RGMII delays for the LS1028A-QDS AR8035 PHY arm: dts: ls1028a: declare the fixed-link speeds for the internal ENETC ports arm: dts: ls1028a: disable enetc-2 by default net: enetc: require a PHY device when probing net: enetc: force the RGMII MAC speed/duplex instead of using in-band signaling net: enetc: propagate the return code from phy_startup() to eth_ops::start MAINTAINERS | 5 + .../dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi | 7 + arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts | 40 +++ arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi | 9 + arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi | 9 + .../dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi | 9 + arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi | 9 + .../dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi | 9 + .../dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi | 9 + arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi | 9 + arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi | 9 + arch/arm/dts/fsl-ls1028a-qds.dtsi | 2 +- arch/arm/dts/fsl-ls1028a.dtsi | 12 +- cmd/net.c | 46 +++ drivers/net/Kconfig | 17 +- drivers/net/dwc_eth_qos.c | 2 - drivers/net/fsl_enetc.c | 59 ++-- drivers/net/fsl_enetc.h | 7 +- drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/nxp-c45-tja11xx.c | 348 +++++++++++++++++++++ drivers/net/phy/phy.c | 3 + drivers/net/smc911x.c | 41 ++- include/phy.h | 5 + 24 files changed, 614 insertions(+), 59 deletions(-) create mode 100644 drivers/net/phy/nxp-c45-tja11xx.c

2 1

[PATCH] cmd: ums: Enable by default for sunxi
by Andre Przywara 06 Jul '21

06 Jul '21

The ums command (presenting a U-Boot block device as a USB mass storage device) is very useful for accessing eMMC devices via USB-OTG. At the moment we enable USB fastboot by default for Allwinner devices, so it makes sense to do the same with USB mass storage, which is actually more versatile and can be accessed on any USB host easily. Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- cmd/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index a9fb4eead29..7b1c96910a8 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1347,6 +1347,7 @@ config CMD_USB_MASS_STORAGE bool "UMS usb mass storage" select USB_FUNCTION_MASS_STORAGE depends on BLK && USB_GADGET + default y if ARCH_SUNXI && USB_MUSB_GADGET help Enables the command "ums" and the USB mass storage support to the export a block device: U-Boot, the USB device, acts as a simple -- 2.17.5

4 4

[PATCH] rk3399: Add basic support for helios64
by Uwe Kleine-König 06 Jul '21

06 Jul '21

This is a stripped down version of the vendor U-Boot patch by Aditya Prayoga found in the armbian repository. This patch is enough to have the 1G ethernet port, the micro SD card, eMMC and UART operational and let it boot a Debian netboot installer. The device tree is contained in Linux v5.11-rc1. During my work on U-Boot I noticed a wrong pull setting, the corresponding patch is still in linux-next and already applied in the copy that is added by this patch. Signed-off-by: Uwe Kleine-König <uwe(a)kleine-koenig.org> --- Hello, @Aditya: I kept you as maintainer in MAINTAINERS, is this ok for you? I doubt that I'm qualified enough for that. So please wait for this question to be resolved before you apply this patch. Best regards Uwe arch/arm/dts/Makefile | 1 + .../arm/dts/rk3399-kobol-helios64-u-boot.dtsi | 266 +++++++++++++ arch/arm/dts/rk3399-kobol-helios64.dts | 372 ++++++++++++++++++ arch/arm/mach-rockchip/rk3399/Kconfig | 17 + board/kobol/helios64/Kconfig | 24 ++ board/kobol/helios64/MAINTAINERS | 6 + board/kobol/helios64/Makefile | 5 + board/kobol/helios64/helios64.c | 262 ++++++++++++ board/kobol/helios64/sys_otp.c | 248 ++++++++++++ board/kobol/helios64/sys_otp.h | 10 + configs/helios64-rk3399_defconfig | 142 +++++++ include/configs/helios64.h | 47 +++ 12 files changed, 1400 insertions(+) create mode 100644 arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-kobol-helios64.dts create mode 100644 board/kobol/helios64/Kconfig create mode 100644 board/kobol/helios64/MAINTAINERS create mode 100644 board/kobol/helios64/Makefile create mode 100644 board/kobol/helios64/helios64.c create mode 100644 board/kobol/helios64/sys_otp.c create mode 100644 board/kobol/helios64/sys_otp.h create mode 100644 configs/helios64-rk3399_defconfig create mode 100644 include/configs/helios64.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fd47e408f826..752ba4fd8b35 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -125,6 +125,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ + rk3399-kobol-helios64.dtb \ rk3399-khadas-edge.dtb \ rk3399-khadas-edge-captain.dtb \ rk3399-khadas-edge-v.dtb \ diff --git a/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi b/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi new file mode 100644 index 000000000000..84a27548a08d --- /dev/null +++ b/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Aditya Prayoga (aditya(a)kobol.io) + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" + +/ { + aliases { + spi0 = &spi1; + ethernet0 = &gmac; + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff1a0000 earlyprintk"; + stdout-path = "serial2:1500000n8"; + u-boot,spl-boot-order = "same-as-spl", &spiflash, &sdmmc, &sdhci; + }; + + config { + u-boot,spl-payload-offset = <0x80000>; /* @ 512KB */ + }; + + leds { + led-1 { + linux,default-trigger = "panic"; + }; + }; + + vcc3v0_sd: vcc3v0-sd { + startup-delay-us = <20000>; + }; +}; + +&cpu_alert0 { + temperature = <80000>; +}; + +&cpu_alert1 { + temperature = <95000>; +}; + +&cpu_crit { + temperature = <100000>; +}; + +&i2c0 { + rk808: pmic@1b { + rockchip,system-power-controller; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr_s3: DCDC_REG3 { + regulator-name = "vcc_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + /* not used */ + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + }; + + /* not used */ + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; + }; + + vcc1v8_s3: LDO_REG3 { + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + /* not used */ + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + }; + + vcc1v5_s3: LDO_REG6 { + regulator-name = "vcc1v5_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + /* not used */ + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + }; + + vcc3v3_sys_s0: SWITCH_REG1 { + regulator-name = "vcc3v3_sys_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-compatible = "fan53555-reg"; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&pinctrl { + pmic { + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc3v0_s3>; + status = "okay"; +}; + +&sdmmc { + sd-uhs-sdr104; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&gpio1 { + usb-mux-hs { + gpio-hog; + gpios = <RK_PA4 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "USB_MUX_HS"; + }; + + usb-mux-oe { + gpio-hog; + gpios = <RK_PB5 GPIO_ACTIVE_LOW>; + output-high; + line-name = "USB_MUX_OE#"; + }; + + soc-flash-wp { + gpio-hog; + gpios = <RK_PC2 GPIO_ACTIVE_LOW>; + output-low; + line-name = "SOC_WP#"; + }; +}; + +&gpio2 { + sata-flash-wp { + gpio-hog; + gpios = <RK_PD0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "SATA_WP#_LV"; + }; +}; + +&gpio4 { + auto-on-en-d { + gpio-hog; + gpios = <RK_PD1 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "AUTO_ON_EN_D"; + }; + + auto-on-en-clk { + gpio-hog; + gpios = <RK_PD2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "AUTO_ON_EN_CLK"; + }; + + board-rev-id-0 { + gpio-hog; + gpios = <RK_PD5 GPIO_ACTIVE_HIGH>; + input; + }; + + board-rev-id-1 { + gpio-hog; + gpios = <RK_PD6 GPIO_ACTIVE_HIGH>; + input; + }; +}; + +&spi1 { + status = "okay"; + + spiflash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <25000000>; + status = "okay"; + m25p,fast-read; + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/rk3399-kobol-helios64.dts b/arch/arm/dts/rk3399-kobol-helios64.dts new file mode 100644 index 000000000000..66c725a34220 --- /dev/null +++ b/arch/arm/dts/rk3399-kobol-helios64.dts @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Aditya Prayoga <aditya(a)kobol.io> + */ + +/* + * The Kobol Helios64 is a board designed to operate as a NAS and optionally + * ships with an enclosing that can host five 2.5" hard disks. + * + * See https://wiki.kobol.io/helios64/intro/ for further details. + */ + +/dts-v1/; +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Kobol Helios64"; + compatible = "kobol,helios64", "rockchip,rk3399"; + + avdd_1v8_s0: avdd-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "avdd_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys_s3>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_grn_led_on &sys_red_led_on>; + + led-0 { + label = "helios64:green:status"; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-1 { + label = "helios64:red:fault"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + vcc1v8_sys_s0: vcc1v8-sys-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc1v8_sys_s3>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v0_sd"; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + vin-supply = <&vcc3v3_sys_s3>; + }; + + vcc3v3_sys_s3: vcc_lan: vcc3v3-sys-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin_bkup>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc12v_dcin_bkup: vcc12v-dcin-bkup { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin_bkup"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +/* + * The system doesn't run stable with cpu freq enabled, so disallow the lower + * frequencies until this problem is properly understood and resolved. + */ +&cluster0_opp { + /delete-node/ opp00; + /delete-node/ opp01; + /delete-node/ opp02; + /delete-node/ opp03; + /delete-node/ opp04; +}; + +&cluster1_opp { + /delete-node/ opp00; + /delete-node/ opp01; + /delete-node/ opp02; + /delete-node/ opp03; + /delete-node/ opp04; + /delete-node/ opp05; + /delete-node/ opp06; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clock-parents = <&clkin_gmac>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + clock_in_out = "input"; + phy-mode = "rgmii"; + phy-supply = <&vcc_lan>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins &gphy_reset>; + rx_delay = <0x20>; + tx_delay = <0x28>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys_s3>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys_s3>; + vddio-supply = <&vcc3v0_s3>; + wakeup-source; + #clock-cells = <1>; + + regulators { + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_sys_s3: DCDC_REG4 { + regulator-name = "vcc1v8_sys_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio_s0: LDO_REG4 { + regulator-name = "vcc_sdio_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v0_s3: LDO_REG8 { + regulator-name = "vcc3v0_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + temp@4c { + compatible = "national,lm75"; + reg = <0x4c>; + }; +}; + +&io_domains { + audio-supply = <&vcc1v8_sys_s0>; + bt656-supply = <&vcc1v8_sys_s0>; + gpio1830-supply = <&vcc3v0_s3>; + sdmmc-supply = <&vcc_sdio_s0>; + status = "okay"; +}; + +&pinctrl { + gmac { + gphy_reset: gphy-reset { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + leds { + sys_grn_led_on: sys-grn-led-on { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + sys_red_led_on: sys-red-led-on { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc3v0-sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc3v0_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vqmmc-supply = <&vcc1v8_sys_s0>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio_s0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 17628f917127..7890bafe5618 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -28,6 +28,22 @@ config TARGET_PINEBOOK_PRO_RK3399 with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, 1920*1080 screen and all the usual laptop features. +config TARGET_HELIOS64 + bool "Kobol Innovations Helios64" + select BOARD_LATE_INIT + help + Helios64 is a Network Attached Storage board based on Rockchip RK3399. + + Key features of the Helios64 include: + * on-board PCIe to 5 Ports SATA Controller JMB585 + * on-board USB 3.0 hub (3x USB 3.0 host) + * USB Type-C (Support DisplayPort Alt Mode) + * on-board 1 Gigabit Ethernet + * on-board 2.5 Gigabit Ethernet (Realtek RTL8156) + * on-board eMMC + * on-board LPDDR4 + * SPI, I2C, UART, GPIO + config TARGET_PUMA_RK3399 bool "Theobroma Systems RK3399-Q7 (Puma)" help @@ -153,6 +169,7 @@ endif # BOOTCOUNT_LIMIT source "board/firefly/roc-pc-rk3399/Kconfig" source "board/google/gru/Kconfig" +source "board/kobol/helios64/Kconfig" source "board/pine64/pinebook-pro-rk3399/Kconfig" source "board/pine64/rockpro64_rk3399/Kconfig" source "board/rockchip/evb_rk3399/Kconfig" diff --git a/board/kobol/helios64/Kconfig b/board/kobol/helios64/Kconfig new file mode 100644 index 000000000000..644cdbd8f314 --- /dev/null +++ b/board/kobol/helios64/Kconfig @@ -0,0 +1,24 @@ +if TARGET_HELIOS64 + +config SYS_BOARD + default "helios64" + +config SYS_VENDOR + default "kobol" + +config SYS_CONFIG_NAME + default "helios64" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +config ENV_SECT_SIZE + default 0x1000 if ENV_IS_IN_SPI_FLASH + +config ENV_SIZE + default 0x8000 + +config ENV_OFFSET + default 0x460000 if ENV_IS_IN_SPI_FLASH + +endif diff --git a/board/kobol/helios64/MAINTAINERS b/board/kobol/helios64/MAINTAINERS new file mode 100644 index 000000000000..a9c88c79e331 --- /dev/null +++ b/board/kobol/helios64/MAINTAINERS @@ -0,0 +1,6 @@ +HELIOS64 BOARD +M: Aditya Prayoga <aditya(a)kobol.io> +S: Maintained +F: board/kobol/helios64/ +F: include/configs/helios64.h +F: configs/helios64_defconfig diff --git a/board/kobol/helios64/Makefile b/board/kobol/helios64/Makefile new file mode 100644 index 000000000000..ab34245a6d6a --- /dev/null +++ b/board/kobol/helios64/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Aditya Prayoga <aditya(a)kobol.io> + +obj-y := helios64.o sys_otp.o diff --git a/board/kobol/helios64/helios64.c b/board/kobol/helios64/helios64.c new file mode 100644 index 000000000000..1fe948eec4ee --- /dev/null +++ b/board/kobol/helios64/helios64.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Aditya Prayoga (aditya(a)kobol.io) + */ + +#include <common.h> +#include <dm.h> +#include <env.h> +#include <log.h> +#include <led.h> +#include <pci.h> +#include <power/regulator.h> +#include <scsi.h> +#include <spl_gpio.h> +#include <syscon.h> +#include <usb.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/gpio.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/misc.h> +#include <asm/arch-rockchip/periph.h> + +#include "sys_otp.h" + +#ifndef CONFIG_TPL_BUILD +int board_early_init_f(void) +{ +#ifdef CONFIG_SPL_BUILD +#define GPIO0_BASE 0xff720000 +#define GRF_BASE 0xff770000 + struct rk3399_grf_regs * const grf = (void *)GRF_BASE; + struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; + + /* Turn ON status LED. At this stage, FDT & DM is not initialized yet */ + spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); +#endif + return 0; +} +#endif + +#ifndef CONFIG_SPL_BUILD +int board_early_init_r(void) +{ + read_otp_data(); + return 0; +} +#endif + +#ifdef CONFIG_MISC_INIT_R +#define GRF_IO_VSEL_BT565_SHIFT 0 +#define GRF_IO_VSEL_AUDIO_SHIFT 1 +#define GRF_IO_VSEL_SDMMC_SHIFT 2 +#define GRF_IO_VSEL_GPIO1830_SHIFT 3 + +#define PMUGRF_CON0_VSEL_SHIFT 8 +#define PMUGRF_CON0_PMU1830_VOL_SHIFT 9 +static void setup_iodomain(void) +{ + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + struct rk3399_pmugrf_regs *pmugrf = + syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); + + /* AUDIO is in 1.8v domain */ + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_AUDIO_SHIFT); + + /* SDMMC is in 3.0v domain */ + rk_setreg(&grf->io_vsel, 0 << GRF_IO_VSEL_SDMMC_SHIFT); + + /* GPIO1830 is in 3.0v domain */ + rk_setreg(&grf->io_vsel, 0 << GRF_IO_VSEL_GPIO1830_SHIFT); + + /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ + rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); + rk_setreg(&pmugrf->soc_con0, 0 << PMUGRF_CON0_PMU1830_VOL_SHIFT); +} + +/* + * Swap mmc0 and mmc1 in boot_targets if booted from SD-Card. + * + * If bootsource is uSD-card we can assume that we want to use the + * SD-Card instead of the eMMC as first boot_target for distroboot. + * We only want to swap the defaults and not any custom environment a + * user has set. We exit early if a changed boot_targets environment + * is detected. + */ +static int setup_boottargets(void) +{ + const char *boot_device = + ofnode_read_chosen_string("u-boot,spl-boot-device"); + char *env_default, *env; + + if (!boot_device) { + debug("%s: /chosen/u-boot,spl-boot-device not set\n", + __func__); + return -1; + } + debug("%s: booted from %s\n", __func__, boot_device); + + env_default = env_get_default("boot_targets"); + env = env_get("boot_targets"); + if (!env) { + debug("%s: boot_targets does not exist\n", __func__); + return -1; + } + debug("%s: boot_targets current: %s - default: %s\n", + __func__, env, env_default); + + if (strcmp(env_default, env) != 0) { + debug("%s: boot_targets not default, don't change it\n", + __func__); + return 0; + } + + /* + * Only run, if booting from mmc1 (i.e. /mmc@fe320000) and + * only consider cases where the default boot-order first + * tries to boot from mmc0 (eMMC) and then from mmc1 + * (i.e. external SD). + * + * In other words: the SD card will be moved to earlier in the + * order, if U-Boot was also loaded from the SD-card. + */ + if (!strcmp(boot_device, "/mmc@fe320000")) { + char *mmc0, *mmc1; + + debug("%s: booted from SD-Card\n", __func__); + mmc0 = strstr(env, "mmc0"); + mmc1 = strstr(env, "mmc1"); + + if (!mmc0 || !mmc1) { + debug("%s: only one mmc boot_target found\n", __func__); + return -1; + } + + /* + * If mmc0 comes first in the boot order, we need to change + * the strings to make mmc1 first. + */ + if (mmc0 < mmc1) { + mmc0[3] = '1'; + mmc1[3] = '0'; + debug("%s: set boot_targets to: %s\n", __func__, env); + env_set("boot_targets", env); + } + } + + return 0; +} + +static void setup_leds(void) +{ + struct udevice *dev; + + led_get_by_label("helios64:green:status", &dev); + led_set_state(dev, LEDST_OFF); + mdelay(250); + led_set_state(dev, LEDST_ON); +} + +int misc_init_r(void) +{ + const u32 cpuid_offset = 0x7; + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; + + setup_iodomain(); + set_board_info(); + + ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); + if (ret) + return ret; + + ret = rockchip_cpuid_set(cpuid, cpuid_length); + if (ret) + return ret; + + if (mac_read_from_otp()) + ret = rockchip_setup_macaddr(); + + setup_boottargets(); + setup_leds(); + + return ret; +} +#endif + +#ifdef CONFIG_LAST_STAGE_INIT +static void auto_power_enable(void) +{ + struct gpio_desc *enable, *clock; + + if (gpio_hog_lookup_name("AUTO_ON_EN_D", &enable)) { + debug("Fail to get AUTO_ON_EN_D\n"); + return; + } + + if (gpio_hog_lookup_name("AUTO_ON_EN_CLK", &clock)) { + debug("Fail to get AUTO_ON_EN_CLK\n"); + return; + } + + dm_gpio_set_value(enable, 1); + dm_gpio_set_value(clock, 1); + mdelay(10); + dm_gpio_set_value(clock, 0); +} + +int last_stage_init(void) +{ + auto_power_enable(); + +#ifdef CONFIG_PCI + scsi_scan(true); +#endif + + return 0; +} +#endif + +#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) +int checkboard(void) +{ + int major, minor; + + printf("Revision: "); + + if (!get_revision(&major, &minor)) + printf("%i.%i - %s\n", major, minor, get_variant()); + else + printf("UNKNOWN\n"); + + return 0; +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + char *env; + + env = env_get("board_rev"); + if (env) + fdt_setprop_string(blob, fdt_path_offset(blob, "/"), + "kobol,board-rev", env); + + env = env_get("cpuid#"); + if (env) + fdt_setprop_string(blob, fdt_path_offset(blob, "/"), + "kobol,cpu-id", env); + + return 0; +} +#endif diff --git a/board/kobol/helios64/sys_otp.c b/board/kobol/helios64/sys_otp.c new file mode 100644 index 000000000000..3a27834641bd --- /dev/null +++ b/board/kobol/helios64/sys_otp.c @@ -0,0 +1,248 @@ +#include <linux/types.h> +#include <dm.h> +#include <spi.h> +#include <log.h> +#include <net.h> +#include <u-boot/crc.h> + +#include "sys_otp.h" + +#define OTP_DEVICE_BUS 0 +#define OTP_DEVICE_CS 0 +#define MAX_NUM_PORTS 2 + +enum board_variant { + BOARD_VARIANT_INVALID = 0, + BOARD_VARIANT_ENG_SAMPLE, + BOARD_VARIANT_4G_PROD_NO_ECC, + BOARD_VARIANT_MAX +}; + +struct __attribute__ ((__packed__)) otp_data_t { + u8 magic[8]; + u8 part_num[16]; + u8 variant; + u8 revision; + u8 serial_num[6]; + u8 mfg_year[2]; + u8 mfg_month; + u8 mfg_day; + u8 mac_addr[MAX_NUM_PORTS][6]; + u8 reserved[204]; + u32 checksum; +} otp; + +static struct spi_slave *slave; +static int has_been_read = 0; +static int data_valid = 0; + +static inline int is_data_valid(void) +{ + return data_valid; +} + +static inline int is_valid_header(void) +{ + if ((otp.magic[0] == 'H') || (otp.magic[1] == '6') || + (otp.magic[2] == '4') || (otp.magic[3] == 'N') || + (otp.magic[4] == 'P') || (otp.magic[5] == 'V') || + (otp.magic[6] == '1') || (otp.magic[7] == 0)) + + return 1; + + return 0; +} + +static int init_system_otp(int bus, int cs) +{ + int ret; + char name[30], *str; + struct udevice *dev; + + snprintf(name, sizeof(name), "generic_%d:%d", bus, cs); + str = strdup(name); + if (!str) + return -ENOMEM; + ret = spi_get_bus_and_cs(bus, cs, 25000000, CONFIG_DEFAULT_SPI_MODE, "spi_generic_drv", + str, &dev, &slave); + return ret; +} + +#ifdef DEBUG +/** + * show_otp_data - display the contents of the OTP register + */ +static void show_otp_data(void) +{ + u32 i; + u32 crc; + + const char* var_str[BOARD_VARIANT_MAX] = { + "Invalid variant", + "Engineering Sample", + "Production - 4GB non ECC" + }; + + printf("\n"); + printf("Register dump: (%lu bytes)\n", sizeof(otp)); + for (i = 0; i < sizeof(otp); i++) { + if ((i % 16) == 0) + printf("%02X: ", i); + printf("%02X ", ((u8 *)&otp)[i]); + if (((i % 16) == 15) || (i == sizeof(otp) - 1)) + printf("\n"); + } + + if (!is_valid_header()) + return; + + printf("Part Number: %s\n", otp.part_num); + printf("Variant: %s\n", var_str[otp.variant]); + printf("Revision: %x.%x\n", (otp.revision & 0xf0) >> 4, otp.revision & 0x0f); + printf("Serial Number: %012llx\n", *((uint64_t*) otp.serial_num) & + 0xFFFFFFFFFFFF); + printf("Manufacturing Date: %02X-%02X-%04X (DD-MM-YYYY)\n", otp.mfg_day, + otp.mfg_month, *(u16*) otp.mfg_year); + + printf("1GbE MAC Address: %02X:%02X:%02X:%02X:%02X:%02X\n", + otp.mac_addr[0][0], otp.mac_addr[0][1], otp.mac_addr[0][2], + otp.mac_addr[0][3], otp.mac_addr[0][4], otp.mac_addr[0][5]); + + printf("2.5GbE MAC Address: %02X:%02X:%02X:%02X:%02X:%02X\n", + otp.mac_addr[1][0], otp.mac_addr[1][1], otp.mac_addr[1][2], + otp.mac_addr[1][3], otp.mac_addr[1][4], otp.mac_addr[1][5]); + + crc = crc32(0, (void *)&otp, sizeof(otp) - 4); + + if (crc == le32_to_cpu(otp.checksum)) + printf("CRC: %08x\n\n", le32_to_cpu(otp.checksum)); + else + printf("CRC: %08x (should be %08x)\n\n", + le32_to_cpu(otp.checksum), crc); + +} +#endif + +int read_otp_data(void) +{ + int ret; + u8 dout[5]; + + if (has_been_read) { + if (is_data_valid()) + return 0; + else + goto data_invalid; + } + + ret = init_system_otp(OTP_DEVICE_BUS, OTP_DEVICE_CS); + if (ret) + return ret; + + ret = spi_claim_bus(slave); + if (ret) { + debug("SPI: Failed to claim SPI bus: %d\n", ret); + return ret; + } + + dout[0] = 0x48; + dout[1] = 0x00; + dout[2] = 0x10; /* Security Register #1 */ + dout[3] = 0x00; + dout[4] = 0x00; /* Dummy Byte */ + + ret = spi_write_then_read(slave, dout, sizeof(dout), NULL, (u8 *)&otp, + sizeof(otp)); + + spi_release_bus(slave); +#ifdef DEBUG + show_otp_data(); +#endif + + has_been_read = (ret == 0) ? 1 : 0; + if (!is_valid_header()) + goto data_invalid; + + if (crc32(0, (void *)&otp, sizeof(otp) - 4) == + le32_to_cpu(otp.checksum)) + data_valid = 1; + + if (!is_data_valid()) + goto data_invalid; + + return 0; + +data_invalid: + printf("Invalid board ID data!\n"); + return -1; +} + +int get_revision(int *major, int *minor) +{ + if (!is_data_valid()) + return -1; + + *major = (otp.revision & 0xf0) >> 4; + *minor = otp.revision & 0x0f; + + return 0; +} + +const char *get_variant(void) +{ + const char* var_str[BOARD_VARIANT_MAX] = { + "Unknown", + "Engineering Sample", + "4GB non ECC" + }; + + if ((otp.variant < BOARD_VARIANT_ENG_SAMPLE) || + (otp.variant >= BOARD_VARIANT_MAX)) + return var_str[0]; + + return var_str[otp.variant]; +} + +void set_board_info(void) +{ + char env_str[13]; + + if (!is_data_valid()) + return; + + snprintf(env_str, sizeof(env_str), "%i.%i", (otp.revision & 0xf0) >> 4, otp.revision & 0x0f); + env_set("board_rev", env_str); + + sprintf(env_str, "%012llx", *((uint64_t*) otp.serial_num) & + 0xFFFFFFFFFFFF); + + env_set("serial#", env_str); +} + +int mac_read_from_otp(void) +{ + unsigned int i; + int ret; + + if (!is_data_valid()) + return -1; + + for (i = 0; i < MAX_NUM_PORTS; i++) { + char enetvar[9]; + + sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); + + if (!is_valid_ethaddr(otp.mac_addr[i])) { + debug("Not valid %s!\n", enetvar); + continue; + } + + /* Only initialize environment variables that are blank + * (i.e. have not yet been set) + */ + if (!env_get(enetvar)) + eth_env_set_enetaddr(enetvar, otp.mac_addr[i]); + } + + return ret; +} diff --git a/board/kobol/helios64/sys_otp.h b/board/kobol/helios64/sys_otp.h new file mode 100644 index 000000000000..61f6f3b3809a --- /dev/null +++ b/board/kobol/helios64/sys_otp.h @@ -0,0 +1,10 @@ +#ifndef __HELIOS64_SYS_OTP_H +#define __HELIOS64_SYS_OTP_H + +int read_otp_data(void); +void set_board_info(void); +int get_revision(int *major, int *minor); +const char *get_variant(void); +int mac_read_from_otp(void); + +#endif diff --git a/configs/helios64-rk3399_defconfig b/configs/helios64-rk3399_defconfig new file mode 100644 index 000000000000..6aee24011e45 --- /dev/null +++ b/configs/helios64-rk3399_defconfig @@ -0,0 +1,142 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_HELIOS64=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_CONSOLE_MUX=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-kobol-helios64.dtb" +CONFIG_MISC_INIT_R=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_TYPES=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_LAST_STAGE_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_TPL=y +CONFIG_CMD_CONFIG=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_BOOTEFI_HELLO=y +CONFIG_CMD_BOOTMENU=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MX_CYCLIC=y +CONFIG_CMD_SHA1SUM=y +CONFIG_SHA1SUM_VERIFY=y +CONFIG_CMD_STRINGS=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_READ=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_EXCEPTION=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_FS_UUID=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-kobol-helios64" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_IP_DEFRAG=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_FIRMWARE=y +CONFIG_GPIO_HOG=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0x8 +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_DM_PMIC_FAN53555=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_DM_RESET=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_SYSCON=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_HEXDUMP=y diff --git a/include/configs/helios64.h b/include/configs/helios64.h new file mode 100644 index 000000000000..6fca9a6be0ab --- /dev/null +++ b/include/configs/helios64.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2020 Aditya Prayoga <aditya(a)kobol.io> + */ + +#ifndef __HELIOS64_H +#define __HELIOS64_H + +#include <configs/rk3399_common.h> + +#define SDRAM_BANK_SIZE (2UL << 30) + +#if defined(CONFIG_ENV_IS_IN_MMC) + #define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) + #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS + #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS + #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE + #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + + +#ifndef CONFIG_SPL_BUILD +#if CONFIG_IS_ENABLED(SCSI) + + #define CONFIG_SYS_SCSI_MAX_SCSI_ID 5 + #define CONFIG_SYS_SCSI_MAX_LUN 1 + #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + + #define BOOT_TARGET_SCSI(func) \ + func(SCSI, scsi, 0) +#else + #define BOOT_TARGET_SCSI(func) +#endif + +#undef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_SCSI(func) \ + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) + +#endif + +#endif -- 2.30.0

8 11

[PATCH v6 0/5] rockchip_sfc: add support for Rockchip SFC
by Jon Lin 06 Jul '21

06 Jul '21

Changes in v6: - Fix dma transfer logic - Fix the error of the way to wait for dma transfer finished status Changes in v5: - Support dma transfer - Add CONFIG_IS_ENABLED(CLK) limitation - Support spinand devices - Support SFC ver4 ver5 - Using "rockchip, sfc" as compatible id - Get clock from the index to compatible with those case which's clock-names is not parsed - px30 use "rockchip, sfc" as compatible id Changes in v4: - None Changes in v3: - Added "rockchip_sfc_adjust_op_work()" function from proposed Linux driver to fix potential issue on hardware. Note I never noticed this issue while testing, so I cannot test if it fixed any specific issue for me. - Updated of-compatible string back to "rockchip,sfc" to match what is currently proposed for upstream driver. The hardware itself has multiple versions but a register is present in the hardware that is read by the driver to set version specific functionality. - Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that sfc nodes match what is in upstream. Changes in v2: - Resending due to glitch with patch file truncating final two lines on patch 1/5 and incorrect patch version number on patch 5/5. Changes in v1: - Reworked code to utilize spi-mem framework, and based it closely off of work in progress code for mainline Linux. - Removed DMA, as it didn't offer much performance benefit for booting (in my test cases), added complexity to the code, and interfered with A-TF. - Updated the names of the bindings to match the work in progress Linux code. - Moved alias to u-boot specific device-tree for Odroid Go Advance. Alias is updated with the spi0 node pointing to the SFC to help the sf command as well as facilitate booting from the SFC. - Note 2 below no longer applies, as rebasing this off of upstream code should allow the device to work for NAND, and by utilizing the spi-mem framework it no longer has to extract the parameters Chris Morgan (5): spi: rockchip_sfc: add support for Rockchip SFC rockchip: px30: Add support for using SFC rockchip: px30: add the serial flash controller mtd: spi-nor-ids: Add XTX XT25F128B rockchip: px30: add support for SFC for Odroid Go Advance arch/arm/dts/px30.dtsi | 38 ++ arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 17 + arch/arm/dts/rk3326-odroid-go2.dts | 16 + arch/arm/mach-rockchip/px30/px30.c | 64 ++ drivers/mtd/spi/Kconfig | 6 + drivers/mtd/spi/spi-nor-ids.c | 8 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/rockchip_sfc.c | 643 +++++++++++++++++++++ 9 files changed, 801 insertions(+) create mode 100644 drivers/spi/rockchip_sfc.c -- 2.17.1

2 7

[PATCH] pci: imx: use reset-gpios if defined by device-tree
by Tim Harvey 06 Jul '21

06 Jul '21

If reset-gpio is defined by device-tree use that instead of a board-specific function to toggle PCI reset. The presense of 'reset-gpio' in the device-tree will override calling the weak imx6_pcie_toggle_reset function therefore I've Cc'd all the board maintainers who rely on that function here as I would like to remove that function completely. The only user of a board-specific weak imx6_pcie_toggle_reset is gwventana which I am the maintainer for and once this patch is accepted I will be able to remove that use case and would then like to remove the use of CONFIG_PCIE_IMX_PERST_GPIO completely. I would have preferred implementing this without changing the codepath for the users of CONFIG_PCIE_IMX_PERST_GPIO but that would require passing in the imx_pcie_priv struct to imx6_pcie_toggle_reset which creates a chicken-and-egg scenario as that's currently a weak function for boards to override. Cc: Ian Ray <ian.ray(a)ge.com> (maintainer:GE BX50V3 BOARD) Cc: Sebastian Reichel <sebastian.reichel(a)collabora.com> (maintainer:GE BX50V3 BOARD) Cc: Fabio Estevam <festevam(a)gmail.com> (maintainer:MX6SABRESD BOARD) Cc: Marek Vasut <marex(a)denx.de> (maintainer:NOVENA BOARD) Cc: Soeren Moch <smoch(a)web.de> (maintainer:TBS2910 BOARD) Cc: Silvio Fricke <open-source(a)softing.de> (maintainer:VINING_2000 BOARD) Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- drivers/pci/pcie_imx.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 73875e00db..c28951655d 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -100,6 +100,8 @@ struct imx_pcie_priv { void __iomem *dbi_base; void __iomem *cfg_base; + struct gpio_desc reset_gpio; + bool gpio_active_high; }; /* @@ -584,7 +586,7 @@ __weak int imx6_pcie_toggle_reset(void) return 0; } -static int imx6_pcie_deassert_core_reset(void) +static int imx6_pcie_deassert_core_reset(struct imx_pcie_priv *priv) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -612,7 +614,14 @@ static int imx6_pcie_deassert_core_reset(void) setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); #endif - imx6_pcie_toggle_reset(); + if (dm_gpio_is_valid(&priv->reset_gpio)) { + /* Assert PERST# for 50ms then de-assert */ + dm_gpio_set_value(&priv->reset_gpio, priv->gpio_active_high ? 0 : 1); + mdelay(50); + dm_gpio_set_value(&priv->reset_gpio, priv->gpio_active_high ? 1 : 0); + } else { + imx6_pcie_toggle_reset(); + } return 0; } @@ -625,7 +634,7 @@ static int imx_pcie_link_up(struct imx_pcie_priv *priv) imx6_pcie_assert_core_reset(priv, false); imx6_pcie_init_phy(); - imx6_pcie_deassert_core_reset(); + imx6_pcie_deassert_core_reset(priv); imx_pcie_regions_setup(priv); @@ -787,6 +796,15 @@ static int imx_pcie_dm_probe(struct udevice *dev) { struct imx_pcie_priv *priv = dev_get_priv(dev); + /* if PERST# valid from dt then assert it */ + gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + priv->gpio_active_high = dev_read_bool(dev, "reset-gpio-active-high"); + if (dm_gpio_is_valid(&priv->reset_gpio)) { + dm_gpio_set_value(&priv->reset_gpio, + priv->gpio_active_high ? 0 : 1); + } + return imx_pcie_link_up(priv); } -- 2.17.1

2 2

[PATCH] smbios: Try CONFIG_SYS_ options before using "Unknow" as a value
by Ilias Apalodimas 06 Jul '21

06 Jul '21

SMBIOS entries for manufacturer and board can't be empty, as the spec explicitly requires a value. Instead of passing "Unknown" and "Unknown product" for the manufacturer and product name if the .dts options are missing, try to use CONFIG_SYS_VENDOR and CONFIG_SYS_BOARD respectively. If those are not found either warn the user at runtime and use "Unknown" for both entries. Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- lib/smbios.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/lib/smbios.c b/lib/smbios.c index b52e125eeb14..d1997ce70d19 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -79,8 +79,10 @@ static int smbios_add_string(struct smbios_ctx *ctx, const char *str) int i = 1; char *p = ctx->eos; - if (!*str) + if (!*str) { str = "Unknown"; + log_warning("Empty string found. Please fix your DTS and/or CONFIG_SYS_* options"); + } for (;;) { if (!*p) { @@ -259,10 +261,10 @@ static int smbios_write_type1(ulong *current, int handle, smbios_set_eos(ctx, t->eos); t->manufacturer = smbios_add_prop(ctx, "manufacturer"); if (!t->manufacturer) - t->manufacturer = smbios_add_string(ctx, "Unknown"); + t->manufacturer = smbios_add_string(ctx, CONFIG_SYS_VENDOR); t->product_name = smbios_add_prop(ctx, "product"); if (!t->product_name) - t->product_name = smbios_add_string(ctx, "Unknown Product"); + t->product_name = smbios_add_string(ctx, CONFIG_SYS_BOARD); t->version = smbios_add_prop_si(ctx, "version", SYSINFO_ID_SMBIOS_SYSTEM_VERSION); if (serial_str) { @@ -293,10 +295,10 @@ static int smbios_write_type2(ulong *current, int handle, smbios_set_eos(ctx, t->eos); t->manufacturer = smbios_add_prop(ctx, "manufacturer"); if (!t->manufacturer) - t->manufacturer = smbios_add_string(ctx, "Unknown"); + t->manufacturer = smbios_add_string(ctx, CONFIG_SYS_VENDOR); t->product_name = smbios_add_prop(ctx, "product"); if (!t->product_name) - t->product_name = smbios_add_string(ctx, "Unknown Product"); + t->product_name = smbios_add_string(ctx, CONFIG_SYS_BOARD); t->version = smbios_add_prop_si(ctx, "version", SYSINFO_ID_SMBIOS_BASEBOARD_VERSION); t->asset_tag_number = smbios_add_prop(ctx, "asset-tag"); @@ -322,7 +324,7 @@ static int smbios_write_type3(ulong *current, int handle, smbios_set_eos(ctx, t->eos); t->manufacturer = smbios_add_prop(ctx, "manufacturer"); if (!t->manufacturer) - t->manufacturer = smbios_add_string(ctx, "Unknown"); + t->manufacturer = smbios_add_string(ctx, CONFIG_SYS_VENDOR); t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP; t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; -- 2.32.0.rc0

4 6

[PATCH] rockchip: rk3328: fix booting error for nanopi-r2s
by jason416 06 Jul '21

06 Jul '21

devices can not boot properly during SPL stage by using microSD card which model is SDSQUNC-032G-ZN6MA. U-Boot SPL 2021.04 (Jul 02 2021 - 19:50:12 +0000) Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices change dts and config to support booting from ultra high speed microSD card on nanopi-r2s. Signed-off-by: jason416 <jason416.gm(a)gmail.com> --- arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 4 ++++ arch/arm/dts/rk3328-nanopi-r2s.dts | 2 +- configs/nanopi-r2s-rk3328_defconfig | 4 ++++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi index 9e2ced1541..d5469748a2 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi @@ -33,6 +33,10 @@ u-boot,dm-spl; }; +&vcc_io_sdio { + u-boot,dm-spl; +}; + &gmac2io { snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; snps,reset-active-low; diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts b/arch/arm/dts/rk3328-nanopi-r2s.dts index 5445c5cb3d..452e4764e6 100644 --- a/arch/arm/dts/rk3328-nanopi-r2s.dts +++ b/arch/arm/dts/rk3328-nanopi-r2s.dts @@ -323,7 +323,7 @@ bus-width = <4>; cap-sd-highspeed; disable-wp; - pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>, <&sdmmc0m1_gpio>; pinctrl-names = "default"; sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 52996266a1..a7969bd7ab 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -56,6 +56,10 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=20000000 -- 2.17.1

1 0

[PATCH] sandbox: Support signal handling only when requested
by Simon Glass 06 Jul '21

06 Jul '21

At present if sandbox crashes it prints a message and tries to exit. But with the recently introduced signal handler, it often seems to get stuck in a loop until the stack overflows: Segmentation violation Segmentation violation Segmentation violation Segmentation violation Segmentation violation Segmentation violation Segmentation violation ... The signal handler is only useful for a few tests, as I understand it. Make it optional. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/sandbox/cpu/start.c | 18 +++++++++++++++--- arch/sandbox/include/asm/state.h | 1 + 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index e87365e800d..72fe293e8bc 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -389,6 +389,16 @@ static int sandbox_cmdline_cb_select_unittests(struct sandbox_state *state, } SANDBOX_CMDLINE_OPT_SHORT(select_unittests, 'k', 1, "Select unit tests to run"); +static int sandbox_cmdline_cb_signals(struct sandbox_state *state, + const char *arg) +{ + state->handle_signals = true; + + return 0; +} +SANDBOX_CMDLINE_OPT_SHORT(signals, 'S', 0, + "Handle signals (such as SIGSEGV) in sandbox"); + static void setup_ram_buf(struct sandbox_state *state) { /* Zero the RAM buffer if we didn't read it, to keep valgrind happy */ @@ -472,9 +482,11 @@ int main(int argc, char *argv[]) if (ret) goto err; - ret = os_setup_signal_handlers(); - if (ret) - goto err; + if (state->handle_signals) { + ret = os_setup_signal_handlers(); + if (ret) + goto err; + } #if CONFIG_VAL(SYS_MALLOC_F_LEN) gd->malloc_base = CONFIG_MALLOC_F_ADDR; diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index bca13069824..1c4c571e28d 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -93,6 +93,7 @@ struct sandbox_state { bool ram_buf_read; /* true if we read the RAM buffer */ bool run_unittests; /* Run unit tests */ const char *select_unittests; /* Unit test to run */ + bool handle_signals; /* Handle signals within sandbox */ /* Pointer to information for each SPI bus/cs */ struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS] -- 2.31.0.rc2.261.g7f71774620-goog

3 14

[PATCH 0/3] sunxi: H616: SPI boot support
by Andre Przywara 06 Jul '21

06 Jul '21

The Allwinner H616 supports booting from SPI NOR flash, for which we use our SPL specific SPI driver. Since this uses hardcoded values for clocks, resets and pins, we need to extend it to cover the H616 SoC as well. Patch 1/3 extends the logic that determines the offset of the U-Boot payload, from a fixed value to actually observing the SPL size. Patch 2/3 piggy backs on the existing H6 SPI boot support, to cover the (very similar) H616 as well. The only actual difference between the two is one pin configuration. Patch 3/3 enables SPI boot for the OrangePi Zero 2 board, which comes with a 2MiB SPI flash chip soldered. In my experiments I couldn't actually convince the BROM to load the SPL, it always fell through to FEL mode. I post this series anyway, because: 1) We will need this code in any case, since it loads the rest of U-Boot (and TF-A) from SPI flash. By hacking sunxi-fel I could verify that this part works: the SPL code detected "SPI boot" and booted the rest of the firmware successfully from SPI flash. 2) I would encourage other people to try this, maybe it's just my board that is broken? (I dimly remember booting something some months ago.) The easiest way to flash U-Boot is via sunxi-fel: $ sunxi-fel -v -p spiflash-write 0 u-boot-sunxi-with-spl.bin Cheers, Andre Andre Przywara (3): sunxi: SPL SPI: Allow larger SPL sunxi: SPL SPI: Add SPI boot support for the Allwinner H616 SoC sunxi: OrangePi Zero 2: Enable SPI booting arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/spl_spi_sunxi.c | 37 +++++++++++++++++------------ configs/orangepi_zero2_defconfig | 1 + 3 files changed, 24 insertions(+), 16 deletions(-) -- 2.17.5

2 6