June 2021 - U-Boot

Pull request: u-boot-rockchip-20210606
by Kever Yang 07 Jun '21

07 Jun '21

Hi Tom, Please pull the rockchip updates/fixes: - Maintainer mail address update DENX ci: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/7676 Thanks, - Kever The following changes since commit d8729a114e1e98806cffb87d2dca895f99a0170a: Merge https://source.denx.de/u-boot/custodians/u-boot-riscv (2021-05-31 10:19:14 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-rockchip.git tags/u-boot-rockchip-20210606 for you to fetch changes up to 87f9c08d845b65e8dd301d64ae2692d1e694d8ab: MAINTAINERS: Update maintainer's mail address (2021-06-01 19:57:02 +0800) ---------------------------------------------------------------- Kever Yang (1): MAINTAINERS: Update maintainer's mail address MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

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Please pull u-boot-dm
by Simon Glass 07 Jun '21

07 Jun '21

Hi Tom, https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/7711 The following changes since commit c003d2cd6b415319c3e40db42b48c2815acda3d3: Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2021-06-04 09:34:21 -0400) are available in the Git repository at: git://git.denx.de/u-boot-dm.git tags/dm-pull-6jun21 for you to fetch changes up to 269fa8468df40952d538ac945db3d98a8d44f79e: test: add dm_test_read_resource (2021-06-05 07:35:47 -0600) ---------------------------------------------------------------- Minor fixes for sandbox and handling of dm-ranges ---------------------------------------------------------------- Alper Nebi Yasak (1): pwm: cros_ec: Rename "priv_auto_alloc_size" to "priv_auto" Bin Meng (2): of: addr: Translate 'dma-ranges' for parent nodes missing 'dma-ranges' of: addr: Remove call to dev_count_cells() in of_get_address() Heinrich Schuchardt (1): sandbox: correct determination of the text base Patrick Delaunay (2): net: luton: remove address translation after ofnode_read_resource test: add dm_test_read_resource arch/sandbox/cpu/start.c | 5 ++++- drivers/core/of_addr.c | 12 +++++------- drivers/net/mscc_eswitch/luton_switch.c | 5 +---- drivers/pwm/cros_ec_pwm.c | 2 +- test/dm/test-fdt.c | 33 +++++++++++++++++++++++++++++++++ 5 files changed, 44 insertions(+), 13 deletions(-) Regards, Simon

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Please pull u-boot-video
by Anatolij Gustschin 07 Jun '21

07 Jun '21

Hi Tom, please pull new video patches for v2021.07-rc3. gitlab CI: https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/7704 Thanks! The following changes since commit c003d2cd6b415319c3e40db42b48c2815acda3d3: Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2021-06-04 09:34:21 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-video.git tags/video-for-2021-07-rc3 for you to fetch changes up to 0df6e66c9994869aff0bbed486495fa4a56aed77: pico-imx6ul: disable video after DM_VIDEO conversion deadline (2021-06-05 10:53:25 +0200) ---------------------------------------------------------------- - disable legacy video for brxre1, mx28evk, pico-imx6ul, pxm2 and rut boards after DM_VIDEO conversion deadline ---------------------------------------------------------------- Anatolij Gustschin (5): siemens: rut: disable video after DM_VIDEO conversion deadline siemens: pxm2: disable video after DM_VIDEO conversion deadline mx28evk: disable video after DM_VIDEO conversion deadline brxre1: disable video after DM_VIDEO conversion deadline pico-imx6ul: disable video after DM_VIDEO conversion deadline board/BuR/brxre1/board.c | 9 +++++++++ configs/brxre1_defconfig | 4 ++-- configs/mx28evk_auart_console_defconfig | 6 +++--- configs/mx28evk_defconfig | 6 +++--- configs/mx28evk_nand_defconfig | 6 +++--- configs/mx28evk_spi_defconfig | 6 +++--- configs/pico-dwarf-imx6ul_defconfig | 4 ++-- configs/pico-hobbit-imx6ul_defconfig | 4 ++-- configs/pico-pi-imx6ul_defconfig | 4 ++-- configs/pxm2_defconfig | 4 ++-- configs/rut_defconfig | 5 ++--- 11 files changed, 33 insertions(+), 25 deletions(-)

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[PATCH 1/3] Revert "sama5d3: Fix Galois Field Table offsets"
by Tudor Ambarus 07 Jun '21

07 Jun '21

This reverts commit 786f888b743e9b83c9095cb9b5548ebe2e29afc5. Looks like the datasheet at https://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D3-Series-Data-sheet-… is wrong, and the testing was poorly done, because the PMECC did not raise any error, but also didn't correct any bitflips. Restoring the offsets as they were before, makes the PMECC on sama5d3x capable of correcting bitflips. Fixes: 786f888b74 ("sama5d3: Fix Galois Field Table offsets") Signed-off-by: Tudor Ambarus <tudor.ambarus(a)microchip.com> --- arch/arm/mach-at91/include/mach/sama5d3.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index f4f05676f7..83f18a8148 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -190,8 +190,8 @@ /* * PMECC table in ROM */ -#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 -#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000 +#define ATMEL_PMECC_INDEX_OFFSET_512 0x10000 +#define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000 /* * SAMA5D3 specific prototypes -- 2.25.1

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[PATCH] arm: bootm: wrong lmb region reservation when PRAM is used
by Aleksandar Gerasimovski 07 Jun '21

07 Jun '21

This is a draft patch to describe the problem and to initiate a discussion for solution. PRAM usage is not taken into account when reserving lmb for ARM architecture, this means that predefined PRAM region is reserved by the u-boot and cannot be used by the u-boot users. In our case this bug leads to non functional ramfs boot, as the PRAM and ram rootfs address ranges are getting reserved by the u-boot. It is obvious that here PRAM region is ignored, but my question is is this clear to everyone and expected? Taking board_f.c as reference, when calculating relocation address PRAM area is taken into account so I would expect that to be case here. Here the intention is to reserve unused space at the end of the effective RAM but PRAM is not part of that. Possible solution would be to introduce something like get_effective_memsize here e.g powerpc/lib/bootm.c but then also NR_DRAM_BANKS has to be considered? Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski(a)hitachi-powergrids.com> --- arch/arm/lib/bootm.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 11af9e2..4b06d25 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -54,7 +54,7 @@ static ulong get_sp(void) void arch_lmb_reserve(struct lmb *lmb) { - ulong sp, bank_end; + ulong sp, bank_end, pram = 0; int bank; /* @@ -69,6 +69,11 @@ void arch_lmb_reserve(struct lmb *lmb) sp = get_sp(); debug("## Current stack ends at 0x%08lx ", sp); +#ifdef CONFIG_PRAM + pram = env_get_ulong("pram", 10, CONFIG_PRAM); + pram = pram << 10; /* size is in kB */ +#endif + /* adjust sp by 4K to be safe */ sp -= 4096; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { @@ -76,8 +81,9 @@ void arch_lmb_reserve(struct lmb *lmb) sp < gd->bd->bi_dram[bank].start) continue; /* Watch out for RAM at end of address space! */ + /* @todo: pram obviously wrong if NR_DRAM_BANKS > 1 */ bank_end = gd->bd->bi_dram[bank].start + - gd->bd->bi_dram[bank].size - 1; + gd->bd->bi_dram[bank].size - pram - 1; if (sp > bank_end) continue; if (bank_end > gd->ram_top) -- 1.8.3.1

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[PATCH] mtd: spinand: macronix: Add support for serial NAND flash
by Jaime Liao 07 Jun '21

07 Jun '21

Macronix NAND Flash devices are available in different configurations and densities. MX"35" means SPI NAND MX35"LF"/"UF" , LF means 3V and UF meands 1.8V MX35LF"2G" , 2G means 2Gbits MX35LF2G"E4"/"24"/"14", E4 means internal ECC and Quad I/O(x4) 24 means 8-bit ecc requirement and Quad I/O(x4) 14 means 4-bit ecc requirement and Quad I/O(x4) MX35LF2G14AC is 3V 2Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7926/MX35LF2G14AC,%203V… MX35UF4G24AD/MX35UF2G24AD/MX35UF1G24AD is 1.8V 4Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7980/MX35UF4G24AD,%201.… MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/MX35UF4GE4AD,%201.… MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/MX35UF2GE4AC,%201.… MX35UF2G14AC/MX35UF1G14AC are 1.8V 2G/1Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7931/MX35UF2G14AC,%201.… Validated via normal(default) and QUAD mode by read, erase, read back, on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host(drivers/spi/spi-mxic.c). Signed-off-by: Jaime Liao <jaimeliao(a)mxic.com.tw> --- drivers/mtd/nand/spi/macronix.c | 100 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c index 215f09a..8a33dce 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -114,6 +114,106 @@ static const struct spinand_info macronix_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_INFO("MX35LF2G14AC", 0x20, + NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF4G24AD", 0xb5, + NAND_MEMORG(1, 4096, 256, 64, 2048, 2, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF4GE4AD", 0xb7, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2G14AC", 0xa0, + NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2G24AD", 0xa4, + NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2GE4AD", 0xa6, + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF2GE4AC", 0xa2, + NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1G14AC", 0x90, + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1G24AD", 0x94, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1GE4AD", 0x96, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + SPINAND_INFO("MX35UF1GE4AC", 0x92, + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, + mx35lf1ge4ab_ecc_get_status)), + }; static int macronix_spinand_detect(struct spinand_device *spinand) -- 1.9.1

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U-Boot does not boot from MicroSD card >1 USB storage devices are present
by Eimar Koort 07 Jun '21

07 Jun '21

Hi all, There seems to be a bug in combination with RPI4 and 2 HDD-s are connected over same USB port. When HDD-s are present, then u-boot is not able to boot up OS from SD card. Created a FreeBSD bug report about this issue. However it seems not to be FreeBSD problem, but U-Boot bug instead. I have to mention that all this worked with older RPI4 firmware and U-Boot 2020.10, which came with then Freebsd13-current. Some updates (including rpi firmware update) later it stopped working. Steps to reproduce: take USB HUB, attach 2 or more HDD/usb thumb drives or something like that, connect it to RPI and try to boot up from SD card. Longer reading and much more details can be found here: Newer bug report created by Roger Leigh: https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=256441 And an older one: https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=253983 Regards, -- Eimar Koort ( eimar.koort(a)tutamail.com )

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[PATCH v1 0/3] lpc32xx updates
by Trevor Woerner 07 Jun '21

07 Jun '21

This patch series starts with some lpc32xx-related cleanups, then adds support for a new LPC32XX board: the Embedded Artists LPC3250 DevKit v2 Trevor Woerner (3): lpc32xx: Kconfig: switch to CONFIG_CONS_INDEX lpc32xx: import device tree from Linux arm: lpc32xx: add EA LPC3250 DevKitv2 board support arch/arm/dts/Makefile | 2 + arch/arm/dts/lpc3250-ea3250-u-boot.dtsi | 15 + arch/arm/dts/lpc3250-ea3250.dts | 273 ++++++++++ arch/arm/dts/lpc32xx.dtsi | 508 ++++++++++++++++++ arch/arm/include/asm/arch-lpc32xx/config.h | 4 +- arch/arm/mach-lpc32xx/Kconfig | 4 + arch/arm/mach-lpc32xx/devices.c | 3 +- board/ea/ea-lpc3250devkitv2/Kconfig | 15 + board/ea/ea-lpc3250devkitv2/MAINTAINERS | 9 + board/ea/ea-lpc3250devkitv2/Makefile | 4 + board/ea/ea-lpc3250devkitv2/README.rst | 132 +++++ .../ea-lpc3250devkitv2/ea-lpc3250devkitv2.c | 37 ++ board/timll/devkit3250/devkit3250.c | 2 +- board/timll/devkit3250/devkit3250_spl.c | 2 +- board/work-microwave/work_92105/work_92105.c | 2 +- .../work_92105/work_92105_spl.c | 2 +- configs/devkit3250_defconfig | 2 + configs/ea-lpc3250devkitv2_defconfig | 23 + configs/work_92105_defconfig | 2 + include/configs/devkit3250.h | 5 - include/configs/ea-lpc3250devkitv2.h | 37 ++ include/configs/work_92105.h | 5 - include/dt-bindings/clock/lpc32xx-clock.h | 58 ++ scripts/config_whitelist.txt | 1 - 24 files changed, 1128 insertions(+), 19 deletions(-) create mode 100644 arch/arm/dts/lpc3250-ea3250-u-boot.dtsi create mode 100644 arch/arm/dts/lpc3250-ea3250.dts create mode 100644 arch/arm/dts/lpc32xx.dtsi create mode 100644 board/ea/ea-lpc3250devkitv2/Kconfig create mode 100644 board/ea/ea-lpc3250devkitv2/MAINTAINERS create mode 100644 board/ea/ea-lpc3250devkitv2/Makefile create mode 100644 board/ea/ea-lpc3250devkitv2/README.rst create mode 100644 board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c create mode 100644 configs/ea-lpc3250devkitv2_defconfig create mode 100644 include/configs/ea-lpc3250devkitv2.h create mode 100644 include/dt-bindings/clock/lpc32xx-clock.h -- 2.30.0.rc0

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Re: [PATCH] riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT
by Rick Chen 07 Jun '21

07 Jun '21

> From: Bin Meng <bmeng.cn(a)gmail.com> > Sent: Saturday, June 05, 2021 7:01 AM > To: Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com>; u-boot(a)lists.denx.de > Cc: Bin Meng <bmeng.cn(a)gmail.com> > Subject: [PATCH] riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT > > The doc says CONFIG_SKIP_LOWLEVEL_INIT is in ax25-ae350.h, while actually it is not. Remove it. > > Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> > --- > > doc/board/AndesTech/ax25-ae350.rst | 19 ++++--------------- > 1 file changed, 4 insertions(+), 15 deletions(-) Reviewed-by: Rick Chen <rick(a)andestech.com>

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[PATCH] Revert "mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output"
by Fabio Estevam 07 Jun '21

07 Jun '21

This reverts commit 63756575b42b8b4fb3f59cbbf0cedf03331bc2d2. Since this commit a imx6qdl-pico board boots extremely slowly in both SPL as well as U-Boot proper. Fix this revert for now to avoid such regression. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- drivers/mmc/fsl_esdhc_imx.c | 29 ++++++++--------------------- include/fsl_esdhc_imx.h | 2 -- 2 files changed, 8 insertions(+), 23 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index a4675838e58a..b49d5ede2711 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -653,10 +653,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4); #ifdef CONFIG_FSL_USDHC - esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); - ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); - if (ret) - pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); + esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN); #else esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); #endif @@ -668,7 +665,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n"); #ifdef CONFIG_FSL_USDHC - esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); #else esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); #endif @@ -723,14 +720,8 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); struct fsl_esdhc *regs = priv->esdhc_regs; u32 val; - u32 tmp; - int ret; if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { - esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); - ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); - if (ret) - pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); esdhc_write32(&regs->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET); /* @@ -748,7 +739,6 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) pr_warn("HS400 strobe DLL status REF not lock!\n"); if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK)) pr_warn("HS400 strobe DLL status SLV not lock!\n"); - esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); } } @@ -980,18 +970,14 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) #ifdef MMC_SUPPORTS_TUNING if (mmc->clk_disable) { #ifdef CONFIG_FSL_USDHC - u32 tmp; - - esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); - ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); - if (ret) - pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); + esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN); #else esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); #endif } else { #ifdef CONFIG_FSL_USDHC - esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | + VENDORSPEC_CKEN); #else esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); #endif @@ -1067,7 +1053,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) #ifndef CONFIG_FSL_USDHC esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); #else - esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); #endif /* Set the initial clock speed */ @@ -1205,7 +1191,8 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, esdhc_write32(&regs->autoc12err, 0); esdhc_write32(&regs->clktunectrlstatus, 0); #else - esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | + VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); #endif if (priv->vs18_enable) diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index b0920344641c..45ed635a77bf 100644 --- a/include/fsl_esdhc_imx.h +++ b/include/fsl_esdhc_imx.h @@ -39,7 +39,6 @@ #define VENDORSPEC_HCKEN 0x00001000 #define VENDORSPEC_IPGEN 0x00000800 #define VENDORSPEC_INIT 0x20007809 -#define VENDORSPEC_FRC_SDCLK_ON 0x00000100 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) @@ -97,7 +96,6 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) -#define PRSSTAT_SDOFF (0x00000080) #define PRSSTAT_SDSTB (0X00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) -- 2.25.1

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