June 2021 - U-Boot

[PATCH V3] MAINTAINER, git-mailrc: Update the mmc maintainer
by Jaehoon Chung 24 Jun '21

24 Jun '21

Update to me as co-maintainer with Peng. Additionally, update the mmc alias in git-mailrc. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changelog on V2 - keep original alias Changelog on V3 - Update commit-msg - Add Bin's reviewed-by tag --- MAINTAINERS | 1 + doc/git-mailrc | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 86ff5e04a62b..a9257cde4df2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -882,6 +882,7 @@ F: arch/mips/dts/mrvl,cn73xx.dtsi MMC M: Peng Fan <peng.fan(a)nxp.com> +M: Jaehoon Chung <jh80.chung(a)samsung.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-mmc.git F: drivers/mmc/ diff --git a/doc/git-mailrc b/doc/git-mailrc index 34f936f4d83c..dc7b39b32faf 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -119,7 +119,7 @@ alias kerneldoc uboot, marex alias fdt uboot, sjg alias i2c uboot, hs alias kconfig uboot, masahiro -alias mmc uboot, freenix +alias mmc uboot, freenix, jaehoon alias nand uboot alias net uboot, jhersh alias phy uboot, jhersh -- 2.29.0

3 2

[PATCH v1 1/1] test: Include /sbin to the PATH when creating file system
by Andy Shevchenko 24 Jun '21

24 Jun '21

On some distributions the mkfs is under /sbin and /sbin is not set for mere users. Include /sbin to the PATH when creating file system, so that users won't get a scary traceback from Python. Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- test/py/tests/test_fs/conftest.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py index 410a675b9714..7325486cdb1a 100644 --- a/test/py/tests/test_fs/conftest.py +++ b/test/py/tests/test_fs/conftest.py @@ -159,6 +159,10 @@ def mk_fs(config, fs_type, size, id): count = (size + 1048576 - 1) / 1048576 + # Some distributions do not add /sbin to the default PATH, where mkfs lives + if '/sbin' not in os.environ["PATH"].split(os.pathsep): + os.environ["PATH"] += os.pathsep + '/sbin' + try: check_call('rm -f %s' % fs_img, shell=True) check_call('dd if=/dev/zero of=%s bs=1M count=%d' -- 2.30.2

2 1

[PATCH 1/1] malloc: add SPDX license identifiers
by Heinrich Schuchardt 24 Jun '21

24 Jun '21

The original code is in the public domain. Licenses/README states that the general license for U-Boot is GPL 2.0+. So we can mark the malloc code as GPL 2.0+ too. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- common/dlmalloc.c | 10 ++++++++++ include/malloc.h | 9 +++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/common/dlmalloc.c b/common/dlmalloc.c index cf0270a9c1..11729e8c85 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1,3 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This code is based on a version (aka dlmalloc) of malloc/free/realloc written + * by Doug Lea and released to the public domain, as explained at + * http://creativecommons.org/publicdomain/zero/1.0/- + * + * The original code is available at http://gee.cs.oswego.edu/pub/misc/ + * as file malloc-2.6.6.c. + */ + #include <common.h> #include <log.h> #include <asm/global_data.h> diff --git a/include/malloc.h b/include/malloc.h index 024b18be00..1fbaf3755c 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -1,12 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* - A version of malloc/free/realloc written by Doug Lea and released to the - public domain. Send questions/comments/complaints/performance data - to dl(a)cs.oswego.edu + This code is based on a version of malloc/free/realloc written by Doug Lea and + released to the public domain. Send questions/comments/complaints/performance + data to dl(a)cs.oswego.edu * VERSION 2.6.6 Sun Mar 5 19:10:03 2000 Doug Lea (dl at gee) Note: There may be an updated version of this malloc obtainable at - ftp://g.oswego.edu/pub/misc/malloc.c + http://g.oswego.edu/pub/misc/malloc.c Check before installing! * Why use this malloc? -- 2.30.2

2 1

Please pull u-boot-x86
by Bin Meng 24 Jun '21

24 Jun '21

Hi Tom, This PR includes the following changes for v2021.07 release: - x86: Discard .note.gnu.property sections - nvme: Skip block device creation for inactive namespaces - nvme: Convert NVMe doc to reST, and various minor fixes Azure results: PASS https://dev.azure.com/bmeng/GitHub/_build/results?buildId=381&view=results The following changes since commit 1ce892cb1ce970d8ee6ffcecc22351c84e67fca4: azure: Use msys2 20210604 installer for Windows build (2021-06-22 09:06:03 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-x86 for you to fetch changes up to f68d5a66cd53a238d64d79cdd330b4dce17c7197: MAINTAINERS: Add an entry for NVMe (2021-06-23 17:21:14 +0800) ---------------------------------------------------------------- Bin Meng (8): x86: Discard .note.gnu.property sections nvme: Move block dev creation from uclass post_probe() to driver probe() nvme: Skip block device creation for inactive namespaces nvme: Eliminate the offset of one during block dev creation nvme: Drop useless members of 'struct nvme_ns' nvme: Don't clear nvme blk device's priv space doc: develop: Convert README.nvme to reST MAINTAINERS: Add an entry for NVMe David Lamparter (1): nvme: fix for big endian systems Wesley Sheng (2): nvme: Correct the prps per page calculation method nvme: Remove the redundant aqa value setting MAINTAINERS | 8 ++++++++ arch/x86/cpu/u-boot-64.lds | 1 + arch/x86/cpu/u-boot-spl.lds | 1 + arch/x86/cpu/u-boot.lds | 1 + doc/develop/driver-model/index.rst | 1 + doc/{README.nvme => develop/driver-model/nvme.rst} | 25 +++++++++++++++++++------ drivers/nvme/nvme-uclass.c | 30 ------------------------------ drivers/nvme/nvme.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++----------- drivers/nvme/nvme.h | 2 -- 9 files changed, 77 insertions(+), 49 deletions(-) rename doc/{README.nvme => develop/driver-model/nvme.rst} (88%) Regards, Bin

2 1

[Resend PULL] Please pull mmc-2021-6-22
by Peng Fan (OSS) 24 Jun '21

24 Jun '21

Hi Tom, Resend with new mail address that subscribed to u-boot list. Please pull u-boot-mmc. ------------------------------- Revert fsl_esdhc_imx using VENDORSPEC_FRC_SDCLK_ON Fix data read for dw_mmc Increase minimum bus freq for mtk-sd Minor cleanup ------------------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/7909 Thanks, Peng. The following changes since commit 97c8cb524c19f054036efd2b4429273bd503e39c: Merge branch 'network_master' of https://source.denx.de/u-boot/custodians/u-boot-net (2021-06-18 11:18:56 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-mmc.git tags/mmc-2021-6-22 for you to fetch changes up to f132aab403271ff00c0cfdd3af6504e87c7d0aaf: Revert "mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output" (2021-06-22 12:03:32 +0800) ---------------------------------------------------------------- Fabio Estevam (1): Revert "mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output" Jaehoon Chung (2): mmc: fsl_esdhc_imx: use mmc_send_cmd instead of dm_mmc_send_cmd mmc: mmc-uclass: change to static about dm function Ley Foon Tan (2): mmc: dw_mmc: Fixes data read when receiving DTO interrupt in FIFO mode mmc: dwmmc: socfpga: Get "fifo-mode" property from DT Reuben Dowle (1): mmc: Update environment variable with active partition Weijie Gao (1): mmc: mtk-sd: increase the minimum bus frequency cmd/mmc.c | 14 +++++++++----- doc/usage/mmc.rst | 4 +++- drivers/mmc/dw_mmc.c | 6 +++--- drivers/mmc/fsl_esdhc_imx.c | 31 +++++++++---------------------- drivers/mmc/mmc-uclass.c | 24 ++++++++++++------------ drivers/mmc/mmc_private.h | 1 - drivers/mmc/mtk-sd.c | 5 +++++ drivers/mmc/socfpga_dw_mmc.c | 2 ++ include/fsl_esdhc_imx.h | 2 -- include/mmc.h | 13 +------------ 10 files changed, 44 insertions(+), 58 deletions(-)

2 1

[PATCH -next] ARM: dts: k3-j7200-common-proc-board-u-boot.dtsi: Fix dtc warnings
by Vignesh Raghavendra 24 Jun '21

24 Jun '21

Fix following dtc warning by explicitly setting up #size-cells and #address-cells when overriding node in -u-boot.dtsi arch/arm/dts/k3-j7200-common-proc-board.dtb: Warning (reg_format): /bus@100000/bus@28380000/mcu-navss/ringacc@2b800000:reg: property has invalid length (80 bytes) (#address-cells == 2, #size-cells == 1) Signed-off-by: Vignesh Raghavendra <vigneshr(a)ti.com> --- arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 41ce9fcb59..786cc48050 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -43,6 +43,8 @@ mcu-navss{ u-boot,dm-spl; + #address-cells = <2>; + #size-cells = <2>; ringacc@2b800000 { reg = <0x0 0x2b800000 0x0 0x400000>, -- 2.32.0

3 3

[PATCH] sunxi: h3: add console support for uart1-3
by Manuel Dipolt 24 Jun '21

24 Jun '21

Add uart1-3 console support for the Allwinner H3 SOC Signed-off-by: Manuel Dipolt <manuel.dipolt(a)robart.cc> --- arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++ arch/arm/mach-sunxi/board.c | 14 ++++++++++++++ include/configs/sunxi-common.h | 5 ++++- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 40a3f845d0..50010071ae 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -148,6 +148,9 @@ enum sunxi_gpio_number { #define SUN6I_GPA_SDC2 5 #define SUN6I_GPA_SDC3 4 #define SUN8I_H3_GPA_UART0 2 +#define SUN8I_H3_GPG_UART1 2 +#define SUN8I_H3_GPA_UART2 2 +#define SUN8I_H3_GPA_UART3 3 #define SUN4I_GPB_PWM 2 #define SUN4I_GPB_TWI0 2 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 8e9bb63d9d..31f780d1b5 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -127,10 +127,24 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I_H3) + sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_H3_GPG_UART1); + sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_H3_GPG_UART1); + sunxi_gpio_set_pull(SUNXI_GPG(6), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) +#if defined(CONFIG_MACH_SUN8I_H3) + sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2); + sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2); + sunxi_gpio_set_pull(SUNXI_GPA(0), SUNXI_GPIO_PULL_UP); +#else sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); +#endif +#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_H3) + sunxi_gpio_set_cfgpin(SUNXI_GPA(14), SUN8I_H3_GPA_UART3); + sunxi_gpio_set_cfgpin(SUNXI_GPA(13), SUN8I_H3_GPA_UART3); + sunxi_gpio_set_pull(SUNXI_GPA(13), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index fceb812448..5b7c310fde 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -246,10 +246,13 @@ extern int soft_i2c_gpio_scl; #else #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28000:115200" #endif -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) +#elif CONFIG_CONS_INDEX == 2 && \ + (defined(CONFIG_MACH_SUN5I) || \defined(CONFIG_MACH_SUN8I_H3)) #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200" #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200" +#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_H3) +#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28C00:115200" #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) #define OF_STDOUT_PATH "/soc@01c00000/serial@01f02800:115200" #else -- 2.20.1

1 0

[PATCH] serial: zynq: Add support for serial parameters
by Kunihiko Hayashi 24 Jun '21

24 Jun '21

This adds serial parameters that include stop bit mode, parity mode, and character length. Mark parity and space parity modes are not supported. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko(a)socionext.com> --- drivers/serial/serial_zynq.c | 64 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 799d524..a644e78 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -28,7 +28,17 @@ #define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */ #define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */ +#define ZYNQ_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ +#define ZYNQ_UART_MR_STOPMODE_1_5_BIT 0x00000040 /* 1.5 stop bits */ +#define ZYNQ_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ + #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ +#define ZYNQ_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ +#define ZYNQ_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ + +#define ZYNQ_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ +#define ZYNQ_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ +#define ZYNQ_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ struct uart_zynq { u32 control; /* 0x0 - Control Register [8:0] */ @@ -137,6 +147,59 @@ static int zynq_serial_setbrg(struct udevice *dev, int baudrate) return 0; } +static int zynq_serial_setconfig(struct udevice *dev, uint serial_config) +{ + struct zynq_uart_plat *plat = dev_get_plat(dev); + struct uart_zynq *regs = plat->regs; + u32 val = 0; + + switch (SERIAL_GET_BITS(serial_config)) { + case SERIAL_6_BITS: + val |= ZYNQ_UART_MR_CHARLEN_6_BIT; + break; + case SERIAL_7_BITS: + val |= ZYNQ_UART_MR_CHARLEN_7_BIT; + break; + case SERIAL_8_BITS: + val |= ZYNQ_UART_MR_CHARLEN_8_BIT; + break; + default: + return -ENOTSUPP; /* not supported in driver */ + } + + switch (SERIAL_GET_STOP(serial_config)) { + case SERIAL_ONE_STOP: + val |= ZYNQ_UART_MR_STOPMODE_1_BIT; + break; + case SERIAL_ONE_HALF_STOP: + val |= ZYNQ_UART_MR_STOPMODE_1_5_BIT; + break; + case SERIAL_TWO_STOP: + val |= ZYNQ_UART_MR_STOPMODE_2_BIT; + break; + default: + return -ENOTSUPP; /* not supported in driver */ + } + + switch (SERIAL_GET_PARITY(serial_config)) { + case SERIAL_PAR_NONE: + val |= ZYNQ_UART_MR_PARITY_NONE; + break; + case SERIAL_PAR_ODD: + val |= ZYNQ_UART_MR_PARITY_ODD; + break; + case SERIAL_PAR_EVEN: + val |= ZYNQ_UART_MR_PARITY_EVEN; + break; + default: + return -ENOTSUPP; /* not supported in driver */ + } + + writel(val, &regs->mode); + + return 0; +} + static int zynq_serial_probe(struct udevice *dev) { struct zynq_uart_plat *plat = dev_get_plat(dev); @@ -198,6 +261,7 @@ static const struct dm_serial_ops zynq_serial_ops = { .pending = zynq_serial_pending, .getc = zynq_serial_getc, .setbrg = zynq_serial_setbrg, + .setconfig = zynq_serial_setconfig, }; static const struct udevice_id zynq_serial_ids[] = { -- 2.7.4

2 4

[PATCH v2] mtd: spinand: macronix: Add support for serial NAND flash
by Jaime Liao 24 Jun '21

24 Jun '21

Change in v2: - remove spinand Flash IDs which are sw-ecc requirement cause sw-ecc function is not supported in u-boot v1: - Add spinand Flash IDs in drivers/mtd/nand/spi/macronix.c Jaime Liao (1): mtd: spinand: macronix: Add support for serial NAND flash drivers/mtd/nand/spi/macronix.c | 46 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) -- 1.9.1

2 2

[PATCH] clock_imx8mq: Added 66 MHz support for QSPI
by Kwon Tae-young 24 Jun '21

24 Jun '21

At the current clock setting, the maximum clock for QSPI is 25 MHz. In my case I use M-RAM which supports up to 100 MHz for QSPI, and with this change the QSPI can be clocked up to 66 MHz. Signed-off-by: Kwon Tae-young <tykwon(a)m2i.co.kr> --- arch/arm/mach-imx/imx8m/clock_imx8mq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 8fecc60ecb..47b4a8f01f 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -473,11 +473,11 @@ int set_clk_qspi(void) { /* * set qspi root - * sys pll1 100M + * sys pll1 266M */ clock_enable(CCGR_QSPI, 0); clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(7)); + CLK_ROOT_SOURCE_SEL(5)); clock_enable(CCGR_QSPI, 1); return 0; -- 2.17.1

3 3