April 2021 - U-Boot

Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages
by Manish Pandey2 12 Apr '21

12 Apr '21

Hi, From TF-A project point of view, we prefer to use existing mechanism to pass parameters across boot stages using linked list of tagged elements (as suggested by Julius). It has support for both generic and SiP-specific tags. Having said that, it does not stop partners to introduce new mechanisms suitable for their usecase in platform port initially and later move to generic code if its suitable for other platforms. To start with, Ampere can introduce a platform specific implementation of memory tag(speed/NUMA topology etc) which can be evaluated and discussed for generalization in future. The tag will be populated in BL2 stage and can be forwarded to further stages(and to BL33) by passing the head of list pointer in one of the registers. Initially any register can be used but going forward a standardization will be needed. The U-boot bloblist mentioned by Simon is conceptually similar to what TF-A is using, if there is consensus of using bloblist/taglist then TF-A tag list may be enhanced to take best of both the implementations. One of the potential problems of having structure used in different projects is maintainability, this can be avoided by having a single copy of these structures in TF-A (kept inside "include/export" which intended to be used by other projects.) Regarding usage of either UUID or tag, I echo the sentiments of Simon and Julius to keep it simple and use tag values. Looking forward to having further discussions on zoom call today. Thanks Manish P ________________________________ From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of Julius Werner via TF-A <tf-a(a)lists.trustedfirmware.org> Sent: 25 March 2021 02:43 To: Simon Glass <sjg(a)chromium.org> Cc: Harb Abdulhamid OS <abdulhamid(a)os.amperecomputing.com>; Boot Architecture Mailman List <boot-architecture(a)lists.linaro.org>; tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org>; U-Boot Mailing List <u-boot(a)lists.denx.de>; Paul Isaac's <paul.isaacs(a)linaro.org>; Ron Minnich <rminnich(a)google.com> Subject: Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages Just want to point out that TF-A currently already supports a (very simple) mechanism like this: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/… https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/… https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/… It's just a linked list of tagged elements. The tag space is split into TF-A-wide generic tags and SiP-specific tags (with plenty of room to spare if more areas need to be defined -- a 64-bit tag can fit a lot). This is currently being used by some platforms that run coreboot in place of BL1/BL2, to pass information from coreboot (BL2) to BL31. I would echo Simon's sentiment of keeping this as simple as possible and avoiding complicated and bloated data structures with UUIDs. You usually want to parse something like this as early as possible in the passed-to firmware stage, particularly if the structure encodes information about the debug console (like it does for the platforms I mentioned above). For example, in BL31 this basically means doing it right after moving from assembly to C in bl31_early_platform_setup2() to get the console up before running anything else. At that point in the BL31 initialization, the MMU and caches are disabled, so data accesses are pretty expensive and you don't want to spend a lot of parsing effort or calculate complicated checksums or the like. You just want something extremely simple where you ideally have to touch every data word only once. On Wed, Mar 24, 2021 at 5:06 PM Simon Glass via TF-A <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>> wrote: Hi Harb, On Wed, 24 Mar 2021 at 11:39, Harb Abdulhamid OS <abdulhamid(a)os.amperecomputing.com<mailto:abdulhamid@os.amperecomputing.com>> wrote: Hello Folks, Appreciate the feedback and replies on this. Glad to see that there is interest in this topic. 😊 I try to address the comments/feedback from Francois and Simon below…. @François Ozog<mailto:francois.ozog@linaro.org> – happy to discuss this on a zoom call. I will make that time slot work, and will be available to attend April 8, 4pm CT. Note that I’m using the term “HOB” here more generically, as there are typically vendor specific structures beyond the resource descriptor HOB, which provides only a small subset of the information that needs to be passed between the boot phases. The whole point here is to provide mechanism to develop firmware that we can build ARM Server SoC’s that support *any* BL33 payload (e.g. EDK2, AptioV, CoreBoot, and maybe even directly boot strapping LinuxBoot at some point). In other-words, we are trying to come up with a TF-A that would be completely agnostic to the implementation of BL33 (i.e. BL33 is built completely independently by a separate entity – e.g. an ODM/OEM). Keep in mind, in the server/datacenter market segment we are not building vertically integrated systems with a single entity compiling firmware/software stacks like most folks in TF-A have become use to. There are two categories of higher level firmware code blobs in the server/datacenter model: 1. “SoC” or “silicon” firmware – in TF-A this may map to BL1, BL2, BL31, and *possibly* one or more BL32 instances 2. “Platform” or “board” firmware – in TF-A this may map to BL33 and *possibly* one or more BL32 instances. Even the platform firmware stack could be further fragmented by having multiple entities involved in delivering the entire firmware stack: IBVs, ODMs, OEMs, CSPs, and possibly even device vendor code. To support a broad range of platform designs with a broad range of memory devices, we need a crisp and clear contract between the SoC firmware that initializes memory (e.g. BL2) and how that platform boot firmware (e.g. BL33) gathers information about what memory that was initialized, at what speeds, NUMA topology, and many other relevant information that needs to be known and comprehended by the platform firmware and eventually by the platform software. I understand the versatility of DT, but I see two major problems with DT: * DT requires more complicated parsing to get properties, and even more complex to dynamically set properties – this HOB structures may need to be generated in boot phases where DDR is not available, and therefore we will be extremely memory constrained. * DT is probably overkill for this purpose – We really just want a list of pointers to simple C structures that code cast (e.g. JEDEC SPD data blob) I think that we should not mix the efforts around DT/ACPI specs with what we are doing here, because those specs and concepts were developed for a completely different purpose (i.e. abstractions needed for OS / RTOS software, and not necessarily suitable for firmware-to-firmware hand-offs). Frankly, I would personally push back pretty hard on defining SMC’s for something that should be one way information passing. Every SMC we add is another attack vector to the secure world and an increased burden on the folks that have to do security auditing and threat analysis. I see no benefit in exposing these boot/HOB/BOB structures at run-time via SMC calls. Please do let me know if you disagree and why. Look forward to discussing on this thread or on the call. @Simon Glass<mailto:sjg@chromium.org> - Thanks for the pointer to bloblist. I briefly reviewed and it seems like a good baseline for what we may be looking for. That being said, I would say that there is some benefit in having some kind of unique identifiers (e.g. UUID or some unique signature) so that we can tie standardized data structures (based on some future TBD specs) to a particular ID. For example, if the TPM driver in BL33 is looking for the TPM structure in the HOB/BOB list, and may not care about the other data blobs. The driver needs a way to identify and locate the blob it cares about. The tag is intended to serve that purpose, although perhaps it should switch from an auto-allocating enum to one with explicit values for each entry and a range for 'local' use. I guess we can achieve this with the tag, but the problem with tag when you have eco-system with a lot of parties doing parallel development, you can end up with tag collisions and folks fighting about who has rights to what tag values. We would need some official process for folks to register tags for whatever new structures we define, or maybe some tag range for vendor specific structures. This comes with a lot of pain and bureaucracy. On the other hand, UUID has been a proven way to make it easy to just define your own blobs with *either* standard or vendor specific structures without worry of ID collisions between vendors. True. I think the pain is overstated, though. In this case I think we actually want something that can be shared between projects and orgs, so some amount of coordination could be considered a benefit. It could just be a github pull request. I find the UUID unfriendly and not just to code size and eyesight! Trying to discover what GUIDs mean or are valid is quite tricky. E.g. see this code: #define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ EFI_GUID(0xd038747c, 0xd00c, 0x4980, \ 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55) (etc.) static struct guid_name { efi_guid_t guid; const char *name; } guid_name[] = { { FSP_HOB_RESOURCE_OWNER_TSEG_GUID, "TSEG" }, { FSP_HOB_RESOURCE_OWNER_FSP_GUID, "FSP" }, { FSP_HOB_RESOURCE_OWNER_SMM_PEI_SMRAM_GUID, "SMM PEI SMRAM" }, { FSP_NON_VOLATILE_STORAGE_HOB_GUID, "NVS" }, { FSP_VARIABLE_NV_DATA_HOB_GUID, "Variable NVS" }, { FSP_GRAPHICS_INFO_HOB_GUID, "Graphics info" }, { FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID1, "PCD database ea" }, { FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID2, "PCD database 9b" }, (never figured out what those two are) { FSP_HOB_RESOURCE_OWNER_PEIM_DXE_GUID, "PEIM Init DXE" }, { FSP_HOB_RESOURCE_OWNER_ALLOC_STACK_GUID, "Alloc stack" }, { FSP_HOB_RESOURCE_OWNER_SMBIOS_MEMORY_GUID, "SMBIOS memory" }, { {}, "zero-guid" }, {} }; static const char *guid_to_name(const efi_guid_t *guid) { struct guid_name *entry; for (entry = guid_name; entry->name; entry++) { if (!guidcmp(guid, &entry->guid)) return entry->name; } return NULL; } Believe it or not it took a fair bit of effort to find just that small list, with nearly every one in a separate doc, from memory. We can probably debate whether there is any value in GUID/UUID or not during the call… but again, boblist seems like a reasonable starting point as an alternative to HOB. Indeed. There is certainly value in both approaches. Regards, Simon Thanks, --Harb From: François Ozog <francois.ozog(a)linaro.org<mailto:francois.ozog@linaro.org>> Sent: Tuesday, March 23, 2021 10:00 AM To: François Ozog <francois.ozog(a)linaro.org<mailto:francois.ozog@linaro.org>>; Ron Minnich <rminnich(a)google.com<mailto:rminnich@google.com>>; Paul Isaac's <paul.isaacs(a)linaro.org<mailto:paul.isaacs@linaro.org>> Cc: Simon Glass <sjg(a)chromium.org<mailto:sjg@chromium.org>>; Harb Abdulhamid OS <abdulhamid(a)os.amperecomputing.com<mailto:abdulhamid@os.amperecomputing.com>>; Boot Architecture Mailman List <boot-architecture(a)lists.linaro.org<mailto:boot-architecture@lists.linaro.org>>; tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org> Subject: Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages +Ron Minnich<mailto:rminnich@google.com> +Paul Isaac's<mailto:paul.isaacs@linaro.org> Adding Ron and Paul because I think this interface should be also benefiting LinuxBoot efforts. On Tue, 23 Mar 2021 at 11:17, François Ozog via TF-A <tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>> wrote: Hi, I propose we cover the topic at the next Trusted Substrate<https://collaborate.linaro.org/display/TS/Trusted+Substrate+Home> zoom call<https://linaro-org.zoom.us/j/94563644892> on April 8th 4pm CET. The agenda: ABI between non-secure firmware and the rest of firmware (EL3, S-EL1, S-EL2, SCP) to adapt hardware description to some runtime conditions. runtime conditions here relates to DRAM size and topology detection, secure DRAM memory carvings, PSCI and SCMI interface publishing. For additional background on existing metadata: UEFI Platform Initialization Specification Version 1.7<https://uefi.org/sites/default/files/resources/PI_Spec_1_7_final_Jan_2019.p…>, 5.5 Resource Descriptor HOB Out of the ResourceType we care about is EFI_RESOURCE_SYSTEM_MEMORY. This HOB lacks memory NUMA attachment or something that could be related to fill SRAT table for ACPI or relevant DT proximity domains. HOB is not consistent accros platforms: some platforms (Arm) lists memory from the booting NUMA node, other platforms (x86) lists all memory from all NUMA nodes. (At least this is the case on the two platforms I tested). There are two proposals to use memory structures from SPL/BLx up to the handover function (as defined in the Device Tree technical report<https://docs.google.com/document/d/1CLkhLRaz_zcCq44DLGmPZQFPbYHOC6nzPowaL0X…>) which can be U-boot (BL33 or just U-Boot in case of SPL/U-Boot scheme) or EDK2. I would propose we also discuss possibility of FF-A interface to actually query information or request actions to be done (this is a model actually used in some SoCs with proprietary SMC calls). Requirements (to be validated): - ACPI and DT hardware descriptions. - agnostic to boot framework (SPL/U-Boot, TF-A/U-Boot, TF-A/EDK2) - agnostic to boot framework (SPL/U-Boot, TF-A/U-Boot, TF-A/EDK2, TF-A/LinuxBoot) - at least allows complete DRAM description and "persistent" usage (reserved areas for secure world or other usages) - support secure world device assignment Cheers FF On Mon, 22 Mar 2021 at 19:56, Simon Glass <sjg(a)chromium.org<mailto:sjg@chromium.org>> wrote: Hi, Can I suggest using bloblist for this instead? It is lightweight, easier to parse, doesn't have GUIDs and is already used within U-Boot for passing info between SPL/U-Boot, etc. Docs here: https://github.com/u-boot/u-boot/blob/master/doc/README.bloblist Header file describes the format: https://github.com/u-boot/u-boot/blob/master/include/bloblist.h Full set of unit tests: https://github.com/u-boot/u-boot/blob/master/test/bloblist.c Regards, Simon On Mon, 22 Mar 2021 at 23:58, François Ozog <francois.ozog(a)linaro.org<mailto:francois.ozog@linaro.org>> wrote: > > +Boot Architecture Mailman List <boot-architecture(a)lists.linaro.org<mailto:boot-architecture@lists.linaro.org>> > > standardization is very much welcomed here and need to accommodate a very > diverse set of situations. > For example, TEE OS may need to pass memory reservations to BL33 or > "capture" a device for the secure world. > > I have observed a number of architectures: > 1) pass information from BLx to BLy in the form of a specific object > 2) BLx called by BLy by a platform specific SMC to get information > 3) BLx called by BLy by a platform specific SMC to perform Device Tree > fixups > > I also imagined a standardized "broadcast" FF-A call so that any firmware > element can either provide information or "do something". > > My understanding of your proposal is about standardizing on architecture 1) > with the HOB format. > > The advantage of the HOB is simplicity but it may be difficult to implement > schemes such as pruning a DT because device assignment in the secure world. > > In any case, it looks feasible to have TF-A and OP-TEE complement the list > of HOBs to pass information downstream (the bootflow). > > It would be good to start with building the comprehensive list of > information that need to be conveyed between firmware elements: > > information. | authoritative entity | reporting entity | information > exchanged: > dram | TFA | TFA | > <format to be detailed, NUMA topology to build the SRAT table or DT > equivalent?> > PSCI | SCP | TFA? | > SCMI | SCP or TEE-OS | TFA? TEE-OS?| > secure SRAM | TFA. | TFA. | > secure DRAM | TFA? TEE-OS? | TFA? TEE-OS? | > other? | | > | > > Cheers > > FF > > > On Mon, 22 Mar 2021 at 09:34, Harb Abdulhamid OS via TF-A < > tf-a(a)lists.trustedfirmware.org<mailto:tf-a@lists.trustedfirmware.org>> wrote: > > > Hello Folks, > > > > > > > > I'm emailing to start an open discussion about the adoption of a concept > > known as "hand-off blocks" or HOB to become a part of the TF-A Firmware > > Framework Architecture (FFA). This is something that is a pretty major > > pain point when it comes to the adoption of TF-A in ARM Server SoC’s > > designed to enable a broad range of highly configurable datacenter > > platforms. > > > > > > > > > > > > What is a HOB (Background)? > > > > --------------------------- > > > > UEFI PI spec describes a particular definition for how HOB may be used for > > transitioning between the PEI and DXE boot phases, which is a good > > reference point for this discussion, but not necessarily the exact solution > > appropriate for TF-A. > > > > > > > > A HOB is simply a dynamically generated data structure passed in between > > two boot phases. This is information that was obtained through discovery > > and needs to be passed forward to the next boot phase *once*, with no API > > needed to call back (e.g. no call back into previous firmware phase is > > needed to fetch this information at run-time - it is simply passed one time > > during boot). > > > > > > > > There may be one or more HOBs passed in between boot phases. If there are > > more than one HOB that needs to be passed, this can be in a form of a "HOB > > table", which (for example) could be a UUID indexed array of pointers to > > HOB structures, used to locate a HOB of interest (based on UUID). In such > > cases, instead of passing a single HOB, the boot phases may rely on passing > > the pointer to the HOB table. > > > > > > > > This has been extremely useful concept to employ on highly configurable > > systems that must rely on flexible discovery mechanisms to initialize and > > boot the system. This is especially helpful when you have multiple > > > > > > > > > > > > Why do we need HOBs in TF-A?: > > > > ----------------------------- > > > > It is desirable that EL3 firmware (e.g. TF-A) built for ARM Server SoC in > > a way that is SoC specific *but* platform agnostic. This means that a > > single ARM SoC that a SiP may deliver to customers may provide a single > > TF-A binary (e.g. BL1, BL2, BL31) that could be used to support a broad > > range of platform designs and configurations in order to boot a platform > > specific firmware (e.g. BL33 and possibly even BL32 code). In order to > > achieve this, the platform configuration must be *discovered* instead of > > statically compiled as it is today in TF-A via device tree based > > enumeration. The mechanisms of discovery may differ broadly depending on > > the relevant industry standard, or in some cases may have rely on SiP > > specific discovery flows. > > > > > > > > For example: On server systems that support a broad range DIMM memory > > population/topologies, all the necessary information required to boot is > > fully discovered via standard JEDEC Serial Presence Detect (SPD) over an > > I2C bus. Leveraging the SPD bus, may platform variants could be supported > > with a single TF-A binary. Not only is this information required to > > initialize memory in early boot phases (e.g. BL2), the subsequent boot > > phases will also need this SPD info to construct a system physical address > > map and properly initialize the MMU based on the memory present, and where > > the memory may be present. Subsequent boot phases (e.g. BL33 / UEFI) may > > need to generate standard firmware tables to the operating systems, such as > > SMBIOS tables describing DIMM topology and various ACPI tables (e.g. SLIT, > > SRAT, even NFIT if NVDIMM's are present). > > > > > > > > In short, it all starts with a standardized or vendor specific discovery > > flow in an early boot stage (e.g. BL1/BL2), followed by the passing of > > information to the next boot stages (e.g. BL31/BL32/BL33). > > > > > > > > Today, every HOB may be a vendor specific structure, but in the future > > there may be benefit of defining standard HOBs. This may be useful for > > memory discovery, passing the system physical address map, enabling TPM > > measured boot, and potentially many other common HOB use-cases. > > > > > > > > It would be extremely beneficial to the datacenter market segment if the > > TF-A community would adopt this concept of information passing between all > > boot phases as opposed to rely solely on device tree enumeration. This is > > not intended to replace device tree, rather intended as an alternative way > > to describe the info that must be discovered and dynamically generated. > > > > > > > > > > > > Conclusion: > > > > ----------- > > > > We are proposing that the TF-A community begin pursuing the adoption of > > HOBs as a mechanism used for information exchange between each boot stage > > (e.g. BL1->BL2, BL2->BL31, BL31->BL32, and BL31->BL33)? Longer term we > > want to explore standardizing some HOB structures for the BL33 phase (e.g. > > UEFI HOB structures), but initially would like to agree on this being a > > useful mechanism used to pass information between each boot stage. > > > > > > > > Thanks, > > > > --Harb > > > > > > > > > > > > > > -- > > TF-A mailing list > > TF-A(a)lists.trustedfirmware.org<mailto:TF-A@lists.trustedfirmware.org> > > https://lists.trustedfirmware.org/mailman/listinfo/tf-a > > > > > -- > François-Frédéric Ozog | *Director Linaro Edge & Fog Computing Group* > T: +33.67221.6485 > francois.ozog(a)linaro.org<mailto:francois.ozog@linaro.org> | Skype: ffozog > _______________________________________________ > boot-architecture mailing list > boot-architecture(a)lists.linaro.org<mailto:boot-architecture@lists.linaro.org> > https://lists.linaro.org/mailman/listinfo/boot-architecture -- [https://drive.google.com/a/linaro.org/uc?id=0BxTAygkus3RgQVhuNHMwUi1mYWc&ex…] François-Frédéric Ozog | Director Linaro Edge & Fog Computing Group T: +33.67221.6485 francois.ozog(a)linaro.org<mailto:francois.ozog@linaro.org> | Skype: ffozog -- TF-A mailing list TF-A(a)lists.trustedfirmware.org<mailto:TF-A@lists.trustedfirmware.org> https://lists.trustedfirmware.org/mailman/listinfo/tf-a -- [https://drive.google.com/a/linaro.org/uc?id=0BxTAygkus3RgQVhuNHMwUi1mYWc&ex…] François-Frédéric Ozog | Director Linaro Edge & Fog Computing Group T: +33.67221.6485 francois.ozog(a)linaro.org<mailto:francois.ozog@linaro.org> | Skype: ffozog -- TF-A mailing list TF-A(a)lists.trustedfirmware.org<mailto:TF-A@lists.trustedfirmware.org> https://lists.trustedfirmware.org/mailman/listinfo/tf-a

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[PATCH 1/2] arm: dts: bcm283x: Add minimal smbios information
by matthias.bgg＠kernel.org 12 Apr '21

12 Apr '21

From: Matthias Brugger <mbrugger(a)suse.com> At present SMBIOS tables are emtpy, which breaks some use-cases that rely on that. Add some minimal information to fullfill this. Signed-off-by: Matthias Brugger <mbrugger(a)suse.com> --- arch/arm/dts/bcm283x-u-boot.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/dts/bcm283x-u-boot.dtsi b/arch/arm/dts/bcm283x-u-boot.dtsi index 68d03627f4..f5235cb083 100644 --- a/arch/arm/dts/bcm283x-u-boot.dtsi +++ b/arch/arm/dts/bcm283x-u-boot.dtsi @@ -6,6 +6,26 @@ * (C) Copyright 2016 Fabian Vogt <fvogt(a)suse.com> */ +/ { + smbios { + compatible = "u-boot,sysinfo-smbios"; + smbios { + system { + manufacturer = "raspberrypi"; + product = "rpi"; + }; + baseboard { + manufacturer = "raspberrypi"; + product = "rpi"; + }; + chassis { + manufacturer = "raspberrypi"; + product = "rpi"; + }; + }; + }; +}; + &uart0 { skip-init; u-boot,dm-pre-reloc; -- 2.30.2

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Weird issue when trying to access to uboot environment from Linux
by gianluca 12 Apr '21

12 Apr '21

Hello, I am facing a strange/weird issue when trying to access to filesystem based (/boot/uboot.env) in STM32MP157c-dk2 evaluation board. Uboot is 2020.07-rc5 from github, the board DEVICETREE is stm32mp157c-dk2, the kernel is from Robert C.Nelson repository (from DigiKey EEWiki) and it is 5.12.0-rc6 with some patches applied during built time. The FSBL1 and FSBL2 and SSBL are written in the specific partitions. The linux filesystem has 3 partitions: /boot (for kernel, devicetrees and uboot.env) as EXT4 filesystem, / (for Debian 11 Bullseye rootfilesystem) and /recoveryfs has a Debian 10 minimal bootstrap configuration. Usually UBoot is looking for the bit 2 of each partition (bootable flag) and look for extlinux.conf configuration. This configuration file is with a couple of entries: > label Linux 5.12.0-rc6-armv7-lpae-x7 > kernel /vmlinuz-5.12.0-rc6-armv7-lpae-x7 > append console=ttySTM0,115200 root=/dev/mmcblk0p6 ro rootfstype=ext4 rootwait noswap mem=512M > fdtdir /dtbs/5.12.0-rc6-armv7-lpae-x7/ > devicetree /dtbs/5.12.0-rc6-armv7-lpae-x7/stm32mp157c-dk2.dtb > label Recovery 5.12.0-rc6-armv7-lpae-x7 > kernel /vmlinuz-5.12.0-rc6-armv7-lpae-x7 > append console=ttySTM0,115200 root=/dev/mmcblk0p5 ro rootfstype=ext4 rootwait noswap mem=512M recovery > fdtdir /dtbs/5.12.0-rc6-armv7-lpae-x7/ > devicetree /dtbs/5.12.0-rc6-armv7-lpae-x7/stm32mp157c-dk2.dtb Linux & Recovery. Linux is Debian 11 Bullseye and Recovery is Debian 10 Minimal Install. My goal at the moment is to add the ethaddr environment variable to the /boot/uboot.env (EXT4) configuration file. Using the u-boot tools with fw_printenv it fails with: > # fw_printenv > Cannot read environment, using default > Cannot read default environment from file The file /etc/fw_env.config has only one entry: /boot/uboot.env 0x0000 0x4000 The file itself is 8192 bytes (0x4000 == 16384) but the fw_env.config is (partially) wrong. I do not know if this extra information are used when accessing a file-system-based u-boot environment anyway. Following strace fw_printenv here is the culprit: > execve("/usr/bin/fw_printenv", ["fw_printenv"], 0xbeaf6770 /* 20 vars */) = 0 > brk(NULL) = 0x92f000 > mmap2(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0xb6fb2000 > access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or directory) > openat(AT_FDCWD, "/etc/ld.so.cache", O_RDONLY|O_LARGEFILE|O_CLOEXEC) = 3 > fstat64(3, {st_mode=S_IFREG|0644, st_size=118003, ...}) = 0 > mmap2(NULL, 118003, PROT_READ, MAP_PRIVATE, 3, 0) = 0xb6f6e000 > close(3) = 0 > openat(AT_FDCWD, "/usr/lib/arm-linux-gnueabihf/libubootenv.so.0.3", O_RDONLY|O_LARGEFILE|O_CLOEXEC) = 3 > read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0(\0\1\0\0\0\320\f\0\0004\0\0\0"..., 512) = 512 > fstat64(3, {st_mode=S_IFREG|0644, st_size=13784, ...}) = 0 > mmap2(NULL, 78040, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0xb6f5a000 > mprotect(0xb6f5d000, 61440, PROT_NONE) = 0 > mmap2(0xb6f6c000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x2000) = 0xb6f6c000 > close(3) = 0 > openat(AT_FDCWD, "/lib/arm-linux-gnueabihf/libz.so.1", O_RDONLY|O_LARGEFILE|O_CLOEXEC) = 3 > read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0(\0\1\0\0\0h\32\0\0004\0\0\0"..., 512) = 512 > fstat64(3, {st_mode=S_IFREG|0644, st_size=75404, ...}) = 0 > mmap2(NULL, 139500, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0xb6f37000 > mprotect(0xb6f49000, 61440, PROT_NONE) = 0 > mmap2(0xb6f58000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x11000) = 0xb6f58000 > close(3) = 0 > openat(AT_FDCWD, "/lib/arm-linux-gnueabihf/libc.so.6", O_RDONLY|O_LARGEFILE|O_CLOEXEC) = 3 > read(3, "\177ELF\1\1\1\3\0\0\0\0\0\0\0\0\3\0(\0\1\0\0\0Y\253\1\0004\0\0\0"..., 512) = 512 > fstat64(3, {st_mode=S_IFREG|0755, st_size=973416, ...}) = 0 > mmap2(NULL, 1042632, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0xb6e38000 > mprotect(0xb6f22000, 61440, PROT_NONE) = 0 > mmap2(0xb6f31000, 16384, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0xe9000) = 0xb6f31000 > mmap2(0xb6f35000, 6344, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0xb6f35000 > close(3) = 0 > set_tls(0xb6fb3580) = 0 > mprotect(0xb6f31000, 8192, PROT_READ) = 0 > mprotect(0xb6f58000, 4096, PROT_READ) = 0 > mprotect(0xb6f6c000, 4096, PROT_READ) = 0 > mprotect(0x431000, 4096, PROT_READ) = 0 > mprotect(0xb6fb4000, 4096, PROT_READ) = 0 > munmap(0xb6f6e000, 118003) = 0 > brk(NULL) = 0x92f000 > brk(0x950000) = 0x950000 Now the interesting stuff: > openat(AT_FDCWD, "/etc/fw_env.config", O_RDONLY) = 3 > fstat64(3, {st_mode=S_IFREG|0644, st_size=36, ...}) = 0 > read(3, "/boot/uboot.env 0x0000 0x4"..., 4096) = 36 > lstat64("/boot", {st_mode=S_IFDIR|0755, st_size=1024, ...}) = 0 > lstat64("/boot/uboot.env", {st_mode=S_IFREG|0755, st_size=8192, ...}) = 0 > stat64("/boot/uboot.env", {st_mode=S_IFREG|0755, st_size=8192, ...}) = 0 > openat(AT_FDCWD, "/boot/uboot.env", O_RDONLY) = 4 > close(4) = 0 > read(3, "", 4096) = 0 > close(3) = 0 > openat(AT_FDCWD, "/var/lock/fw_printenv.lock", O_WRONLY|O_CREAT|O_TRUNC, 0666) = 3 > flock(3, LOCK_EX) = 0 > openat(AT_FDCWD, "/boot/uboot.env", O_RDONLY) = 4 > read(4, "t\310;\372\1altbootcmd=run bootcmd\0arch"..., 16384) = 8192 > close(4) = 0 > write(2, "Cannot read environment, using d"..., 39Cannot read environment, using default > ) = 39 > openat(AT_FDCWD, "/etc/u-boot-initial-env", O_RDONLY) = -1 ENOENT (No such file or directory) > write(2, "Cannot read default environment "..., 42Cannot read default environment from file > ) = 42 > exit_group(-13) = ? > +++ exited with 243 +++ What is happening here? The 16384 when reading read(4, "t\310;"..., 16384) = 8192 is correct? Obvioulsy I do not have a /etc/u-boot-initial-env so this error is a no-go issue. Why I cannot read the environment? This environment is written by u-boot itself when not finding any previous uboot.env at the first boot. This is FSBL1 > U-Boot SPL 2020.07-rc5 (Apr 07 2021 - 17:20:03 +0200) > Model: STMicroelectronics STM32MP157C-DK2 Discovery Board > RAM: DDR3-DDR3L 16bits 533000Khz > Trying to boot from MMC1 > > This is SSBL (U-BOOT) > U-Boot 2020.07-rc5 (Apr 07 2021 - 17:20:03 +0200) > > CPU: STM32MP157CAC Rev.B > Model: STMicroelectronics STM32MP157C-DK2 Discovery Board > Board: stm32mp1 in basic mode (st,stm32mp157c-dk2) > Board: MB1272 Var2.0 Rev.C-01 > DRAM: 512 MiB > Clocks: > - MPU : 650 MHz > - MCU : 208.878 MHz > - AXI : 266.500 MHz > - PER : 24 MHz > - DDR : 533 MHz > NAND: 0 MiB > MMC: STM32 SD/MMC: 0 > Loading Environment from EXT4... ** File not found /uboot.env ** > > ** Unable to read "/uboot.env" from mmc0:4 ** In this case there is NO uboot.env so the warning is normal. > In: serial > Out: serial > Err: serial > Net: eth0: ethernet@5800a000 > Hit any key to stop autoboot: 0 > Boot over mmc0! > Saving Environment to EXT4... File System is consistent Now it saves the uboot.env with some default/board default configurations > update journal finished > done > OK update the filesystem (for journal too) > switch to partitions #0, OK > mmc0 is current device > Scanning mmc 0:4... > Found /extlinux/extlinux.conf > Retrieving file: /extlinux/extlinux.conf > 590 bytes read in 27 ms (20.5 KiB/s) > 1: Linux 5.12.0-rc6-armv7-lpae-x7 Why it found only 1 entry? The file is composed by two entries as above. > Retrieving file: /vmlinuz-5.12.0-rc6-armv7-lpae-x7 > 11526656 bytes read in 516 ms (21.3 MiB/s) > append: console=ttySTM0,115200 root=/dev/mmcblk0p6 ro rootfstype=ext4 rootwait noswap mem=512M > Retrieving file: /dtbs/5.12.0-rc6-armv7-lpae-x7/stm32mp157c-dk2.dtb > 59602 bytes read in 31 ms (1.8 MiB/s) > ## Flattened Device Tree blob at c4000000 > Booting using the fdt blob at 0xc4000000 > Loading Device Tree to cffee000, end cffff8d1 ... OK > > Starting kernel ... And from now on everything is normal / as expected... In u-boot commandline I am unable to change the uboot.env: > STM32MP> setenv ethaddr 00:11:22:33:44:55 > ## Error: Can't overwrite "ethaddr" > ## Error inserting "ethaddr" variable, errno=1 But uboot is able to change the environment in that partition. :-( But it is able to add another entry (for example ethaddr0). When trying to delete ethaddr with: > STM32MP> setenv ethaddr 00:11:22:33:44:55 it fails with: > ## Error: Can't overwrite "ethaddr" > ## Error inserting "ethaddr" variable, errno=1 I tried another command: > STM32MP> env delete ethaddr > ## Error: Can't delete "ethaddr" What's wrong? My first goal is to give this board a particular mac address without writing it on the OTP registers. Is this possible? Where am I wrong? Thank you for any help you give me. Regards, Gianluca -- Eurek s.r.l. | Electronic Engineering | http://www.eurek.it via Celletta 8/B, 40026 Imola, Italy | Phone: +39-(0)542-609120 p.iva 00690621206 - c.f. 04020030377 | Fax: +39-(0)542-609212

1 0

[PATCH 1/1] cmd/exception: support ebreak exception on RISC-V
by Heinrich Schuchardt 12 Apr '21

12 Apr '21

The ebreak instruction should generate a breakpoint exception. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- cmd/riscv/exception.c | 10 ++++++++++ doc/usage/exception.rst | 3 +++ 2 files changed, 13 insertions(+) diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c index 9687cec812..7a08061d12 100644 --- a/cmd/riscv/exception.c +++ b/cmd/riscv/exception.c @@ -8,6 +8,13 @@ #include <common.h> #include <command.h> +static int do_ebreak(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + asm volatile ("ebreak\n"); + return CMD_RET_FAILURE; +} + static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -28,6 +35,8 @@ static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc, } static struct cmd_tbl cmd_sub[] = { + U_BOOT_CMD_MKENT(ebreak, CONFIG_SYS_MAXARGS, 1, do_ebreak, + "", ""), U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned, "", ""), U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined, @@ -37,6 +46,7 @@ static struct cmd_tbl cmd_sub[] = { static char exception_help_text[] = "<ex>\n" " The following exceptions are available:\n" + " ebreak - breakpoint\n" " undefined - illegal instruction\n" " unaligned - load address misaligned\n" ; diff --git a/doc/usage/exception.rst b/doc/usage/exception.rst index db1490f005..27df88bd5c 100644 --- a/doc/usage/exception.rst +++ b/doc/usage/exception.rst @@ -31,6 +31,9 @@ type **RISC-V:** + ebreak + breakpoint exception + unaligned load address misaligned -- 2.31.0

2 1

[PATCH] imx: cmd: use struct cmd_tbl
by Peng Fan (OSS) 12 Apr '21

12 Apr '21

From: Peng Fan <peng.fan(a)nxp.com> cmd_tbl_t is removed, need use struct cmd_tbl Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- arch/arm/mach-imx/cmd_mfgprot.c | 2 +- arch/arm/mach-imx/priblob.c | 2 +- cmd/cmd_fsl_caam.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c index 1430f61909..47ae9bf1eb 100644 --- a/arch/arm/mach-imx/cmd_mfgprot.c +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; * Returns zero on success, CMD_RET_USAGE in case of misuse and negative * on error. */ -static int do_mfgprot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +static int do_mfgprot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { u8 *m_ptr, *dgst_ptr, *c_ptr, *d_ptr, *dst_ptr; char *pubk, *sign, *sel; diff --git a/arch/arm/mach-imx/priblob.c b/arch/arm/mach-imx/priblob.c index e253eddfdc..9b92eae781 100644 --- a/arch/arm/mach-imx/priblob.c +++ b/arch/arm/mach-imx/priblob.c @@ -15,7 +15,7 @@ #include <command.h> #include "../drivers/crypto/fsl_caam_internal.h" -int do_priblob_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_priblob_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { writel((readl(CAAM_SCFGR) & 0xFFFFFFFC) | 3, CAAM_SCFGR); printf("New priblob setting = 0x%x\n", readl(CAAM_SCFGR) & 0x3); diff --git a/cmd/cmd_fsl_caam.c b/cmd/cmd_fsl_caam.c index d41d672320..95133835d7 100644 --- a/cmd/cmd_fsl_caam.c +++ b/cmd/cmd_fsl_caam.c @@ -7,7 +7,7 @@ #include <command.h> #include <fsl_caam.h> -static int do_caam(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_caam(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { int ret, i; -- 2.30.0

1 0

[RFC PATCH] watchdog: base rate-limiting on get_ticks() rather than get_timer()
by Rasmus Villemoes 12 Apr '21

12 Apr '21

On powerpc, get_timer() is implemented using a volatile variable that gets incremented from the decrementer interrupt handler. Hence, when interrupts are disabled, time as measured by get_timer() ceases to pass. Interrupts are necessarily disabled during bootm (see the comment in bootm_disable_interrupts() for why). But after interrupts are disabled, there's still lots of work to do - e.g. decompressing the kernel image to the right load address. Unfortunately, the rate-limiting logic in wdt_uclass.c's watchdog_reset function means that WATCHDOG_RESET() becomes a no-op, since get_timer() never progresses past the next_reset. This, combined with an external gpio-triggered watchdog that must be petted at least every 800ms, means our board gets reset before booting into linux. Now, at least on powerpc, get_ticks() continues to return sensible results whether or not interrupts are enabled. So this fixes the above problem for our board - but I don't know if get_ticks() can be assumed to always work. Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- This is what I had in mind. I also considered making it a config knob (possibly just auto-selected based on $ARCH) whether to use get_timer() or get_ticks(), but that becomes quite ugly. drivers/watchdog/wdt-uclass.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index 4cdb7bd64c..7be4e9b5bc 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -16,14 +16,15 @@ DECLARE_GLOBAL_DATA_PTR; #define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000) -/* - * Reset every 1000ms, or however often is required as indicated by a - * hw_margin_ms property. - */ -static ulong reset_period = 1000; +static u64 ratelimit_ticks; int initr_watchdog(void) { + /* + * Reset every 1000ms, or however often is required as indicated by a + * hw_margin_ms property. + */ + u32 reset_period = 1000; u32 timeout = WATCHDOG_TIMEOUT_SECS; /* @@ -48,6 +49,7 @@ int initr_watchdog(void) 4 * reset_period) / 4; } + ratelimit_ticks = usec_to_tick(reset_period * 1000); wdt_start(gd->watchdog_dev, timeout * 1000, 0); gd->flags |= GD_FLG_WDT_READY; printf("WDT: Started with%s servicing (%ds timeout)\n", @@ -117,17 +119,17 @@ int wdt_expire_now(struct udevice *dev, ulong flags) */ void watchdog_reset(void) { - static ulong next_reset; - ulong now; + static u64 last_reset; + u64 now; /* Exit if GD is not ready or watchdog is not initialized yet */ if (!gd || !(gd->flags & GD_FLG_WDT_READY)) return; /* Do not reset the watchdog too often */ - now = get_timer(0); - if (time_after(now, next_reset)) { - next_reset = now + reset_period; + now = get_ticks(); + if (now - last_reset >= ratelimit_ticks) { + last_reset = now; wdt_reset(gd->watchdog_dev); } } -- 2.23.0

4 12

[PATCH] pwm: sifive: make set_config() and set_enable() work properly
by Vincent Chen 12 Apr '21

12 Apr '21

The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work properly due to the wrong implementations. It will cause the u-boot PWM command to not work as expected. The bugs will be resolved in this patch. Signed-off-by: Vincent Chen <vincent.chen(a)sifive.com> --- drivers/pwm/pwm-sifive.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c index 01212d6..b9813a3 100644 --- a/drivers/pwm/pwm-sifive.c +++ b/drivers/pwm/pwm-sifive.c @@ -38,6 +38,9 @@ #define PWM_SIFIVE_SIZE_PWMCMP 4 #define PWM_SIFIVE_CMPWIDTH 16 +#define PWM_SIFIVE_CHANNEL_ENABLE_VAL 0 +#define PWM_SIFIVE_CHANNEL_DISABLE_VAL 0xffff + DECLARE_GLOBAL_DATA_PTR; struct pwm_sifive_regs { @@ -77,7 +80,7 @@ static int pwm_sifive_set_config(struct udevice *dev, uint channel, */ scale_pow = lldiv((uint64_t)priv->freq * period_ns, 1000000000); scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf); - val |= FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale); + val |= (FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale) | PWM_SIFIVE_PWMCFG_EN_ALWAYS); /* * The problem of output producing mixed setting as mentioned at top, @@ -88,6 +91,7 @@ static int pwm_sifive_set_config(struct udevice *dev, uint channel, num = (u64)duty_ns * (1U << PWM_SIFIVE_CMPWIDTH); frac = DIV_ROUND_CLOSEST_ULL(num, period_ns); frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1); + frac = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - frac; writel(val, priv->base + regs->cfg); writel(frac, priv->base + regs->cmp0 + channel * @@ -100,18 +104,15 @@ static int pwm_sifive_set_enable(struct udevice *dev, uint channel, bool enable) { struct pwm_sifive_priv *priv = dev_get_priv(dev); const struct pwm_sifive_regs *regs = &priv->data->regs; - u32 val; debug("%s: Enable '%s'\n", __func__, dev->name); - if (enable) { - val = readl(priv->base + regs->cfg); - val |= PWM_SIFIVE_PWMCFG_EN_ALWAYS; - writel(val, priv->base + regs->cfg); - } else { - writel(0, priv->base + regs->cmp0 + channel * - PWM_SIFIVE_SIZE_PWMCMP); - } + if (enable) + writel(PWM_SIFIVE_CHANNEL_ENABLE_VAL, priv->base + + regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP); + else + writel(PWM_SIFIVE_CHANNEL_DISABLE_VAL, priv->base + + regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP); return 0; } -- 2.7.4

1 0

[PATCH V2 0/3] arm: omap3: Make functions static when possible
by Adam Ford 12 Apr '21

12 Apr '21

A few functions are defined without being labeled as static to that file. In an effort to keep SPL as small as possible, one function needs to be moved into an #ifdef so it's only enabled when the calling function is available, and all of these can simply be marked as static. Before: text data bss dec hex filename 50988 1053 1888 53929 d2a9 spl/u-boot-spl After: text data bss dec hex filename 50972 1053 1888 53913 d299 spl/u-boot-spl While not significant, a few bytes can be very helpful when SPL is limited. Adam Ford (3): arm: omap3: Make try_unlock_memory() static arm: omap3: Make secureworld_exit() static arm: omap3: Make secure_unlock_mem() static arch/arm/include/asm/arch-omap3/sys_proto.h | 2 -- arch/arm/mach-omap2/omap3/board.c | 21 +++++++++++---------- 2 files changed, 11 insertions(+), 12 deletions(-) -- 2.25.1

2 4

Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core
by Rick Chen 12 Apr '21

12 Apr '21

Hi Sean ,Bin > From: Bin Meng [mailto:bmeng.cn@gmail.com] > Sent: Tuesday, April 06, 2021 5:16 PM > To: Sean Anderson > Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Pragnesh Patel; Bin Meng; Simon Glass; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad Kim; U-Boot Mailing List > Subject: Re: [RFC PATCH v4 1/2] arch: riscv: cpu: Add callback to init each core > > On Sat, Apr 3, 2021 at 6:53 AM Sean Anderson <seanga2(a)gmail.com> wrote: > > > > On 3/30/21 1:26 AM, Green Wan wrote: > > > Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to > > > allow different riscv hart perform setup code for each hart as early > > > as possible. Since all the harts enter the callback, they must be able > > > to run the same setup. > > > > > > Signed-off-by: Green Wan <green.wan(a)sifive.com> > > > --- > > > arch/riscv/cpu/cpu.c | 15 +++++++++++++++ > > > arch/riscv/cpu/start.S | 14 ++++++++++++++ > > > 2 files changed, 29 insertions(+) > > > > > > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c > > > index 85592f5bee..1652e51137 100644 > > > --- a/arch/riscv/cpu/cpu.c > > > +++ b/arch/riscv/cpu/cpu.c > > > @@ -140,3 +140,18 @@ int arch_early_init_r(void) > > > { > > > return riscv_cpu_probe(); > > > } > > > + > > > +/** > > > + * riscv_hart_early_init() - A dummy function called by > > > + * ./arch/riscv/cpu/start.S to allow to disable/enable features of each core. > > > + * For example, turn on or off the functional block of CPU harts. > > > + * > > > + * In a multi-core system, this function must not access shared resources. > > > + * > > > + * Any access to such resources would probably be better done with > > > + * available_harts_lock held. However, I doubt that any such access will be > > > + * necessary. > > > + */ > > > +__weak void riscv_hart_early_init(void) > > > +{ > > > +} > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > > > index 8589509e01..ab73008f23 100644 > > > --- a/arch/riscv/cpu/start.S > > > +++ b/arch/riscv/cpu/start.S > > > @@ -117,6 +117,20 @@ call_board_init_f_0: > > > mv sp, a0 > > > #endif > > > > > > +#if CONFIG_IS_ENABLED(RISCV_MMODE) > > > + /* > > > + * Jump to riscv_hart_early_init() to perform init for each core. Not > > > + * expect to access gd since gd is not initialized. All operations in the > > > + * function should affect core itself only. In multi-core system, any access > > > + * to common resource or registers outside core should be avoided or need a > > > + * protection for multicore. > > > + * > > > + * A dummy implementation is provided in ./arch/riscv/cpu/cpu.c. > > > + */ > > > +call_riscv_hart_early_init: > > > + jal riscv_hart_early_init > > > +#endif > > > + > > > > I wonder if we could move the calls to icache_enable and dcache_enable > > into this function. Though this would have the consequence of enabling > > caches on all harts for CPUs which previously only enabled them for the > > boot hart. I think ax25 is the only CPU which currently does this. Bin, > > would this be an issue? No, they are functions shall be called in different stage about lottery. riscv_hart_early_init() is called before lottery for all harts. It shall not move icache_enable() and dcache_enable() into riscv_hart_early_init(), they are belong to the stage after lottery only for main hart. > > Good catch. I believe AX25 cache support is currently somehow broken? No, AX25 cache support is currently work well. > > I think Rick has to comment on this as he added this via commit: > > commit 52923c6db7f00e0197ec894c8c1bb8a7681974bb > Author: Rick Chen <rick(a)andestech.com> > Date: Wed Nov 7 09:34:06 2018 +0800 > > riscv: cache: Implement i/dcache [status, enable, disable] > > AndeStar RISC-V(V5) provide mcache_ctl register which > can configure I/D cache as enabled or disabled. > > This CSR will be encapsulated by CONFIG_RISCV_NDS. > If you want to configure cache on AndeStar V5 > AE350 platform. YOu can enable [*] AndeStar V5 ISA support > by make menuconfig. > > This approach also provide the expansion when the > vender specific features are going to join in. > > Signed-off-by: Rick Chen <rick(a)andestech.com> > Cc: Greentime Hu <greentime(a)andestech.com> > > The original commit has i/d cache enabled on all harts. But it was > later moved to boot hart due to SMP support. Not all harts will enable i/d cache during startup currently, only main hart will enable i/d cache here. So only main hart will disable i/d cache in cleanup_before_linux(). Thanks, Rick > > However on the cleanup side, it looks only the boot hart calls i/d > cache disable? > > See arch/riscv/cpu/ax25/cpu.c:: cleanup_before_linux() > > Regards, > Bin

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[PATCH 00/57] Enforce DM_MMC migration and remove platforms
by Tom Rini 12 Apr '21

12 Apr '21

Hey all, First, the main point of this series is that after v2021.04 is release I intend to make something like this be merged, along with the series I posted earlier about other block drivers. There's some platforms that I've omitted here as people have said they will update them ASAP and I'm going to pick up those patches before this gets merged. And it's soon enough in the future that I expect the people that haven't posted them yet will be able to in time. Next, I'm going to do another series on top of this to pick another migration that's due by v2019.07, and I'm likely to do DM_PCI to see where that is with these removals taken care of. Finally, I am quite happy to have any of these platforms remain in tree, so long as someone is willing to maintain them. A few of the patches in here are re-posts, and I'll sort that out when applying the other migration. -- Tom

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