April 2021 - U-Boot

[PATCH] Revert "spl: Drop bd_info in the data section"
by xiaobo 20 Apr '21

20 Apr '21

From: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> This reverts commit 38d6b7ebdaee3e0e8426ef1b9df88bdce8ae2e75. struct global_data contains a pointer to the bd_info structure. This pointer was populated spl_set_bd() to a pre-allocated bd_info in the ".data" section. The referenced commit replaced this mechanism to one that uses malloc(). That new mechanism is only used if SPL_ALLOC_BD=y. which very few boards do. The result is that (struct global_data)->bd is NULL in SPL on most platforms. This breaks falcon mode, since arch_fixup_fdt() tries to access (struct global_data)->bd and set the "/memory" node in the devicetree. The result is that the "/memory" node contains garbage values, causing linux to panic() as it sets up the page table. Instead of trying to fix the mess, potentially causing other issues, revert to the code that worked, while this change is reworked. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 5 +---- common/spl/Kconfig | 9 --------- common/spl/spl.c | 20 ++++++++------------ include/spl.h | 10 +--------- 4 files changed, 10 insertions(+), 34 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 5b43a2a231..b3f1148f9d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -41,9 +41,6 @@ u32 spl_boot_device(void) #ifdef CONFIG_SPL_BUILD -/* Define board data structure */ -static struct bd_info bdata __attribute__ ((section(".data"))); - void spl_board_init(void) { #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2) @@ -89,7 +86,7 @@ void board_init_f(ulong dummy) get_clocks(); preloader_console_init(); - gd->bd = &bdata; + spl_set_bd(); #ifdef CONFIG_SYS_I2C #ifdef CONFIG_SPL_I2C_SUPPORT diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 0f528f346f..df5468f1ac 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -113,15 +113,6 @@ config SPL_FSL_PBL Create boot binary having SPL binary in PBI format concatenated with u-boot binary. -config SPL_ALLOC_BD - bool "Allocate memory for bd_info" - default y if X86 || SANDBOX - help - Some boards don't allocate space for this in their board_init_f() - code. In this case U-Boot can allocate space for gd->bd in the - standard SPL flow (board_init_r()). Enable this option to support - this feature. - endmenu config HANDOFF diff --git a/common/spl/spl.c b/common/spl/spl.c index 8c4cd933cf..a0a608fd77 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -55,6 +55,9 @@ binman_sym_declare(ulong, spl, image_pos); binman_sym_declare(ulong, spl, size); #endif +/* Define board data structure */ +static struct bd_info bdata __attribute__ ((section(".data"))); + /* * Board-specific Platform code can reimplement show_boot_progress () if needed */ @@ -490,19 +493,14 @@ static int spl_common_init(bool setup_malloc) return 0; } -int spl_alloc_bd(void) +void spl_set_bd(void) { /* * NOTE: On some platforms (e.g. x86) bdata may be in flash and not * writeable. */ - if (!gd->bd) { - gd->bd = malloc(sizeof(*gd->bd)); - if (!gd->bd) - return -ENOMEM; - } - - return 0; + if (!gd->bd) + gd->bd = &bdata; } int spl_early_init(void) @@ -652,6 +650,8 @@ void board_init_r(gd_t *dummy1, ulong dummy2) debug(">>" SPL_TPL_PROMPT "board_init_r()\n"); + spl_set_bd(); + #if defined(CONFIG_SYS_SPL_MALLOC_START) mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE); @@ -661,10 +661,6 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (spl_init()) hang(); } - if (IS_ENABLED(CONFIG_SPL_ALLOC_BD) && spl_alloc_bd()) { - puts("Cannot alloc bd\n"); - hang(); - } #if !defined(CONFIG_PPC) && !defined(CONFIG_ARCH_MX6) /* * timer_init() does not exist on PPC systems. The timer is initialized diff --git a/include/spl.h b/include/spl.h index 4f6e0e53f5..cee9a42ddb 100644 --- a/include/spl.h +++ b/include/spl.h @@ -357,15 +357,7 @@ u32 spl_mmc_boot_mode(const u32 boot_device); * If not overridden, it is weakly defined in common/spl/spl_mmc.c. */ int spl_mmc_boot_partition(const u32 boot_device); - -/** - * spl_alloc_bd() - Allocate space for bd_info - * - * This sets up the gd->bd pointer by allocating memory for it - * - * @return 0 if OK, -ENOMEM if out of memory - */ -int spl_alloc_bd(void); +void spl_set_bd(void); /** * spl_set_header_raw_uboot() - Set up a standard SPL image structure -- 2.31.1

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[PATCH v3 0/5] sysinfo: Add gpio sysinfo driver
by Sean Anderson 20 Apr '21

20 Apr '21

This series adds a GPIO sysinfo driver using the dm_gpio_get_values_as_int_base3 function. The board revision is mapped based in devicetree properties. This series is based on Simon's GPIO series [1]. [1] https://patchwork.ozlabs.org/project/uboot/list/?series=228126 Changes in v3: - Fix assuming any nonzero return of dev_count_phandle_with_args was an error. - Fix assuming nonzero return from dm_gpio_get_values_as_int_base3 is an error. - Move detected bool into sysinfo_priv struct - Rebase onto u-boot/next - Use SYSINFO_ID_BOARD_MODEL instead of SYSINFO_ID_REVISION Changes in v2: - Document sysinfo_gpio_priv - Enforce sysinfo detect ordering in uclass. Users must still call sysinfo_detect beforehand. - Fix unbalanced brace in sysinfo_gpio_get_int - Modify sysinfo test to check for detect() ordering. - Refactor driver to take advantage of the uclass detect ordering guarantee. - Reorder includes - Set BOARD_HWVERSION to SYSINFO_ID_REVISION, as they represent the same content. - Use enums instead of defines for sysinfo ids Sean Anderson (5): dm: gpio: Fix gpio_get_list_count failing with livetree sysinfo: Use global sysinfo IDs for existing sysinfo drivers sysinfo: Require that sysinfo_detect be called before other methods sysinfo: Add gpio-sysinfo driver test: Add gpio-sysinfo test arch/sandbox/dts/test.dts | 7 + common/spl/spl_fit.c | 4 + .../sysinfo/gpio-sysinfo.txt | 37 +++++ drivers/gpio/gpio-uclass.c | 6 +- drivers/sysinfo/Kconfig | 8 + drivers/sysinfo/Makefile | 1 + drivers/sysinfo/gazerbeam.h | 8 +- drivers/sysinfo/gpio.c | 141 ++++++++++++++++++ drivers/sysinfo/sandbox.h | 2 +- drivers/sysinfo/sysinfo-uclass.c | 29 +++- include/sysinfo.h | 26 ++-- test/dm/Makefile | 1 + test/dm/sysinfo-gpio.c | 69 +++++++++ test/dm/sysinfo.c | 23 +-- 14 files changed, 336 insertions(+), 26 deletions(-) create mode 100644 doc/device-tree-bindings/sysinfo/gpio-sysinfo.txt create mode 100644 drivers/sysinfo/gpio.c create mode 100644 test/dm/sysinfo-gpio.c -- 2.25.1

2 8

Possible USB Mass Storage bug on Xilinx's Zynq
by Bruno L. Albrecht 20 Apr '21

20 Apr '21

Hello people, it's my first post here, so forgive me if I do something wrong. I'll try to be short and clear. I'm developing on an Avnet PicoZed (based on a Xilinx Zynq SoC) and my objective is to expose the eMMC as a Mass Storage Device over an USB Connection. I used the following config flag on defconfig file ( https://github.com/Xilinx/u-boot-xlnx/blob/master/configs/xilinx_zynq_virt_… ): CONFIG_CMD_USB_MASS_STORAGE=y To the Device Tree ( https://github.com/Xilinx/u-boot-xlnx/blob/master/arch/arm/dts/zynq-picozed…) I added the usb configuration: aliases { > <...> > usb0 = &usb0; > }; > &usb0 { > u-boot,dm-pre-reloc; > status = "okay"; > dr_mode = "peripheral"; > }; Compilation goes fine and U-Boot boots fine. The eMMC is correctly recognized. Then I use the following command to initiate the USB Mass Storage: ums 0 mmc 0 When on *Windows*, the command is successful for a brief moment and then the board resets with the following error: Zynq> ums 0 mmc 0 > UMS: LUN 0, dev 0, hwpart 0, sector 0x0, count 0xe30000 > \EP1/in FAIL info=40000080 pg0=3eb393c0 > EP1/in FAIL info=40008080 pg0=3eb3d3c0 > EP1/in FAIL info=d8080 pg0=3eaebdc0 > CACHE: Misaligned operation at range [00000001, 00000041] > CACHE: Misaligned operation at range [00000001, 00000041] > data abort > pc : [<3ff67dec>] lr : [<3ff67dec>] > reloc pc : [<0405cdec>] lr : [<0405cdec>] > sp : 3eae81f0 ip : 00000031 fp : 3ffd957c > r10: 00000001 r9 : 3eaeaed0 r8 : 00000001 > r7 : 3ffd9524 r6 : 00000001 r5 : 3ffd94ec r4 : 3ffd95a4 > r3 : e0001000 r2 : 00000001 r1 : 00000041 r0 : 00000001 > Flags: nZCv IRQs off FIQs off Mode SVC_32 > Code: eaffff7e e2861040 e1a00006 ebfe91a6 (e5963004) > Resetting CPU ... > Since I'm working on a Windows machine, I have a Ubuntu running on a Virtual Machine (VirtualBox). So I made a rule to bypass the USB device that would be created on Windows directly to the Virtual Machine (virtually connected the USB device to my Ubuntu). When I do this, the command works. I can access the eMMC and format it and do whatever I want. If I remove the filter and let Windows enumerate the device, the board resets again. I took a look at the dmesg messages on Ubuntu and found the following (the only unusual messages are in bold): [101436.784042] usb 1-2: new full-speed USB device number 25 using ohci-pci > > *[101437.232208] usb 1-2: config 1 interface 0 altsetting 0 endpoint 0x81 > has invalid maxpacket 512, setting to 64[101437.232210] usb 1-2: config 1 > interface 0 altsetting 0 endpoint 0x2 has invalid maxpacket 512, setting to > 64* > [101437.477816] usb 1-2: New USB device found, idVendor=<custom>, > idProduct=<custom>, bcdDevice= 2.21 > [101437.477818] usb 1-2: New USB device strings: Mfr=1, Product=2, > SerialNumber=0 > [101437.477820] usb 1-2: Product: my product name > [101437.477821] usb 1-2: Manufacturer: my manufacturer > [101437.702297] usb-storage 1-2:1.0: USB Mass Storage device detected > [101437.713954] scsi host3: usb-storage 1-2:1.0 > [101438.976664] scsi 3:0:0:0: Direct-Access Linux UMS disk 0 > ffff PQ: 0 ANSI: 2 > [101438.979158] sd 3:0:0:0: Attached scsi generic sg2 type 0 > [101439.284100] sd 3:0:0:0: [sdb] 14876672 512-byte logical blocks: (7.62 > GB/7.09 GiB) > [101439.468523] sd 3:0:0:0: [sdb] Write Protect is off > [101439.468526] sd 3:0:0:0: [sdb] Mode Sense: 0f 00 00 00 > [101439.653020] sd 3:0:0:0: [sdb] Write cache: enabled, read cache: > enabled, doesn't support DPO or FUA > [101440.759756] sdb: sdb1 > [101441.559083] sd 3:0:0:0: [sdb] Attached SCSI removable disk > Not that it sounds like it would interfere, but the USB from the SoC is connected to an USB Hub (USB2514B), to which other devices are connected and work correctly on both Windows and Linux. Any ideas of what might be happening? Cheers Bruno -- Eng. Bruno Landau Albrecht e-mail: brunolalb(a)gmail.com

3 3

[PATCH] Makefile: fix generating environment file
by Oleksandr Suvorov 20 Apr '21

20 Apr '21

If the CONFIG_USE_DEFAULT_ENV_FILE=y and CONFIG_DEFAULT_ENV_FILE points to the empty environment file, the auto-generated file has wrong syntax so it leads to the compilation failure: In file included from include/env_default.h:115, from env/common.c:29: include/generated/defaultenv_autogenerated.h:1:1: error: expected expression before ‘,’ token 1 | , 0x00 | ^ make[1]: *** [scripts/Makefile.build:266: env/common.o] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1744: env] Error 2 Fix this issue conditionally adding the delimiter ", ". Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov(a)toradex.com> --- Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index e423f6de746..d42168661b3 100644 --- a/Makefile +++ b/Makefile @@ -1853,7 +1853,9 @@ define filechk_defaultenv.h grep -v '^$$' | \ tr '\n' '\0' | \ sed -e 's/\\\x0\s*//g' | \ - xxd -i ; echo ", 0x00" ; ) + xxd -i | \ + sed -r 's/([0-9])$$/\1, /'; \ + echo "0x00" ; ) endef define filechk_dt.h -- 2.31.1

1 0

[PATCH] Add support for Raspberry Pi 3B+(32bit)
by Toshifumi NISHINAGA 20 Apr '21

20 Apr '21

Hello all. I will add rpi_3_32b_plus_defconfig to easy to build u-boot for Raspberry Pi 3B+(32bit). Could you merge this patch? Thanks, Toshifumi NISHINAGA >From 28d13f48761ab7c137a5fdf07c76a857967e3590 Mon Sep 17 00:00:00 2001 From: Toshifumi NISHINAGA <tnishinaga.dev(a)gmail.com> Date: Thu, 15 Apr 2021 16:53:33 +0900 Subject: [PATCH] Add support for Raspberry Pi 3B+(32bit) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It also boots on Raspberry Pi 3B+ using rpi_3_32b_defconfig, but the network card doesn't work. This defconfig is based on rpi_3_32b_defconfig. Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev(a)gmail.com> --- configs/rpi_3_32b_plus_defconfig | 46 ++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 configs/rpi_3_32b_plus_defconfig diff --git a/configs/rpi_3_32b_plus_defconfig b/configs/rpi_3_32b_plus_defconfig new file mode 100644 index 0000000000..d147a46ae7 --- /dev/null +++ b/configs/rpi_3_32b_plus_defconfig @@ -0,0 +1,46 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_BCM283X=y +CONFIG_SYS_TEXT_BASE=0x00008000 +CONFIG_TARGET_RPI_3_32B=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x4000 +CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_MISC_INIT_R=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_FS_UUID=y +CONFIG_OF_EMBED=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_BCM2835=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +# CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_CONSOLE_SCROLL_LINES=10 +CONFIG_PHYS_TO_BUS=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.24.3 (Apple Git-128)

3 6

[PATCH 1/2] riscv: board: Support Openpiton Soc
by Tianrui Wei 20 Apr '21

20 Apr '21

>From b8736bf498afc0d250228b0c29f1b402d0d58361 Mon Sep 17 00:00:00 2001 From: Tianrui Wei <tianrui-wei(a)outlook.com> Date: Mon, 20 April 2021 13:03:25 +0800 Subject: [PATCH 1/2] riscv: board: Support Openpiton Soc This patch enables support for OpenPiton risc-v SoC on Digilent Genesys2 FPGA with dual cores configuration Signed-off-by: Tianrui Wei <tianrui-wei(a)outlook.com> Acked-by: Jonathan Balkind <jbalkind(a)ucsb.edu> --- arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/openpiton-riscv64.dts | 160 +++++++++++++++++++++ board/openpiton/riscv/Kconfig | 42 ++++++ board/openpiton/riscv/MAINTAINERS | 6 + board/openpiton/riscv/Makefile | 5 + board/openpiton/riscv/openpiton-riscv.c | 41 ++++++ configs/openpiton_riscv64_defconfig | 132 +++++++++++++++++ include/configs/openpiton-riscv.h | 58 ++++++++ 9 files changed, 449 insertions(+) create mode 100644 arch/riscv/dts/openpiton-riscv64.dts create mode 100644 board/openpiton/riscv/Kconfig create mode 100644 board/openpiton/riscv/MAINTAINERS create mode 100644 board/openpiton/riscv/Makefile create mode 100644 board/openpiton/riscv/openpiton-riscv.c create mode 100644 configs/openpiton_riscv64_defconfig create mode 100644 include/configs/openpiton-riscv.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 30b05408..79f2b0b9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -23,6 +23,9 @@ config TARGET_SIFIVE_FU540 config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" +config TARGET_OPENPITON_RISCV + bool "Support riscv cores on openpiton SoC" + endchoice config SYS_ICACHE_OFF @@ -57,6 +60,7 @@ source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/fu540/Kconfig" source "board/sipeed/maix/Kconfig" +source "board/openpiton/riscv/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 3a6f96c6..0eb8014b 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb +dtb-$(CONFIG_TARGET_OPENPITON_RISCV) += openpiton-riscv64.dtb targets += $(dtb-y) diff --git a/arch/riscv/dts/openpiton-riscv64.dts b/arch/riscv/dts/openpiton-riscv64.dts new file mode 100644 index 00000000..9ef8280e --- /dev/null +++ b/arch/riscv/dts/openpiton-riscv64.dts @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2021 Tianrui Wei <tianrui-wei(a)outlook.com> */ + +// This dts is for a dual core instance of OpenPiton+Ariane built +// to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files +// are automatically generated by the OpenPiton build system and +// this configuration may not be what you need if your configuration +// is different from the below. + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + compatible = "openpiton,ariane"; + + chosen { + u-boot,dm-pre-reloc; + bootargs = "debug loglevel=9"; + stdout-path = "uart0:115200"; + }; + + aliases { + u-boot,dm-pre-reloc; + console = &uart0; + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + timebase-frequency = <520835>; + + CPU0: cpu@0 { + clock-frequency = <66667000>; + u-boot,dm-pre-reloc; + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "eth, ariane", "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + tlb-split; + // HLIC - hart local interrupt controller + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + CPU1: cpu@1 { + clock-frequency = <66667000>; + u-boot,dm-pre-reloc; + device_type = "cpu"; + reg = <1>; + status = "okay"; + compatible = "eth, ariane", "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + tlb-split; + // HLIC - hart local interrupt controller + CPU1_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + }; + + memory@80000000 { + u-boot,dm-pre-reloc; + device_type = "memory"; + reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >; + }; + + uart0: uart@fff0c2c000 { + u-boot,dm-pre-reloc; + compatible = "ns16550"; + reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >; + clock-frequency = <66667000>; + current-speed = <115200>; + interrupt-parent = <&PLIC0>; + interrupts = <1>; + reg-shift = <0>; + // regs are spaced on 8 bit boundary + }; + + eth: ethernet@fff0d00000 { + compatible = "xlnx,xps-ethernetlite-1.00.a"; + device_type = "network"; + reg = < 0x000000ff 0xf0d00000 0x00000000 0x00100000 >; + interrupt-parent = <&PLIC0>; + interrupts = <2>; + local-mac-address = [ 00 18 3E 02 E3 E5 ]; + phy-handle = <&phy0>; + xlnx,duplex = <0x1>; + xlnx,include-global-buffers = <0x1>; + xlnx,include-internal-loopback = <0x0>; + xlnx,include-mdio = <0x1>; + xlnx,rx-ping-pong = <0x1>; + xlnx,s-axi-id-width = <0x1>; + xlnx,tx-ping-pong = <0x1>; + xlnx,use-internal = <0x0>; + axi_ethernetlite_0_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@1 { + compatible = "ethernet-phy-id001C.C915"; + device_type = "ethernet-phy"; + reg = <1>; + }; + }; + }; + + debug-controller@fff1000000 { + compatible = "riscv,debug-013"; + interrupts-extended = < &CPU0_intc 65535 + &CPU1_intc 65535 >; + reg = < 0x000000ff 0xf1000000 0x00000000 0x00001000 >; + reg-names = "control"; + }; + + sdhci_0: sdhci@0xf000000000 { + u-boot,dm-pre-reloc; + status = "okay"; + compatible = "openpiton,piton-mmc"; + reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >; + }; + clint@fff1020000 { + u-boot,dm-pre-reloc; + compatible = "riscv,clint0"; + interrupts-extended = < &CPU0_intc 3 + &CPU0_intc 7 + &CPU1_intc 3 + &CPU1_intc 7 >; + reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >; + reg-names = "control"; + }; + + PLIC0: plic@fff1100000 { + u-boot,dm-pre-reloc; + #address-cells = <0>; + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = < &CPU0_intc 11 + &CPU0_intc 9 + &CPU1_intc 11 + &CPU1_intc 9 >; + reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >; + riscv,max-priority = <7>; + riscv,ndev = <2>; + }; + +}; + diff --git a/board/openpiton/riscv/Kconfig b/board/openpiton/riscv/Kconfig new file mode 100644 index 00000000..31ae44d5 --- /dev/null +++ b/board/openpiton/riscv/Kconfig @@ -0,0 +1,42 @@ +if TARGET_OPENPITON_RISCV + +config SYS_BOARD + default "riscv" + +config SYS_VENDOR + default "openpiton" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "openpiton-riscv" + +config SYS_TEXT_BASE + default 0x81000000 if SPL + default 0x80000000 if !RISCV_SMODE + default 0x81000000 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x80000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x81000000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_EARLY_INIT_R + select SUPPORT_SPL + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE) + imply CMD_CPU + imply SPL_CPU_SUPPORT + imply SPL_OPENSBI + imply SPL_LOAD_FIT + imply SPL_SMP + imply SPL_MMC + imply SMP + imply SPL_RISCV_MMODE + +endif diff --git a/board/openpiton/riscv/MAINTAINERS b/board/openpiton/riscv/MAINTAINERS new file mode 100644 index 00000000..1db6fb60 --- /dev/null +++ b/board/openpiton/riscv/MAINTAINERS @@ -0,0 +1,6 @@ +Openpiton Riscv Bootloader +M: Tianrui Wei<tianrui-wei(a)outlook.com> +S: Maintained +F: board/openpiton/riscv/ +F: include/configs/openpiton-riscv.h +F: configs/openpiton_riscv_defconfig diff --git a/board/openpiton/riscv/Makefile b/board/openpiton/riscv/Makefile new file mode 100644 index 00000000..8cc20e7c --- /dev/null +++ b/board/openpiton/riscv/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 Tianrui Wei +# Tianrui Wei <tianrui-wei(a)outlook.com> +obj-y += openpiton-riscv.o diff --git a/board/openpiton/riscv/openpiton-riscv.c b/board/openpiton/riscv/openpiton-riscv.c new file mode 100644 index 00000000..5be407e7 --- /dev/null +++ b/board/openpiton/riscv/openpiton-riscv.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 SiFive, Inc + * Copyright (c) 2021 Tianrui Wei + * + * + * Authors: + * Pragnesh Patel <pragnesh.patel(a)sifive.com> + * Tianrui Wei <tianrui-wei(a)outlook.com> + */ +#include <common.h> +#include <init.h> +#include <configs/openpiton-riscv.h> +#include <dm.h> +#include <spl.h> + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{ + u8 i; + u32 boot_devices[] = { + BOOT_DEVICE_MMC1, + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif + +int board_init(void) +{ + return 0; +} diff --git a/configs/openpiton_riscv64_defconfig b/configs/openpiton_riscv64_defconfig new file mode 100644 index 00000000..37aa3c80 --- /dev/null +++ b/configs/openpiton_riscv64_defconfig @@ -0,0 +1,132 @@ +CONFIG_RISCV=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64" +CONFIG_TARGET_OPENPITON_RISCV=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_MISC_INIT_R=n +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SPL_PAYLOAD="" +CONFIG_LIBDISK_SUPPORT=y +CONFIG_NR_CPUS=32 +CONFIG_CMODEL_MEDANY=y +CONFIG_EXPORT=n +CONFIG_HASH=n +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_BANNER_PRINT=n +CONFIG_SPL_CRC32_SUPPORT=n +CONFIG_GENERATE_SMBIOS_TABLE=n +CONFIG_EFI_LOADER=n +CONFIG_LIB_DATA=y +CONFIG_SPL_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_FS_EXT4=y +CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_SPL_OPENSBI=n +CONFIG_SPL_RTC_SUPPORT=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_LEGACY_IMAGE_SUPPORT=n +CONFIG_CMD_NET=n +CONFIG_EFI_PARTITION=y +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=128 +CONFIG_EFI_PARTITION_ENTRIES_OFF=0 +CONFIG_SPL_EFI_PARTITION=y +CONFIG_PARTITION_UUIDS=y +CONFIG_OF_EMBED=y +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_CPU=y +CONFIG_CPU_RISCV=y +CONFIG_MMC=y +CONFIG_DM_MMC=y +CONFIG_SPL_DM_MMC=y +CONFIG_MMC_PITON=y +CONFIG_MMC_QUIRKS=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_NS16550=y +CONFIG_DEBUG_UART_SHIFT=0 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_DEBUG_UART_BASE=0xfff0c2c000 +CONFIG_DEBUG_UART_CLOCK=66667000 +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_MMC_VERBOSE=n +CONFIG_MMC_WRITE=n +CONFIG_MMC_HW_PARTITIONING=n +CONFIG_SYS_RELOC_GD_ENV_ADDR=n +CONFIG_SAVEENV=n +CONFIG_NET=n +CONFIG_SPL_PARTITION_UUIDS=n +CONFIG_CMD_EXT4=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_READ=y +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MMC=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MEMINFO=y +CONFIG_EXPERT=n +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_LEGACY_IMAGE_FORMAT=n +CONFIG_ARCH_FIXUP_FDT_MEMORY=n +CONFIG_MENU=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_PART=y +CONFIG_SHOW_REGS=y +CONFIG_LOG=y +CONFIG_LOGLEVEL=9 +CONFIG_SPL_LOGLEVEL=9 +CONFIG_TPL_LOGLEVEL=9 +CONFIG_SPL_LOG=y +CONFIG_SPL_LOG_MAX_LEVEL=9 +CONFIG_SPL_LOG_CONSOLE=y +CONFIG_LOG_ERROR_RETURN=y +CONFIG_CMD_CPU=n +CONFIG_BOOTM_NETBSD=n +CONFIG_BOOTM_PLAN9=n +CONFIG_BOOTM_RTEMS=n +CONFIG_BOOTM_VXWORKS=n +CONFIG_CMD_RUN=n +CONFIG_CMD_IMI=n +CONFIG_CMD_XIMG=n +CONFIG_CMD_EXPORTENV=n +CONFIG_CMD_IMPORTENV=n +CONFIG_CMD_EDITENV=n +CONFIG_CMD_SAVEENV=n +CONFIG_CMD_CRC32=n +CONFIG_CMD_RANDOM=n +CONFIG_CMD_LZMADEC=n +CONFIG_CMD_UNLZ4=n +CONFIG_CMD_UNZIP=n +CONFIG_CMD_FLASH=n +CONFIG_RANDOM_UUID=n +CONFIG_CMD_LOADB=n +CONFIG_CMD_LOADS=n +CONFIG_CMD_ECHO=n +CONFIG_CMD_ITEST=n +CONFIG_CMD_SOURCE=n +CONFIG_CMD_SETEXPR=n +CONFIG_CMD_BLOCK_CACHE=n +CONFIG_CMD_DATE=n +CONFIG_CMD_SLEEP=n +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_FAT=y +CONFIG_DOS_PARTITION=y +CONFIG_ISO_PARTITION=y +CONFIG_DM_ETH=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=65536 +CONFIG_FS_SQUASHFS=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_MD5=y +CONFIG_ZLIB_UNCOMPRESS=y +CONFIG_SPL_GZIP=y +CONFIG_SPL_ZLIB=y +CONFIG_GETOPT=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_RAM_SIFIVE=n diff --git a/include/configs/openpiton-riscv.h b/include/configs/openpiton-riscv.h new file mode 100644 index 00000000..0f30609b --- /dev/null +++ b/include/configs/openpiton-riscv.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2021 Tianrui Wei + * + * Authors: + * Anup Patel <anup.patel(a)wdc.com> + * Tianrui Wei <tianrui-wei(a)outlook.com> + */ + +#ifndef __OPENPITON_RISCV_CONFIG_H +#define __OPENPITON_RISCV_CONFIG_H + +#include <linux/sizes.h> +#define DEBUG +#ifdef CONFIG_SPL +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x82000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0100000 +#define CONFIG_SPL_STACK (0x80000000 + 0x04000000 - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "boot/fw_payload.bin" +#define CONFIG_SPL_GD_ADDR 0x85000000 +#endif + +/* Environment options */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) +#define CONFIG_SYS_MALLOC_LEN SZ_256M +#define CONFIG_SYS_BOOTM_LEN SZ_256M + +/* ------------------------------------------------- + * Environment + */ +//Disable persistent environment variable storage +#define CONFIG_ENV_IS_NOWHERE 1 + +/* --------------------------------------------------------------------- + * Board boot configuration + */ + +#define CONFIG_EXTRA_ENV_SETTINGS "\0" + +#define CONFIG_USE_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "fdt addr ${fdtcontroladdr}; " \ + "fdt move ${fdtcontroladdr} 0x86000000; " \ + "ext4load mmc 0:1 0x80200000 boot/Image; " \ + "booti 0x80200000 - 0x86000000; " + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#endif/* __CONFIG_H */ -- 2.17.1

2 2

[PATCH] arm: allwinner: r40: update R40 DT files from linux 5.12-rc1
by Ivan Uvarov 20 Apr '21

20 Apr '21

Update R40 .dts{,i} and dt-binding headers to current version from kernel. Files taken from Linux 5.12-rc1 release (commit fe07bfda2fb9cdef8a4d4008a409bb02f35f1bd8) Signed-off-by: Ivan Uvarov <i.uvarov(a)cognitivepilot.com> --- arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 23 +- arch/arm/dts/sun8i-r40.dtsi | 375 ++++++++++++++++-- arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts | 12 +- include/dt-bindings/clock/sun8i-r40-ccu.h | 6 +- .../interrupt-controller/arm-gic.h | 5 +- include/dt-bindings/thermal/thermal.h | 3 +- 6 files changed, 375 insertions(+), 49 deletions(-) diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts index c488aaacbd..a6a1087a0c 100644 --- a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -129,7 +129,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gmac_rgmii_pins>; phy-handle = <&phy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-supply = <&reg_dc1sw>; status = "okay"; }; @@ -164,6 +164,10 @@ #include "axp22x.dtsi" +&ir0 { + status = "okay"; +}; + &mmc0 { vmmc-supply = <&reg_dcdc1>; bus-width = <4>; @@ -201,10 +205,15 @@ &pio { pinctrl-names = "default"; pinctrl-0 = <&clk_out_a_pin>; + vcc-pa-supply = <&reg_aldo2>; + vcc-pc-supply = <&reg_dcdc1>; + vcc-pd-supply = <&reg_dcdc1>; + vcc-pe-supply = <&reg_eldo1>; + vcc-pf-supply = <&reg_dcdc1>; + vcc-pg-supply = <&reg_dldo1>; }; &reg_aldo2 { - regulator-always-on; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-name = "vcc-pa"; @@ -218,16 +227,16 @@ }; &reg_dc1sw { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-name = "vcc-gmac-phy"; }; &reg_dcdc1 { regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; }; &reg_dcdc2 { diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi index 06b685869f..d5ad3b9efd 100644 --- a/arch/arm/dts/sun8i-r40.dtsi +++ b/arch/arm/dts/sun8i-r40.dtsi @@ -44,8 +44,10 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r40-ccu.h> +#include <dt-bindings/clock/sun8i-tcon-top.h> #include <dt-bindings/reset/sun8i-r40-ccu.h> #include <dt-bindings/reset/sun8i-de2.h> +#include <dt-bindings/thermal/thermal.h> / { #address-cells = <1>; @@ -78,25 +80,25 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; @@ -109,6 +111,22 @@ status = "disabled"; }; + thermal-zones { + cpu_thermal: cpu0-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + gpu_thermal: gpu-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -118,11 +136,11 @@ display_clocks: clock@1000000 { compatible = "allwinner,sun8i-r40-de2-clk", "allwinner,sun8i-h3-de2-clk"; - reg = <0x01000000 0x100000>; - clocks = <&ccu CLK_DE>, - <&ccu CLK_BUS_DE>; - clock-names = "mod", - "bus"; + reg = <0x01000000 0x10000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; resets = <&ccu RST_BUS_DE>; #clock-cells = <1>; #reset-cells = <1>; @@ -172,6 +190,48 @@ }; }; + deinterlace: deinterlace@1400000 { + compatible = "allwinner,sun8i-r40-deinterlace", + "allwinner,sun8i-h3-deinterlace"; + reg = <0x01400000 0x20000>; + clocks = <&ccu CLK_BUS_DEINTERLACE>, + <&ccu CLK_DEINTERLACE>, + /* + * NOTE: Contrary to what datasheet claims, + * DRAM deinterlace gate doesn't exist and + * it's shared with CSI1. + */ + <&ccu CLK_DRAM_CSI1>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_DEINTERLACE>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mbus 9>; + interconnect-names = "dma-mem"; + }; + + syscon: system-control@1c00000 { + compatible = "allwinner,sun8i-r40-system-control", + "allwinner,sun4i-a10-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun8i-r40-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + nmi_intc: interrupt-controller@1c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; @@ -180,6 +240,69 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-r40-dma", + "allwinner,sun50i-a64-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DMA>; + dma-channels = <16>; + dma-requests = <31>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + + spi0: spi@1c05000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + csi0: csi@1c09000 { + compatible = "allwinner,sun8i-r40-csi0", + "allwinner,sun7i-a20-csi0"; + reg = <0x01c09000 0x1000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI0>; + clock-names = "bus", "isp", "ram"; + resets = <&ccu RST_BUS_CSI0>; + interconnects = <&mbus 5>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + video-codec@1c0e000 { + compatible = "allwinner,sun8i-r40-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_VE>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + allwinner,sram = <&ve_sram 1>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun8i-r40-mmc", "allwinner,sun50i-a64-mmc"; @@ -266,6 +389,38 @@ #phy-cells = <1>; }; + crypto: crypto@1c15000 { + compatible = "allwinner,sun8i-r40-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CE>; + }; + + spi2: spi@1c17000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c17000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ahci: sata@1c18000 { + compatible = "allwinner,sun8i-r40-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; + resets = <&ccu RST_BUS_SATA>; + reset-names = "ahci"; + status = "disabled"; + }; + ehci1: usb@1c19000 { compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; reg = <0x01c19000 0x100>; @@ -312,6 +467,19 @@ status = "disabled"; }; + spi3: spi@1c1f000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c1f000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c20000 0x400>; @@ -322,8 +490,7 @@ }; rtc: rtc@1c20400 { - compatible = "allwinner,sun8i-r40-rtc", - "allwinner,sun8i-h3-rtc"; + compatible = "allwinner,sun8i-r40-rtc"; reg = <0x01c20400 0x400>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clock-output-names = "osc32k", "osc32k-out"; @@ -347,6 +514,20 @@ function = "clk_out_a"; }; + /omit-if-no-ref/ + csi0_8bits_pins: csi0-8bits-pins { + pins = "PE0", "PE2", "PE3", "PE4", "PE5", + "PE6", "PE7", "PE8", "PE9", "PE10", + "PE11"; + function = "csi0"; + }; + + /omit-if-no-ref/ + csi0_mclk_pin: csi0-mclk-pin { + pins = "PE1"; + function = "csi0"; + }; + gmac_rgmii_pins: gmac-rgmii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", @@ -365,6 +546,36 @@ function = "i2c0"; }; + i2c1_pins: i2c1-pins { + pins = "PB18", "PB19"; + function = "i2c1"; + }; + + i2c2_pins: i2c2-pins { + pins = "PB20", "PB21"; + function = "i2c2"; + }; + + i2c3_pins: i2c3-pins { + pins = "PI0", "PI1"; + function = "i2c3"; + }; + + i2c4_pins: i2c4-pins { + pins = "PI2", "PI3"; + function = "i2c4"; + }; + + ir0_pins: ir0-pins { + pins = "PB4"; + function = "ir0"; + }; + + ir1_pins: ir1-pins { + pins = "PB23"; + function = "ir1"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -390,6 +601,36 @@ bias-pull-up; }; + /omit-if-no-ref/ + spi0_pc_pins: spi0-pc-pins { + pins = "PC0", "PC1", "PC2"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi0_cs0_pc_pin: spi0-cs0-pc-pin { + pins = "PC23"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi1_pi_pins: spi1-pi-pins { + pins = "PI17", "PI18", "PI19"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs0_pi_pin: spi1-cs0-pi-pin { + pins = "PI16"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs1_pi_pin: spi1-cs1-pi-pin { + pins = "PI15"; + function = "spi1"; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; @@ -409,6 +650,45 @@ wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + + ir0: ir@1c21800 { + compatible = "allwinner,sun8i-r40-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c21800 0x400>; + pinctrl-0 = <&ir0_pins>; + pinctrl-names = "default"; + clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>; + clock-names = "apb", "ir"; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_BUS_IR0>; + status = "disabled"; + }; + + ir1: ir@1c21c00 { + compatible = "allwinner,sun8i-r40-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c21c00 0x400>; + pinctrl-0 = <&ir1_pins>; + pinctrl-names = "default"; + clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>; + clock-names = "apb", "ir"; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_BUS_IR1>; + status = "disabled"; + }; + + ths: thermal-sensor@1c24c00 { + compatible = "allwinner,sun8i-r40-ths"; + reg = <0x01c24c00 0x100>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_BUS_THS>; + /* TODO: add nvmem-cells for calibration */ + #thermal-sensor-cells = <1>; }; uart0: serial@1c28000 { @@ -518,6 +798,8 @@ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -529,6 +811,8 @@ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -540,6 +824,8 @@ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C3>; resets = <&ccu RST_BUS_I2C3>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -551,22 +837,33 @@ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C4>; resets = <&ccu RST_BUS_I2C4>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - ahci: sata@1c18000 { - compatible = "allwinner,sun8i-r40-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; - resets = <&ccu RST_BUS_SATA>; - resets-name = "ahci"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - + mali: gpu@1c40000 { + compatible = "allwinner,sun8i-r40-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; }; gmac: ethernet@1c50000 { @@ -588,6 +885,16 @@ }; }; + mbus: dram-controller@1c62000 { + compatible = "allwinner,sun8i-r40-mbus"; + reg = <0x01c62000 0x1000>; + clocks = <&ccu 155>; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0x80000000>; + #interconnect-cells = <1>; + }; + tcon_top: tcon-top@1c70000 { compatible = "allwinner,sun8i-r40-tcon-top"; reg = <0x01c70000 0x1000>; @@ -614,12 +921,9 @@ #size-cells = <0>; tcon_top_mixer0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - tcon_top_mixer0_in_mixer0: endpoint@0 { - reg = <0>; + tcon_top_mixer0_in_mixer0: endpoint { remote-endpoint = <&mixer0_out_tcon_top>; }; }; @@ -713,7 +1017,7 @@ compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c73000 0x1000>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; + clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>; clock-names = "ahb", "tcon-ch1"; resets = <&ccu RST_BUS_TCON_TV0>; reset-names = "lcd"; @@ -756,7 +1060,7 @@ compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c74000 0x1000>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>; + clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>; clock-names = "ahb", "tcon-ch1"; resets = <&ccu RST_BUS_TCON_TV1>; reset-names = "lcd"; @@ -798,7 +1102,7 @@ gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, + <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; @@ -818,7 +1122,7 @@ resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; - phy-names = "hdmi-phy"; + phy-names = "phy"; status = "disabled"; ports { @@ -843,7 +1147,7 @@ compatible = "allwinner,sun8i-r40-hdmi-phy"; reg = <0x01ef0000 0x10000>; clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, - <&ccu 7>, <&ccu 16>; + <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>; clock-names = "bus", "mod", "pll-0", "pll-1"; resets = <&ccu RST_BUS_HDMI0>; reset-names = "phy"; @@ -851,6 +1155,15 @@ }; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, diff --git a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts index 15c22b06fc..47954551f5 100644 --- a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts @@ -120,7 +120,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gmac_rgmii_pins>; phy-handle = <&phy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-supply = <&reg_dc1sw>; status = "okay"; }; @@ -198,16 +198,16 @@ }; &reg_dc1sw { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-name = "vcc-gmac-phy"; }; &reg_dcdc1 { regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; }; &reg_dcdc2 { diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h index 4fa5f69fc2..d7337b55a4 100644 --- a/include/dt-bindings/clock/sun8i-r40-ccu.h +++ b/include/dt-bindings/clock/sun8i-r40-ccu.h @@ -43,6 +43,10 @@ #ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_ #define _DT_BINDINGS_CLK_SUN8I_R40_H_ +#define CLK_PLL_VIDEO0 7 + +#define CLK_PLL_VIDEO1 16 + #define CLK_CPU 24 #define CLK_BUS_MIPI_DSI 29 @@ -172,7 +176,7 @@ #define CLK_AVS 152 #define CLK_HDMI 153 #define CLK_HDMI_SLOW 154 - +#define CLK_MBUS 155 #define CLK_DSI_DPHY 156 #define CLK_TVE0 157 #define CLK_TVE1 158 diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h index 1ea1b702fe..35b6f69b7d 100644 --- a/include/dt-bindings/interrupt-controller/arm-gic.h +++ b/include/dt-bindings/interrupt-controller/arm-gic.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * This header provides constants for the ARM GIC. */ @@ -7,14 +8,14 @@ #include <dt-bindings/interrupt-controller/irq.h> -/* interrupt specific cell 0 */ +/* interrupt specifier cell 0 */ #define GIC_SPI 0 #define GIC_PPI 1 /* * Interrupt specifier cell 2. - * The flaggs in irq.h are valid, plus those below. + * The flags in irq.h are valid, plus those below. */ #define GIC_CPU_MASK_RAW(x) ((x) << 8) #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h index b5e6b0069a..bc7babb1a6 100644 --- a/include/dt-bindings/thermal/thermal.h +++ b/include/dt-bindings/thermal/thermal.h @@ -1,10 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * This header provides constants for most thermal bindings. * * Copyright (C) 2013 Texas Instruments * Eduardo Valentin <eduardo.valentin(a)ti.com> - * - * GPLv2 only */ #ifndef _DT_BINDINGS_THERMAL_THERMAL_H -- 2.25.1

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[PATCH v2,RESEND] mmc: mtk-sd: increase the minimum bus frequency
by Weijie Gao 20 Apr '21

20 Apr '21

With a 48MHz input clock, the lowest bus frequency can be as low as 48000000 / (4 * 4095) = 2930Hz. Such an extremely low frequency will cause the mmc framework take seconds to finish the initialization. Limiting the minimum bus frequency to a slightly higher value can solve the issue without any side effects. Reviewed-by: Jaehoon Chung <jh80.chung(a)samsung.com> Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- drivers/mmc/mtk-sd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index 48a764be82..8599f095bc 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -232,6 +232,8 @@ #define SCLK_CYCLES_SHIFT 20 +#define MIN_BUS_CLK 200000 + #define CMD_INTS_MASK \ (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO) @@ -1639,6 +1641,9 @@ static int msdc_drv_probe(struct udevice *dev) else cfg->f_min = host->src_clk_freq / (4 * 4095); + if (cfg->f_min < MIN_BUS_CLK) + cfg->f_min = MIN_BUS_CLK; + if (cfg->f_max < cfg->f_min || cfg->f_max > host->src_clk_freq) cfg->f_max = host->src_clk_freq; -- 2.17.1

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[PATCH v2,RESEND] mmc: mtk-sd: increase the minimum bus frequency
by Weijie Gao 20 Apr '21

20 Apr '21

With a 48MHz input clock, the lowest bus frequency can be as low as 48000000 / (4 * 4095) = 2930Hz. Such an extremely low frequency will cause the mmc framework take seconds to finish the initialization. Limiting the minimum bus frequency to a slightly higher value can solve the issue without any side effects. Signed-off-by: Weijie Gao <weijie.gao(a)mediatek.com> --- drivers/mmc/mtk-sd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index 48a764be82..8599f095bc 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -232,6 +232,8 @@ #define SCLK_CYCLES_SHIFT 20 +#define MIN_BUS_CLK 200000 + #define CMD_INTS_MASK \ (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO) @@ -1639,6 +1641,9 @@ static int msdc_drv_probe(struct udevice *dev) else cfg->f_min = host->src_clk_freq / (4 * 4095); + if (cfg->f_min < MIN_BUS_CLK) + cfg->f_min = MIN_BUS_CLK; + if (cfg->f_max < cfg->f_min || cfg->f_max > host->src_clk_freq) cfg->f_max = host->src_clk_freq; -- 2.17.1

1 0

[PATCH] efi_loader: capsule: return a corret error code at find_boot_device()
by AKASHI Takahiro 20 Apr '21

20 Apr '21

In case of failure at efi_get_variable_int("BootOrder"), we should skip examining boot option variables and return an appropriate error code which is the one the function returned. Fixes: CID 331153 Code maintainability issues (UNUSED_VALUE) Signed-off-by: AKASHI Takahiro <takahiro.akashi(a)linaro.org> --- lib/efi_loader/efi_capsule.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index 691eda5e0d14..2d10f47bff24 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -685,7 +685,6 @@ skip: efi_free_pool(boot_dev); boot_dev = NULL; } -out: if (boot_dev) { u16 *path_str; @@ -703,6 +702,7 @@ out: } else { ret = EFI_NOT_FOUND; } +out: free(boot_order); return ret; -- 2.31.0

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